Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387579
A. Ahrens, W. Liu, S. Ng, V. Kühn, Lie-liang Yang, L. Hanzo
In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power allocation techniques are often optimized for maintaining both a fixed transmit power and a fixed target bit-error rate, while attempting to maximize the overall data-rate, albeit delay-critical real-time interactive applications, such as voice or video transmission, may require a fixed data rate. As an alternative design option, in addition to sophisticated joint bit- and power loading, in this contribution we invoke both coded modulation as well as channel prediction and identify the most beneficial number of modulation signalling levels, while minimizing the bit-error ratio under the constraints of a given fixed throughput. Our performance results show the superiority of bit-interleaved coded modulation using iterative decoding (BICM-ID) against turbo trellis-coded modulation (TTCM), regardless of using idealistic perfect or realistic imperfect channel state information (CSI).
{"title":"SVD-Aided, Iteratively Detected Spatial Division Multiplexing Using Long-Range Channel Prediction","authors":"A. Ahrens, W. Liu, S. Ng, V. Kühn, Lie-liang Yang, L. Hanzo","doi":"10.1109/SIPS.2007.4387579","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387579","url":null,"abstract":"In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power allocation techniques are often optimized for maintaining both a fixed transmit power and a fixed target bit-error rate, while attempting to maximize the overall data-rate, albeit delay-critical real-time interactive applications, such as voice or video transmission, may require a fixed data rate. As an alternative design option, in addition to sophisticated joint bit- and power loading, in this contribution we invoke both coded modulation as well as channel prediction and identify the most beneficial number of modulation signalling levels, while minimizing the bit-error ratio under the constraints of a given fixed throughput. Our performance results show the superiority of bit-interleaved coded modulation using iterative decoding (BICM-ID) against turbo trellis-coded modulation (TTCM), regardless of using idealistic perfect or realistic imperfect channel state information (CSI).","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"1 1","pages":"391-396"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80689087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387631
A. Bahari, T. Arslan, A. Erdogan
This paper presents a method to reduce the computation and memory access for variable-block-size motion estimation using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16×16 pixels) motion estimation. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyse the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full search method without significantly degrading picture quality.
{"title":"Low Computation and Memory Access for Variable Block Size Motion Estimation Using Pixel Truncation","authors":"A. Bahari, T. Arslan, A. Erdogan","doi":"10.1109/SIPS.2007.4387631","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387631","url":null,"abstract":"This paper presents a method to reduce the computation and memory access for variable-block-size motion estimation using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16×16 pixels) motion estimation. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyse the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full search method without significantly degrading picture quality.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"11 1","pages":"681-685"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72998215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387536
Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng
This paper proposes a two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack. Compared with previous parity-based CED methods, this scheme is able to detect errors in both horizontal and vertical direction in data matrix, therefore it has much higher fault coverage of multiple errors while remains 100% coverage of odd-bit errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than those of the traditional methods, whereas the critical path and throughput of this approach remain the same as the ones of traditional ways. It is a novel CED method for AES algorithm against differential fault attack, due to its high efficiency and low cost.
{"title":"Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation","authors":"Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng","doi":"10.1109/SIPS.2007.4387536","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387536","url":null,"abstract":"This paper proposes a two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack. Compared with previous parity-based CED methods, this scheme is able to detect errors in both horizontal and vertical direction in data matrix, therefore it has much higher fault coverage of multiple errors while remains 100% coverage of odd-bit errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than those of the traditional methods, whereas the critical path and throughput of this approach remain the same as the ones of traditional ways. It is a novel CED method for AES algorithm against differential fault attack, due to its high efficiency and low cost.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"8 1","pages":"151-156"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76075539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387569
Shenyuan Li, Sheng Fang, Zhe Li
Distributed video coding (DVC) is a new compression method based on two key information theory results: Slepian-Wolf and Wyner-Ziv theorems. In this paper, we proposed a Wyner-Ziv video coding scheme based on wavelet transform and set-partition in hierarchical trees (SPIHT) which can exploit the spatial, temporal and statistical correlations of the frame sequence. In our scheme, we use Discrete Wavelet Transform (DWT) before quantization, then only coefficients of low frequency subband are Wyner-Ziv encoded using turbo codes, and all coefficients of high frequency subbands in these frames are coded by the SPIHT algorithm. At the decoder, side-information generated through interpolation was used to conditionally decode the Wyner-Ziv frames. Obtained results show that proposed scheme performs better than intra coding scheme only used SPIHT algorithm especially in terms of decoding efficiency at a correspondingly low bit rate.
{"title":"Wyner-Ziv Video Coding for Low Bitrate Using Spiht Algorithm","authors":"Shenyuan Li, Sheng Fang, Zhe Li","doi":"10.1109/SIPS.2007.4387569","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387569","url":null,"abstract":"Distributed video coding (DVC) is a new compression method based on two key information theory results: Slepian-Wolf and Wyner-Ziv theorems. In this paper, we proposed a Wyner-Ziv video coding scheme based on wavelet transform and set-partition in hierarchical trees (SPIHT) which can exploit the spatial, temporal and statistical correlations of the frame sequence. In our scheme, we use Discrete Wavelet Transform (DWT) before quantization, then only coefficients of low frequency subband are Wyner-Ziv encoded using turbo codes, and all coefficients of high frequency subbands in these frames are coded by the SPIHT algorithm. At the decoder, side-information generated through interpolation was used to conditionally decode the Wyner-Ziv frames. Obtained results show that proposed scheme performs better than intra coding scheme only used SPIHT algorithm especially in terms of decoding efficiency at a correspondingly low bit rate.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"102 1","pages":"341-345"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79591972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387610
Zhao Fucai, Huang Yihua
To make the modulation classification system more suitable for signals in a wide range of signal to noise ratio (SNR), a feature extraction method based on signal wavelet packet transform modulus maxima matrix (WPTMMM) and a novel Support Vector Machine Fuzzy Network (SVMFN) classifier is presented in this paper. The WPTMMM feature extraction method has less computational complexity, more stability and has the outstanding advantage of robust with the time and white noise. Further, the SVMFN employs a new definition of fuzzy density which incorporates accuracy and uncertainty of the classifiers to improve recognition reliability to classify nine digital modulation types (i.e. 2ASK, 2FSK, 2PSK, 4ASK, 4FSK, 4PSK, 16QAM, MSK and OQPSK). Computer simulation shows that the proposed scheme has the advantages of high accuracy and reliability (success rates are over 98% when SNR is not lower than 0dB), and adapt to engineering applications.
{"title":"Classification Using Wavelet Packet Decomposition and SVM Fuzzy Network for Digital Modulations in Satellite Communication","authors":"Zhao Fucai, Huang Yihua","doi":"10.1109/SIPS.2007.4387610","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387610","url":null,"abstract":"To make the modulation classification system more suitable for signals in a wide range of signal to noise ratio (SNR), a feature extraction method based on signal wavelet packet transform modulus maxima matrix (WPTMMM) and a novel Support Vector Machine Fuzzy Network (SVMFN) classifier is presented in this paper. The WPTMMM feature extraction method has less computational complexity, more stability and has the outstanding advantage of robust with the time and white noise. Further, the SVMFN employs a new definition of fuzzy density which incorporates accuracy and uncertainty of the classifiers to improve recognition reliability to classify nine digital modulation types (i.e. 2ASK, 2FSK, 2PSK, 4ASK, 4FSK, 4PSK, 16QAM, MSK and OQPSK). Computer simulation shows that the proposed scheme has the advantages of high accuracy and reliability (success rates are over 98% when SNR is not lower than 0dB), and adapt to engineering applications.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"13 1","pages":"562-566"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75361476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387510
Min Li, J. Absar, B. Bougard, L. Perre, F. Catthoor
Orthogonal-Triangular Decomposition (QRD) is one of the most fundamental signal processing primitives based on complex matrix operations [1]. It forms the core of many advanced multi-dimension and statistical signal processing algorithms that utilize orthogonalization, projection, and rank-revealing principles. Especially in the domain of wireless signal processing, many emerging algorithms in MIMO and OFDM systems have explicit or implicit connections to QRD [2]. This paper is about the systematic optimization of QRD implementation on programmable architectures. Based on the analysis of existing works, we introduce the following higher level components to the new optimization methodology: (1) Exploring high level algorithmic alternatives. (2) Categorizing different application scenarios. (3) Merging cascaded matrix operations. The systematic optimization brings significant improvements for programmable QRD implementations. Comparing to the widely accepted implementation in Numerical Receipts [3], our work achieves up to 79.76% cycle count reduction on TI TMS320C6713, a typical VLIW DSP. Moreover, our work achieves remarkable improvement on the memory subsystem, which is very critical for the power consumption and performance of modern DSP. Specifically, when QRD is used to solve least-square linear equations, our work reduces 99.55% LIP misses and 96.52% LID misses for 32×32 equations.
{"title":"Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios","authors":"Min Li, J. Absar, B. Bougard, L. Perre, F. Catthoor","doi":"10.1109/SIPS.2007.4387510","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387510","url":null,"abstract":"Orthogonal-Triangular Decomposition (QRD) is one of the most fundamental signal processing primitives based on complex matrix operations [1]. It forms the core of many advanced multi-dimension and statistical signal processing algorithms that utilize orthogonalization, projection, and rank-revealing principles. Especially in the domain of wireless signal processing, many emerging algorithms in MIMO and OFDM systems have explicit or implicit connections to QRD [2]. This paper is about the systematic optimization of QRD implementation on programmable architectures. Based on the analysis of existing works, we introduce the following higher level components to the new optimization methodology: (1) Exploring high level algorithmic alternatives. (2) Categorizing different application scenarios. (3) Merging cascaded matrix operations. The systematic optimization brings significant improvements for programmable QRD implementations. Comparing to the widely accepted implementation in Numerical Receipts [3], our work achieves up to 79.76% cycle count reduction on TI TMS320C6713, a typical VLIW DSP. Moreover, our work achieves remarkable improvement on the memory subsystem, which is very critical for the power consumption and performance of modern DSP. Specifically, when QRD is used to solve least-square linear equations, our work reduces 99.55% LIP misses and 96.52% LID misses for 32×32 equations.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"15 3 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76237956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387539
Wonchul Lee, Hyojin Choi, Wonyong Sung
Variable block size motion estimation (ME) is one of the new coding tools for H.264/AVC encoder to enhance the video performance. However, the complexity of the variable block size ME is very high because the motion estimation and rate-distortion optimization need to be performed repeatedly for all the possible block mode combinations. In order to reduce this, we propose a new block mode decision algorithm, which can decide the block mode efficiently without trying all the block modes by using the spatial property of image sequences. The experimental results on a VLIW (Very Long Instruction Word) ¿ SIMD (Single Instruction Multiple Data) programmable digital signal processor (DSP) show that the proposed algorithm can save the CPU clock cycles by 47% for the integer-pel ME and 83% for the sub-pel ME. The video performance degradation in terms of PSNR and bitrates is 0.12 dB and 1.04%, respectively.
{"title":"Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor","authors":"Wonchul Lee, Hyojin Choi, Wonyong Sung","doi":"10.1109/SIPS.2007.4387539","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387539","url":null,"abstract":"Variable block size motion estimation (ME) is one of the new coding tools for H.264/AVC encoder to enhance the video performance. However, the complexity of the variable block size ME is very high because the motion estimation and rate-distortion optimization need to be performed repeatedly for all the possible block mode combinations. In order to reduce this, we propose a new block mode decision algorithm, which can decide the block mode efficiently without trying all the block modes by using the spatial property of image sequences. The experimental results on a VLIW (Very Long Instruction Word) ¿ SIMD (Single Instruction Multiple Data) programmable digital signal processor (DSP) show that the proposed algorithm can save the CPU clock cycles by 47% for the integer-pel ME and 83% for the sub-pel ME. The video performance degradation in terms of PSNR and bitrates is 0.12 dB and 1.04%, respectively.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"74 1","pages":"169-174"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83734554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387624
K. Seki, T. Kobori, J. Okello, M. Ikekawa
A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor's performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.
{"title":"A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications","authors":"K. Seki, T. Kobori, J. Okello, M. Ikekawa","doi":"10.1109/SIPS.2007.4387624","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387624","url":null,"abstract":"A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor's performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"45 1","pages":"639-644"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83321603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387615
Xin Lu, K. Nishiyama
This paper discusses the dependability of the maximum like-lihood estimator (MLE) when the dynamical model is specified as vector autoregression (VAR). When the size of the data vector in VAR is enlarged a little, the distributions of the estimates by the MLE become too wide to satisfy the precision requirement. Consequently, it is necessary to largely increase the length of the tested data for sharpening the distributions and obtaining the suitable estimates. In this paper, we give an explanation of this phenomenon and analyze the convergence relation of each parameter.
{"title":"Dependability of Unstructured Estimator in Vector Autoregression Identification","authors":"Xin Lu, K. Nishiyama","doi":"10.1109/SIPS.2007.4387615","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387615","url":null,"abstract":"This paper discusses the dependability of the maximum like-lihood estimator (MLE) when the dynamical model is specified as vector autoregression (VAR). When the size of the data vector in VAR is enlarged a little, the distributions of the estimates by the MLE become too wide to satisfy the precision requirement. Consequently, it is necessary to largely increase the length of the tested data for sharpening the distributions and obtaining the suitable estimates. In this paper, we give an explanation of this phenomenon and analyze the convergence relation of each parameter.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"37 1","pages":"589-594"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85187594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387541
Seonyoung Lee, Kyeongsoon Cho
This paper presents a new method to design the circuit that can perform the inverse transform and inverse quantization operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed the integrated inverse quantization circuit using a shared multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the circuit size.
{"title":"Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder","authors":"Seonyoung Lee, Kyeongsoon Cho","doi":"10.1109/SIPS.2007.4387541","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387541","url":null,"abstract":"This paper presents a new method to design the circuit that can perform the inverse transform and inverse quantization operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed the integrated inverse quantization circuit using a shared multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the circuit size.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"202 1","pages":"181-186"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72930668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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