Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387569
Shenyuan Li, Sheng Fang, Zhe Li
Distributed video coding (DVC) is a new compression method based on two key information theory results: Slepian-Wolf and Wyner-Ziv theorems. In this paper, we proposed a Wyner-Ziv video coding scheme based on wavelet transform and set-partition in hierarchical trees (SPIHT) which can exploit the spatial, temporal and statistical correlations of the frame sequence. In our scheme, we use Discrete Wavelet Transform (DWT) before quantization, then only coefficients of low frequency subband are Wyner-Ziv encoded using turbo codes, and all coefficients of high frequency subbands in these frames are coded by the SPIHT algorithm. At the decoder, side-information generated through interpolation was used to conditionally decode the Wyner-Ziv frames. Obtained results show that proposed scheme performs better than intra coding scheme only used SPIHT algorithm especially in terms of decoding efficiency at a correspondingly low bit rate.
{"title":"Wyner-Ziv Video Coding for Low Bitrate Using Spiht Algorithm","authors":"Shenyuan Li, Sheng Fang, Zhe Li","doi":"10.1109/SIPS.2007.4387569","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387569","url":null,"abstract":"Distributed video coding (DVC) is a new compression method based on two key information theory results: Slepian-Wolf and Wyner-Ziv theorems. In this paper, we proposed a Wyner-Ziv video coding scheme based on wavelet transform and set-partition in hierarchical trees (SPIHT) which can exploit the spatial, temporal and statistical correlations of the frame sequence. In our scheme, we use Discrete Wavelet Transform (DWT) before quantization, then only coefficients of low frequency subband are Wyner-Ziv encoded using turbo codes, and all coefficients of high frequency subbands in these frames are coded by the SPIHT algorithm. At the decoder, side-information generated through interpolation was used to conditionally decode the Wyner-Ziv frames. Obtained results show that proposed scheme performs better than intra coding scheme only used SPIHT algorithm especially in terms of decoding efficiency at a correspondingly low bit rate.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"102 1","pages":"341-345"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79591972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387539
Wonchul Lee, Hyojin Choi, Wonyong Sung
Variable block size motion estimation (ME) is one of the new coding tools for H.264/AVC encoder to enhance the video performance. However, the complexity of the variable block size ME is very high because the motion estimation and rate-distortion optimization need to be performed repeatedly for all the possible block mode combinations. In order to reduce this, we propose a new block mode decision algorithm, which can decide the block mode efficiently without trying all the block modes by using the spatial property of image sequences. The experimental results on a VLIW (Very Long Instruction Word) ¿ SIMD (Single Instruction Multiple Data) programmable digital signal processor (DSP) show that the proposed algorithm can save the CPU clock cycles by 47% for the integer-pel ME and 83% for the sub-pel ME. The video performance degradation in terms of PSNR and bitrates is 0.12 dB and 1.04%, respectively.
{"title":"Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor","authors":"Wonchul Lee, Hyojin Choi, Wonyong Sung","doi":"10.1109/SIPS.2007.4387539","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387539","url":null,"abstract":"Variable block size motion estimation (ME) is one of the new coding tools for H.264/AVC encoder to enhance the video performance. However, the complexity of the variable block size ME is very high because the motion estimation and rate-distortion optimization need to be performed repeatedly for all the possible block mode combinations. In order to reduce this, we propose a new block mode decision algorithm, which can decide the block mode efficiently without trying all the block modes by using the spatial property of image sequences. The experimental results on a VLIW (Very Long Instruction Word) ¿ SIMD (Single Instruction Multiple Data) programmable digital signal processor (DSP) show that the proposed algorithm can save the CPU clock cycles by 47% for the integer-pel ME and 83% for the sub-pel ME. The video performance degradation in terms of PSNR and bitrates is 0.12 dB and 1.04%, respectively.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"74 1","pages":"169-174"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83734554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387583
Kyung-Ju Cho, Yinan Xu, Jin-Gyun Chung
This paper presents a QR decomposition core by exploiting Givens rotation for the generalized decision feedback equalizer (GDFE). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining the fixed-width modified-Booth multiplier and two-stage method (coarse and fine stage), we design an efficient QR decomposition core. By simulations, it is shown that the proposed QR decomposition core can be a feasible solution for GDFE.
{"title":"Hardware Efficient QR Decomposition for GDFE","authors":"Kyung-Ju Cho, Yinan Xu, Jin-Gyun Chung","doi":"10.1109/SIPS.2007.4387583","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387583","url":null,"abstract":"This paper presents a QR decomposition core by exploiting Givens rotation for the generalized decision feedback equalizer (GDFE). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining the fixed-width modified-Booth multiplier and two-stage method (coarse and fine stage), we design an efficient QR decomposition core. By simulations, it is shown that the proposed QR decomposition core can be a feasible solution for GDFE.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"62 1","pages":"412-417"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85055291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387545
Chang-Seok Choi, Hanho Lee
This paper presents a self-reconfigurable adaptive FIR Filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, configuration time advantage allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for realization and autonomous adaptation of FIR filters, and processes the optimal digital signal processing algorithms, which are the low-pass, band-pass and high-pass filter algorithms with various frequencies, for noise removal operations. The proposed stand-alone self-reconfigurable system using Xilinx Virtex4 FPGA and Compact-Flash memory shows the improvement of configuration time and flexibility by using the dynamic partial reconfiguration techniques.
{"title":"A Partial Self-Reconfigurable Adaptive FIR Filter System","authors":"Chang-Seok Choi, Hanho Lee","doi":"10.1109/SIPS.2007.4387545","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387545","url":null,"abstract":"This paper presents a self-reconfigurable adaptive FIR Filter system design using dynamic partial reconfiguration, which has flexibility, power efficiency, configuration time advantage allowing dynamically inserting or removing adaptive FIR filter modules. This self-reconfigurable adaptive FIR filter is responsible for providing the best solution for realization and autonomous adaptation of FIR filters, and processes the optimal digital signal processing algorithms, which are the low-pass, band-pass and high-pass filter algorithms with various frequencies, for noise removal operations. The proposed stand-alone self-reconfigurable system using Xilinx Virtex4 FPGA and Compact-Flash memory shows the improvement of configuration time and flexibility by using the dynamic partial reconfiguration techniques.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2 1","pages":"204-209"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90605599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387629
Dimitris Gkrimpas, Vassilis Paliouras
This paper investigates the combined computational complexity of demodulation and decoding of QAM signals. Four combinations of demodulation and decoding techniques are compared in terms of bit error rate (BER) vs. signal-to-noise (SNR) behavior, finite word length effects, and hardware complexity. It is found that joint demodulation and decoding using a high-radix trellis can be more efficient for higher orders of modulation, while a decoding strategy which produces soft values, followed by a Viterbi decoder is more efficient for lower modulation orders. Complexity formulas that take into account word lengths and modulation order are introduced.
{"title":"On The Complexity of Joint Demodulation and Convolutional Decoding","authors":"Dimitris Gkrimpas, Vassilis Paliouras","doi":"10.1109/SIPS.2007.4387629","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387629","url":null,"abstract":"This paper investigates the combined computational complexity of demodulation and decoding of QAM signals. Four combinations of demodulation and decoding techniques are compared in terms of bit error rate (BER) vs. signal-to-noise (SNR) behavior, finite word length effects, and hardware complexity. It is found that joint demodulation and decoding using a high-radix trellis can be more efficient for higher orders of modulation, while a decoding strategy which produces soft values, followed by a Viterbi decoder is more efficient for lower modulation orders. Complexity formulas that take into account word lengths and modulation order are introduced.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"34 1","pages":"669-674"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87136807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387536
Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng
This paper proposes a two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack. Compared with previous parity-based CED methods, this scheme is able to detect errors in both horizontal and vertical direction in data matrix, therefore it has much higher fault coverage of multiple errors while remains 100% coverage of odd-bit errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than those of the traditional methods, whereas the critical path and throughput of this approach remain the same as the ones of traditional ways. It is a novel CED method for AES algorithm against differential fault attack, due to its high efficiency and low cost.
{"title":"Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation","authors":"Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng","doi":"10.1109/SIPS.2007.4387536","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387536","url":null,"abstract":"This paper proposes a two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack. Compared with previous parity-based CED methods, this scheme is able to detect errors in both horizontal and vertical direction in data matrix, therefore it has much higher fault coverage of multiple errors while remains 100% coverage of odd-bit errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than those of the traditional methods, whereas the critical path and throughput of this approach remain the same as the ones of traditional ways. It is a novel CED method for AES algorithm against differential fault attack, due to its high efficiency and low cost.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"8 1","pages":"151-156"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76075539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387573
Maria Pantoja, N. Ling, Weijia Shang
This paper discusses the problem of transcoding between VC-1 and H.264 video standards. VC-1 uses an adaptive block size integer transform, which is different from the 4×4 integer transform used by H.264. We propose an algorithm to transcode the transform coefficients from VC-1 to those for H.264, which is a fundamental step for transform domain transcoding. The paper also presents a fast computation version of the algorithm. The implementation of the proposed algorithm shows that the quality of the video remains roughly the same while the complexity is greatly reduced when compared with the reference full cascade pixel domain transcoder.
{"title":"Coefficient Conversion for Transform Domain VC-1 TO H.264 Transcoding","authors":"Maria Pantoja, N. Ling, Weijia Shang","doi":"10.1109/SIPS.2007.4387573","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387573","url":null,"abstract":"This paper discusses the problem of transcoding between VC-1 and H.264 video standards. VC-1 uses an adaptive block size integer transform, which is different from the 4×4 integer transform used by H.264. We propose an algorithm to transcode the transform coefficients from VC-1 to those for H.264, which is a fundamental step for transform domain transcoding. The paper also presents a fast computation version of the algorithm. The implementation of the proposed algorithm shows that the quality of the video remains roughly the same while the complexity is greatly reduced when compared with the reference full cascade pixel domain transcoder.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"21 1","pages":"363-367"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90729062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387624
K. Seki, T. Kobori, J. Okello, M. Ikekawa
A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor's performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.
{"title":"A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications","authors":"K. Seki, T. Kobori, J. Okello, M. Ikekawa","doi":"10.1109/SIPS.2007.4387624","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387624","url":null,"abstract":"A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor's performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"45 1","pages":"639-644"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83321603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387579
A. Ahrens, W. Liu, S. Ng, V. Kühn, Lie-liang Yang, L. Hanzo
In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power allocation techniques are often optimized for maintaining both a fixed transmit power and a fixed target bit-error rate, while attempting to maximize the overall data-rate, albeit delay-critical real-time interactive applications, such as voice or video transmission, may require a fixed data rate. As an alternative design option, in addition to sophisticated joint bit- and power loading, in this contribution we invoke both coded modulation as well as channel prediction and identify the most beneficial number of modulation signalling levels, while minimizing the bit-error ratio under the constraints of a given fixed throughput. Our performance results show the superiority of bit-interleaved coded modulation using iterative decoding (BICM-ID) against turbo trellis-coded modulation (TTCM), regardless of using idealistic perfect or realistic imperfect channel state information (CSI).
{"title":"SVD-Aided, Iteratively Detected Spatial Division Multiplexing Using Long-Range Channel Prediction","authors":"A. Ahrens, W. Liu, S. Ng, V. Kühn, Lie-liang Yang, L. Hanzo","doi":"10.1109/SIPS.2007.4387579","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387579","url":null,"abstract":"In this contribution iteratively detected spatial division multiplexing is investigated under the constraint of a fixed data throughput. Existing bit loading and transmit power allocation techniques are often optimized for maintaining both a fixed transmit power and a fixed target bit-error rate, while attempting to maximize the overall data-rate, albeit delay-critical real-time interactive applications, such as voice or video transmission, may require a fixed data rate. As an alternative design option, in addition to sophisticated joint bit- and power loading, in this contribution we invoke both coded modulation as well as channel prediction and identify the most beneficial number of modulation signalling levels, while minimizing the bit-error ratio under the constraints of a given fixed throughput. Our performance results show the superiority of bit-interleaved coded modulation using iterative decoding (BICM-ID) against turbo trellis-coded modulation (TTCM), regardless of using idealistic perfect or realistic imperfect channel state information (CSI).","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"1 1","pages":"391-396"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80689087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387541
Seonyoung Lee, Kyeongsoon Cho
This paper presents a new method to design the circuit that can perform the inverse transform and inverse quantization operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed the integrated inverse quantization circuit using a shared multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the circuit size.
{"title":"Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder","authors":"Seonyoung Lee, Kyeongsoon Cho","doi":"10.1109/SIPS.2007.4387541","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387541","url":null,"abstract":"This paper presents a new method to design the circuit that can perform the inverse transform and inverse quantization operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed the integrated inverse quantization circuit using a shared multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the circuit size.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"202 1","pages":"181-186"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72930668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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