Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387518
Guoguang Chen, R. Ansari
The integration of Orthogonal Frequency Division Multiplexing (OFDM) into Multiple Input Multiple Output (MIMO) systems is regarded as a promising technology to provide high performance in fourth generation (4G) broadband wireless communication systems. However, the inherent drawback of large Peak-to-Average Power Ratio (PAPR) for OFDM carries over to MIMO systems. This paper examines the use of Erasure Pattern Selection (EPS) developed for Single Input Single Output (SISO) systems for the task of reducing PAPR in MIMO-OFDM systems. A MIMO-EPS scheme is proposed for minimizing the peak power value over all antennas, which is shown to produce a PAPR reduction gain around 1.5dB for 2 transmit antennas compared with the conventional MIMO-OFDM. The scheme is analyzed to show its significant performance advantages and lower computational complexity compared with an existing SeLective Mapping (SLM) scheme.
{"title":"Frame Expansion Based Peak to Average Power Ratio Reduction in MIMO OFDM Systems","authors":"Guoguang Chen, R. Ansari","doi":"10.1109/SIPS.2007.4387518","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387518","url":null,"abstract":"The integration of Orthogonal Frequency Division Multiplexing (OFDM) into Multiple Input Multiple Output (MIMO) systems is regarded as a promising technology to provide high performance in fourth generation (4G) broadband wireless communication systems. However, the inherent drawback of large Peak-to-Average Power Ratio (PAPR) for OFDM carries over to MIMO systems. This paper examines the use of Erasure Pattern Selection (EPS) developed for Single Input Single Output (SISO) systems for the task of reducing PAPR in MIMO-OFDM systems. A MIMO-EPS scheme is proposed for minimizing the peak power value over all antennas, which is shown to produce a PAPR reduction gain around 1.5dB for 2 transmit antennas compared with the conventional MIMO-OFDM. The scheme is analyzed to show its significant performance advantages and lower computational complexity compared with an existing SeLective Mapping (SLM) scheme.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"3 1","pages":"61-66"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88911824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387603
Zhengguo Li, W. Yao, S. Rahardja, S. Xie
In this paper, a new framework is proposed for the encoder optimization of scalable video coding (SVC). It is used to provide guidelines for the design of rate control and fast mode decision at the base layer and base layer selection at enhancement layer for the SVC. It is also pointed out that the coding technology of inter-layer prediction with two base layers is desired for the combined coarse granular scalability and spatial scalability such that the coding efficiency losses at layers with higher resolution are about 10% when compared to the corresponding single-layer video coding.
{"title":"New Framework for Encoder Optimization of Scalable Video Coding","authors":"Zhengguo Li, W. Yao, S. Rahardja, S. Xie","doi":"10.1109/SIPS.2007.4387603","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387603","url":null,"abstract":"In this paper, a new framework is proposed for the encoder optimization of scalable video coding (SVC). It is used to provide guidelines for the design of rate control and fast mode decision at the base layer and base layer selection at enhancement layer for the SVC. It is also pointed out that the coding technology of inter-layer prediction with two base layers is desired for the combined coarse granular scalability and spatial scalability such that the coding efficiency losses at layers with higher resolution are about 10% when compared to the corresponding single-layer video coding.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"67 1","pages":"527-532"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78247708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387611
T. Tsai, Chung-Yuan Lin
The task of automatic gesture segmentation is highly challenging due to the computational burden, the presence of unpredictable body motion and ambiguous nongesture hand motion. In this paper, a new approach is developed using Hausdorff based model tracking technique for the application of real-time human-computer interaction. This paper proposed a Three Phases Model Tracking approach, which consists of two main stages; one is motion history analysis, which classifies dynamic gesture into preparation, retraction and nucleus state based on temporal relationship. The other is model tracking, which tracks signer model and object model with different constraint based on the classified state. Finally, gesture model is extracted based on matching object model and signer model and the hand gesture region is segmented from the gesture model. Experiments are performed to test the robustness of gesture segmentation under various hand scale and complex background. The segmentation error rate and computational complexity are also analyzed to demonstrate that the proposed Three Phases Model Tracking approach can be applicable to real-time human-computer interaction system.
{"title":"Visual Hand Gesture Segmentation Using Signer Model for Real-Time Human-Computer Interaction Application","authors":"T. Tsai, Chung-Yuan Lin","doi":"10.1109/SIPS.2007.4387611","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387611","url":null,"abstract":"The task of automatic gesture segmentation is highly challenging due to the computational burden, the presence of unpredictable body motion and ambiguous nongesture hand motion. In this paper, a new approach is developed using Hausdorff based model tracking technique for the application of real-time human-computer interaction. This paper proposed a Three Phases Model Tracking approach, which consists of two main stages; one is motion history analysis, which classifies dynamic gesture into preparation, retraction and nucleus state based on temporal relationship. The other is model tracking, which tracks signer model and object model with different constraint based on the classified state. Finally, gesture model is extracted based on matching object model and signer model and the hand gesture region is segmented from the gesture model. Experiments are performed to test the robustness of gesture segmentation under various hand scale and complex background. The segmentation error rate and computational complexity are also analyzed to demonstrate that the proposed Three Phases Model Tracking approach can be applicable to real-time human-computer interaction system.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"14 1","pages":"567-572"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91104258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387538
Hoseok Chang, Youngjoon Lee, Wonyong Sung
We conducted a mobile platform specific software and system optimization for an open-source multimedia player, MPlayer. The target system is based on the Intel XScale PXA270 CPU. The optimization process consists of 4 steps: utilizing the color conversion hardware, adopting SIMD optimization, increasing the external memory access speed, and exploiting the internal memory. At each optimization step, we measured the execution time, cache miss characteristics, and power consumption. The experimental results with a QVGA-sized MPEG4 movie clip show that hardware based color conversion and SIMD optimization bring about 19.2% and 27.6% of execution time reduction, respectively, while increasing the external memory access speed and utilizing the internal memory result in 35.9% additional execution time reduction. The results show that it is important to break the memory bus bottleneck by using faster data bus settings and exploiting internal SRAM.
{"title":"Performance Optimization of a Multimedia Player on a Mobile CPU Platform","authors":"Hoseok Chang, Youngjoon Lee, Wonyong Sung","doi":"10.1109/SIPS.2007.4387538","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387538","url":null,"abstract":"We conducted a mobile platform specific software and system optimization for an open-source multimedia player, MPlayer. The target system is based on the Intel XScale PXA270 CPU. The optimization process consists of 4 steps: utilizing the color conversion hardware, adopting SIMD optimization, increasing the external memory access speed, and exploiting the internal memory. At each optimization step, we measured the execution time, cache miss characteristics, and power consumption. The experimental results with a QVGA-sized MPEG4 movie clip show that hardware based color conversion and SIMD optimization bring about 19.2% and 27.6% of execution time reduction, respectively, while increasing the external memory access speed and utilizing the internal memory result in 35.9% additional execution time reduction. The results show that it is important to break the memory bus bottleneck by using faster data bus settings and exploiting internal SRAM.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"21 1","pages":"163-168"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82654277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387614
Lu Yang, S. Attallah
In this paper, we propose a new optimal diagonal-matrix step-size for the fast data projection method (FDPM) algorithm. The proposed step-sizes control the decoupled subspace vectors individually as compared to conventional methods where all the subspace vectors are multiplied by the same step-size value (scalar case). Simulation results show that FDPM with this optimal diagonal-matrix step-size outperforms the original algorithm as it offers faster convergence rate, smaller steady state error and smaller orthogonality error simultaneously. The proposed method can easily be applied to other subspace algorithms as well.
{"title":"Adaptive Noise Subspace Estimation Algorithm with an Optimal Diagonal-Matrix Step-Size","authors":"Lu Yang, S. Attallah","doi":"10.1109/SIPS.2007.4387614","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387614","url":null,"abstract":"In this paper, we propose a new optimal diagonal-matrix step-size for the fast data projection method (FDPM) algorithm. The proposed step-sizes control the decoupled subspace vectors individually as compared to conventional methods where all the subspace vectors are multiplied by the same step-size value (scalar case). Simulation results show that FDPM with this optimal diagonal-matrix step-size outperforms the original algorithm as it offers faster convergence rate, smaller steady state error and smaller orthogonality error simultaneously. The proposed method can easily be applied to other subspace algorithms as well.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2 1","pages":"584-588"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87419263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387531
G. Varatkar, Naresh R Shanbhag
In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference(MSAD) block is employed for detecting and correcting errors in the MSAD block. This architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio (PSNR) of ISR-ANT architecture increases by up to 1.8dB over that of the conventional architecture in 130nm IBM process technology. Furthermore, the PSNR variation is also reduced by 7× over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.
{"title":"Variation-Tolerant Motion Estimation Architecture","authors":"G. Varatkar, Naresh R Shanbhag","doi":"10.1109/SIPS.2007.4387531","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387531","url":null,"abstract":"In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference(MSAD) block is employed for detecting and correcting errors in the MSAD block. This architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio (PSNR) of ISR-ANT architecture increases by up to 1.8dB over that of the conventional architecture in 130nm IBM process technology. Furthermore, the PSNR variation is also reduced by 7× over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2 1","pages":"126-131"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83682100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387585
L. Aksoy, Ece Olcay Günes, E. Costa, P. Flores, J. Monteiro
In this work, we analyze the effect of representing constants under binary, CSD, and MSD representations on the minimum number of operations required in a multiple constant multiplications problem. To this end, we resort to a recently proposed algorithm that computes the exact minimum solution. To extend the applicability of this algorithm to much larger instances, we propose problem reduction and model simplification techniques that significantly reduce the search space. We have conducted experiments on a rich set of instances including randomly generated and FIR filter instances. The results show that, contrary to common belief, the binary representation clearly yields better solutions than CSD, and even provides slightly better solutions than MSD. Moreover, the superiority of the binary solutions increases as the number and bit-width of the constants increase.
{"title":"Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications","authors":"L. Aksoy, Ece Olcay Günes, E. Costa, P. Flores, J. Monteiro","doi":"10.1109/SIPS.2007.4387585","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387585","url":null,"abstract":"In this work, we analyze the effect of representing constants under binary, CSD, and MSD representations on the minimum number of operations required in a multiple constant multiplications problem. To this end, we resort to a recently proposed algorithm that computes the exact minimum solution. To extend the applicability of this algorithm to much larger instances, we propose problem reduction and model simplification techniques that significantly reduce the search space. We have conducted experiments on a rich set of instances including randomly generated and FIR filter instances. The results show that, contrary to common belief, the binary representation clearly yields better solutions than CSD, and even provides slightly better solutions than MSD. Moreover, the superiority of the binary solutions increases as the number and bit-width of the constants increase.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"14 1","pages":"424-429"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86340555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387568
Zhu Gang, Yang Ping, Yun He
Multi-view Video Coding (MVC) is a fundamental encoding technique for FTV (free-viewpoint television), 3DTV (3D television) and surveillance. Efficient MVC requires coding algorithms exploiting temporal as well as inter-view dependencies between cameras. Assisted by the camera parameters the inter-view dependencies can be properly utilized. We propose in this paper a new inter-view prediction method based on camera parameters. The comparative test results based on the JSVM software platform are shown.
{"title":"A New Inter-View Prediction Method for Multi-View Video Coding","authors":"Zhu Gang, Yang Ping, Yun He","doi":"10.1109/SIPS.2007.4387568","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387568","url":null,"abstract":"Multi-view Video Coding (MVC) is a fundamental encoding technique for FTV (free-viewpoint television), 3DTV (3D television) and surveillance. Efficient MVC requires coding algorithms exploiting temporal as well as inter-view dependencies between cameras. Assisted by the camera parameters the inter-view dependencies can be properly utilized. We propose in this paper a new inter-view prediction method based on camera parameters. The comparative test results based on the JSVM software platform are shown.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2016 1","pages":"337-340"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86583465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387558
G. Song, W. Zhuang, Zhigang Wei, Aiguo Song
In order to better control the mobile nodes in wireless sensor networks, an effective navigation algorithm is proposed in this paper. The static nodes are used as beacons. The methods of topology credits and TDOA (time difference of arrival) are adopted. Credits of nodes are used to create topology of the networks. Meanwhile, the TDOA method is used to calculate the distance of neighbor nodes to determine the next turning angle. Simulation and experimental results show that the proposed algorithm is effective in navigating the mobile nodes precisely to the region of interest. The comparison between the proposed algorithm and the VFF (virtual force field) method shows that the former has better performance in guiding mobile nodes in wireless sensor networks.
{"title":"An Effective Algorithm for Guiding Mobile Nodes in Wireless Sensor Networks","authors":"G. Song, W. Zhuang, Zhigang Wei, Aiguo Song","doi":"10.1109/SIPS.2007.4387558","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387558","url":null,"abstract":"In order to better control the mobile nodes in wireless sensor networks, an effective navigation algorithm is proposed in this paper. The static nodes are used as beacons. The methods of topology credits and TDOA (time difference of arrival) are adopted. Credits of nodes are used to create topology of the networks. Meanwhile, the TDOA method is used to calculate the distance of neighbor nodes to determine the next turning angle. Simulation and experimental results show that the proposed algorithm is effective in navigating the mobile nodes precisely to the region of interest. The comparison between the proposed algorithm and the VFF (virtual force field) method shows that the former has better performance in guiding mobile nodes in wireless sensor networks.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"123 1","pages":"279-282"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75743010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387594
P. Salmela, Chung-Ching Shen, S. Bhattacharyya, J. Takala
The implementation of real-time signal processing applications calls for parallelism to avoid unpractical clock frequencies and to lower power consumption. In this paper, a method for exploring the design space of parallel elementary computing resources is proposed. The method can be used to find a suitable set of computing resources for processors applying instruction level parallelism (ILP) or pure hardware designs. The extensive size of the design space is coped with coarse level modeling and evaluation. The method presents the system as a union of multisets of computing resources. This formulation provides a general framework for efficient, multi-objective optimization in terms of relevant cost metrics, including processing latency, area, and power consumption. We demonstrate this framework by developing a multiobjective evolutionary algorithm based on it, and applying this algorithm to a rake receiver application.
{"title":"Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations","authors":"P. Salmela, Chung-Ching Shen, S. Bhattacharyya, J. Takala","doi":"10.1109/SIPS.2007.4387594","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387594","url":null,"abstract":"The implementation of real-time signal processing applications calls for parallelism to avoid unpractical clock frequencies and to lower power consumption. In this paper, a method for exploring the design space of parallel elementary computing resources is proposed. The method can be used to find a suitable set of computing resources for processors applying instruction level parallelism (ILP) or pure hardware designs. The extensive size of the design space is coped with coarse level modeling and evaluation. The method presents the system as a union of multisets of computing resources. This formulation provides a general framework for efficient, multi-objective optimization in terms of relevant cost metrics, including processing latency, area, and power consumption. We demonstrate this framework by developing a multiobjective evolutionary algorithm based on it, and applying this algorithm to a rake receiver application.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"48 1","pages":"475-480"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79562005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}