Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387610
Zhao Fucai, Huang Yihua
To make the modulation classification system more suitable for signals in a wide range of signal to noise ratio (SNR), a feature extraction method based on signal wavelet packet transform modulus maxima matrix (WPTMMM) and a novel Support Vector Machine Fuzzy Network (SVMFN) classifier is presented in this paper. The WPTMMM feature extraction method has less computational complexity, more stability and has the outstanding advantage of robust with the time and white noise. Further, the SVMFN employs a new definition of fuzzy density which incorporates accuracy and uncertainty of the classifiers to improve recognition reliability to classify nine digital modulation types (i.e. 2ASK, 2FSK, 2PSK, 4ASK, 4FSK, 4PSK, 16QAM, MSK and OQPSK). Computer simulation shows that the proposed scheme has the advantages of high accuracy and reliability (success rates are over 98% when SNR is not lower than 0dB), and adapt to engineering applications.
{"title":"Classification Using Wavelet Packet Decomposition and SVM Fuzzy Network for Digital Modulations in Satellite Communication","authors":"Zhao Fucai, Huang Yihua","doi":"10.1109/SIPS.2007.4387610","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387610","url":null,"abstract":"To make the modulation classification system more suitable for signals in a wide range of signal to noise ratio (SNR), a feature extraction method based on signal wavelet packet transform modulus maxima matrix (WPTMMM) and a novel Support Vector Machine Fuzzy Network (SVMFN) classifier is presented in this paper. The WPTMMM feature extraction method has less computational complexity, more stability and has the outstanding advantage of robust with the time and white noise. Further, the SVMFN employs a new definition of fuzzy density which incorporates accuracy and uncertainty of the classifiers to improve recognition reliability to classify nine digital modulation types (i.e. 2ASK, 2FSK, 2PSK, 4ASK, 4FSK, 4PSK, 16QAM, MSK and OQPSK). Computer simulation shows that the proposed scheme has the advantages of high accuracy and reliability (success rates are over 98% when SNR is not lower than 0dB), and adapt to engineering applications.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"13 1","pages":"562-566"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75361476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387510
Min Li, J. Absar, B. Bougard, L. Perre, F. Catthoor
Orthogonal-Triangular Decomposition (QRD) is one of the most fundamental signal processing primitives based on complex matrix operations [1]. It forms the core of many advanced multi-dimension and statistical signal processing algorithms that utilize orthogonalization, projection, and rank-revealing principles. Especially in the domain of wireless signal processing, many emerging algorithms in MIMO and OFDM systems have explicit or implicit connections to QRD [2]. This paper is about the systematic optimization of QRD implementation on programmable architectures. Based on the analysis of existing works, we introduce the following higher level components to the new optimization methodology: (1) Exploring high level algorithmic alternatives. (2) Categorizing different application scenarios. (3) Merging cascaded matrix operations. The systematic optimization brings significant improvements for programmable QRD implementations. Comparing to the widely accepted implementation in Numerical Receipts [3], our work achieves up to 79.76% cycle count reduction on TI TMS320C6713, a typical VLIW DSP. Moreover, our work achieves remarkable improvement on the memory subsystem, which is very critical for the power consumption and performance of modern DSP. Specifically, when QRD is used to solve least-square linear equations, our work reduces 99.55% LIP misses and 96.52% LID misses for 32×32 equations.
{"title":"Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios","authors":"Min Li, J. Absar, B. Bougard, L. Perre, F. Catthoor","doi":"10.1109/SIPS.2007.4387510","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387510","url":null,"abstract":"Orthogonal-Triangular Decomposition (QRD) is one of the most fundamental signal processing primitives based on complex matrix operations [1]. It forms the core of many advanced multi-dimension and statistical signal processing algorithms that utilize orthogonalization, projection, and rank-revealing principles. Especially in the domain of wireless signal processing, many emerging algorithms in MIMO and OFDM systems have explicit or implicit connections to QRD [2]. This paper is about the systematic optimization of QRD implementation on programmable architectures. Based on the analysis of existing works, we introduce the following higher level components to the new optimization methodology: (1) Exploring high level algorithmic alternatives. (2) Categorizing different application scenarios. (3) Merging cascaded matrix operations. The systematic optimization brings significant improvements for programmable QRD implementations. Comparing to the widely accepted implementation in Numerical Receipts [3], our work achieves up to 79.76% cycle count reduction on TI TMS320C6713, a typical VLIW DSP. Moreover, our work achieves remarkable improvement on the memory subsystem, which is very critical for the power consumption and performance of modern DSP. Specifically, when QRD is used to solve least-square linear equations, our work reduces 99.55% LIP misses and 96.52% LID misses for 32×32 equations.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"15 3 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76237956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387622
M. V. D. Horst, R. H. Mak
We present a method to design multi-dimensional rank order filters. Our designs are more efficient than existing ones from literature, e.g. reducing the number of operations required by a 2-dimensional 7 × 7 median filter by 66%. This efficiency is maintained regardless of the amount of parallelism, therefore the throughput of our designs scales linearly with the amount of hardware. To accomplish this we introduce a framework in the form of a generator graph. This graph allows us to formalize our methods and formulate an algorithm that produces efficient designs by reusing common sub-expressions. Like other rank order filters our designs are based on sorting networks composed from Batcher¿s merging networks. However, we introduce an additional optimization that increases the savings obtained by pruning sorting networks. Our design method is independent of the implementation method and resulting designs can be implemented both as a VLSI circuit and as a program for an SIMD processor.
{"title":"Multi-Dimensional Parallel Rank Order Filtering","authors":"M. V. D. Horst, R. H. Mak","doi":"10.1109/SIPS.2007.4387622","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387622","url":null,"abstract":"We present a method to design multi-dimensional rank order filters. Our designs are more efficient than existing ones from literature, e.g. reducing the number of operations required by a 2-dimensional 7 × 7 median filter by 66%. This efficiency is maintained regardless of the amount of parallelism, therefore the throughput of our designs scales linearly with the amount of hardware. To accomplish this we introduce a framework in the form of a generator graph. This graph allows us to formalize our methods and formulate an algorithm that produces efficient designs by reusing common sub-expressions. Like other rank order filters our designs are based on sorting networks composed from Batcher¿s merging networks. However, we introduce an additional optimization that increases the savings obtained by pruning sorting networks. Our design method is independent of the implementation method and resulting designs can be implemented both as a VLSI circuit and as a program for an SIMD processor.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"135 1","pages":"627-632"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82864599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387597
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, A. Wu
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (NoC) provides a practical solution to solve the problem. The major components in NoC are routers, which are dominated by the buffer size. Previous mechanisms need large buffer size to achieve high performance. In this paper, a dynamic channel flow control mechanism is proposed to realize the channel resource sharing globally, which can increase the throughput and the channel utilization rate. An 8 × 8 mesh on-chip network is implemented on a cycle accurate simulator. By the experimental result, the proposed mechanism can reduce the buffer size by 30% as compared with virtual channel flow control at the same throughput. Moreover, the throughput can be improved by 20% as compared with wormhole flow control.
{"title":"Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency","authors":"Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, A. Wu","doi":"10.1109/SIPS.2007.4387597","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387597","url":null,"abstract":"System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (NoC) provides a practical solution to solve the problem. The major components in NoC are routers, which are dominated by the buffer size. Previous mechanisms need large buffer size to achieve high performance. In this paper, a dynamic channel flow control mechanism is proposed to realize the channel resource sharing globally, which can increase the throughput and the channel utilization rate. An 8 × 8 mesh on-chip network is implemented on a cycle accurate simulator. By the experimental result, the proposed mechanism can reduce the buffer size by 30% as compared with virtual channel flow control at the same throughput. Moreover, the throughput can be improved by 20% as compared with wormhole flow control.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"27 1","pages":"493-498"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81270069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387570
Junqing Liu, Tianhao Li
Binary arithmetic codes with forbidden symbols (named error correction arithmetic codes: ECAC) can be modeled as finite state machines and treated as variable length trellis codes. In this paper, a novel iterative joint source channel decoding algorithm is proposed for decoding trellis based error correction arithmetic codes. Unlike the conventional iterative decoding algorithm, it is needless to use the additional check codes such as CRC during the encoding, the proposed algorithm utilizes the Monte Carlo methods to detect the error bit directly. Furthermore, the outer error detector can not only detect the error bits but also provide the probability of the error location to the inner error corrector so as to accelerate the decoding process. Experimental results show that the proposed algorithm has some significant performance improvements over some conventional decoding algorithms in terms of the symbol error rate, while the increased computational complexity can be accepted.
{"title":"Iterative Joint Source Channel Decoding of Error Correction Arithmetic Codes","authors":"Junqing Liu, Tianhao Li","doi":"10.1109/SIPS.2007.4387570","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387570","url":null,"abstract":"Binary arithmetic codes with forbidden symbols (named error correction arithmetic codes: ECAC) can be modeled as finite state machines and treated as variable length trellis codes. In this paper, a novel iterative joint source channel decoding algorithm is proposed for decoding trellis based error correction arithmetic codes. Unlike the conventional iterative decoding algorithm, it is needless to use the additional check codes such as CRC during the encoding, the proposed algorithm utilizes the Monte Carlo methods to detect the error bit directly. Furthermore, the outer error detector can not only detect the error bits but also provide the probability of the error location to the inner error corrector so as to accelerate the decoding process. Experimental results show that the proposed algorithm has some significant performance improvements over some conventional decoding algorithms in terms of the symbol error rate, while the increased computational complexity can be accepted.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"15 1","pages":"346-350"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82477412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387567
Y. Ismail, M. Elgamel, M. Bayoumi
Dynamic Block Size Motion Estimation (DBS-ME) and smart Dynamic Early Search Termination (DEST) techniques are proposed and implemented in this paper. Both of the proposed techniques are combined and applied to the conventional phase correlation technique. The performance, visual quality and complexity of the proposed techniques are compared to that of the original phase correlation motion estimation (PC-ME) and Full Search Block Matching (FSBM) techniques. The proposed techniques provide an increase in the encoding quality besides a decrease in the computational complexity of ME process. Results show that there is approximately 100% of the stationary blocks decided by the FSBM algorithm are discovered correctly which consequently reduce the computations compared with the original FS and PC techniques. Also it is noted that, DBS-ME technique greatly decreases the computations required for ME process by decreasing the required padding to one or two pixels for both the current and the reference blocks. In addition, the motion field of the proposed algorithm gives much lower entropy than PC-ME which means more reduction in the transmitted bit rate.
{"title":"Adaptive Techniques for a Fast Frequency Domain Motion Estimation","authors":"Y. Ismail, M. Elgamel, M. Bayoumi","doi":"10.1109/SIPS.2007.4387567","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387567","url":null,"abstract":"Dynamic Block Size Motion Estimation (DBS-ME) and smart Dynamic Early Search Termination (DEST) techniques are proposed and implemented in this paper. Both of the proposed techniques are combined and applied to the conventional phase correlation technique. The performance, visual quality and complexity of the proposed techniques are compared to that of the original phase correlation motion estimation (PC-ME) and Full Search Block Matching (FSBM) techniques. The proposed techniques provide an increase in the encoding quality besides a decrease in the computational complexity of ME process. Results show that there is approximately 100% of the stationary blocks decided by the FSBM algorithm are discovered correctly which consequently reduce the computations compared with the original FS and PC techniques. Also it is noted that, DBS-ME technique greatly decreases the computations required for ME process by decreasing the required padding to one or two pixels for both the current and the reference blocks. In addition, the motion field of the proposed algorithm gives much lower entropy than PC-ME which means more reduction in the transmitted bit rate.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"48 1","pages":"331-336"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82680761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387620
Hua Yan, Ju Liu
This paper proposes two effective synchronous and parallel recursion schemes to implement regularization super-resolution image reconstruction. In the synchronous recursion, iteration step is adaptively adjusted by the speed of gradient descent to each observation channel. When blur support is too large or low-resolution images are severely degraded, however, the high-frequency information of the desired high-resolution (HR) image is still smoothed. So for fusing the information from different observation channels more effectively, parallel recursion is proposed to reconstruct desired HR image. In the two recursion schemes, spatial integration in down-sampling process is removed as well as system blurs, and nearest interpolation in up-sampling process is used to restrain edge artifact. Simulation results demonstrate that the two proposed implementation schemes give more satisfying results in both objective and subjective measurements.
{"title":"Implementation Schemes of Regularization Super-Resolution Image Reconstruction","authors":"Hua Yan, Ju Liu","doi":"10.1109/SIPS.2007.4387620","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387620","url":null,"abstract":"This paper proposes two effective synchronous and parallel recursion schemes to implement regularization super-resolution image reconstruction. In the synchronous recursion, iteration step is adaptively adjusted by the speed of gradient descent to each observation channel. When blur support is too large or low-resolution images are severely degraded, however, the high-frequency information of the desired high-resolution (HR) image is still smoothed. So for fusing the information from different observation channels more effectively, parallel recursion is proposed to reconstruct desired HR image. In the two recursion schemes, spatial integration in down-sampling process is removed as well as system blurs, and nearest interpolation in up-sampling process is used to restrain edge artifact. Simulation results demonstrate that the two proposed implementation schemes give more satisfying results in both objective and subjective measurements.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"16 1","pages":"615-620"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88935320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387615
Xin Lu, K. Nishiyama
This paper discusses the dependability of the maximum like-lihood estimator (MLE) when the dynamical model is specified as vector autoregression (VAR). When the size of the data vector in VAR is enlarged a little, the distributions of the estimates by the MLE become too wide to satisfy the precision requirement. Consequently, it is necessary to largely increase the length of the tested data for sharpening the distributions and obtaining the suitable estimates. In this paper, we give an explanation of this phenomenon and analyze the convergence relation of each parameter.
{"title":"Dependability of Unstructured Estimator in Vector Autoregression Identification","authors":"Xin Lu, K. Nishiyama","doi":"10.1109/SIPS.2007.4387615","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387615","url":null,"abstract":"This paper discusses the dependability of the maximum like-lihood estimator (MLE) when the dynamical model is specified as vector autoregression (VAR). When the size of the data vector in VAR is enlarged a little, the distributions of the estimates by the MLE become too wide to satisfy the precision requirement. Consequently, it is necessary to largely increase the length of the tested data for sharpening the distributions and obtaining the suitable estimates. In this paper, we give an explanation of this phenomenon and analyze the convergence relation of each parameter.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"37 1","pages":"589-594"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85187594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387589
R. Banchuin, B. Chipipop, B. Sirinaovakul
In this research, the practical 4-OTA-based floating inductor based upon the often cited monolithic CMOS technology has been studied and its complete passive equivalent circuit model, where the effects of both parasitic elements and finite opened-loop bandwidth have been taken into account, has been proposed. The accuracy evaluation of the proposed model has also been performed. The resulting model has been found to be excellently accurate with a considerably very small average error. Furthermore, the further study which is the inclusion of the mismatches among OTAs in order to obtain the most accurate results has also been proposed. However, the proposed passive equivalent circuit model has been found to be a convenience tool for the design of any signal processing circuits which require the CMOS-OTA-based floating inductors due to its considerably very small average error and the nature of the monolithic CMOS technology which allows the exclusion of the mismatches among OTAs.
{"title":"Novel Complete Passive Equivalent Circuit Model of the Practical 4-OTA-Based Floating Inductor","authors":"R. Banchuin, B. Chipipop, B. Sirinaovakul","doi":"10.1109/SIPS.2007.4387589","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387589","url":null,"abstract":"In this research, the practical 4-OTA-based floating inductor based upon the often cited monolithic CMOS technology has been studied and its complete passive equivalent circuit model, where the effects of both parasitic elements and finite opened-loop bandwidth have been taken into account, has been proposed. The accuracy evaluation of the proposed model has also been performed. The resulting model has been found to be excellently accurate with a considerably very small average error. Furthermore, the further study which is the inclusion of the mismatches among OTAs in order to obtain the most accurate results has also been proposed. However, the proposed passive equivalent circuit model has been found to be a convenience tool for the design of any signal processing circuits which require the CMOS-OTA-based floating inductors due to its considerably very small average error and the nature of the monolithic CMOS technology which allows the exclusion of the mismatches among OTAs.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"93 1","pages":"447-451"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86207068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387555
Junfeng Fan, K. Sakiyama, I. Verbauwhede
In this paper, we investigate the efficient software implementations of theMontgomery modular multiplication algorithm on amulti-core system. AHW/SW co-design technique is used to find the efficient system architecture and the instruction scheduling method. We first implement the Montgomery modular multiplication on a multi-core systemwith general purpose cores. We then speed up it by adopting the Multiply-Accumulate (MAC) operation in each core. As a result, the performance can be improved by a factor of 1.53 and 2.15 when 256-bit and 1024-bit Montgomery modular multiplication being performed, respectively.
{"title":"Montgomery Modular Multiplication Algorithm on Multi-Core Systems","authors":"Junfeng Fan, K. Sakiyama, I. Verbauwhede","doi":"10.1109/SIPS.2007.4387555","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387555","url":null,"abstract":"In this paper, we investigate the efficient software implementations of theMontgomery modular multiplication algorithm on amulti-core system. AHW/SW co-design technique is used to find the efficient system architecture and the instruction scheduling method. We first implement the Montgomery modular multiplication on a multi-core systemwith general purpose cores. We then speed up it by adopting the Multiply-Accumulate (MAC) operation in each core. As a result, the performance can be improved by a factor of 1.53 and 2.15 when 256-bit and 1024-bit Montgomery modular multiplication being performed, respectively.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"22 1","pages":"261-266"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81760394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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