Microprocessing and Microprogramming最新文献

One of the main obstacles to exploiting the fine-grained parallelism that is available in general-purpose code is the frequency of branches that cause unpredictable changes in the control flow of a program at run-time. Whenever a branch is taken, a performance penalty may be incurred as the processor waits for instructions to be fetched from the branch target stream. RISC processors introduce a delayed-branch mechanism which defines branch delay slots into which code can be scheduled. This strategy allows the processor to be kept busy executing useful instructions while the change of control flow takes place. While the concept of delayed branches can be readily extended to VLIW architectures, it is less clear how it should be incorporated in a superscalar architecture. This paper proposes a general branch-delay mechanism which is suitable for a range of code-compatible superscalar processors and which completely avoids the need to introduce NOPs into the code. This technique was developed as an integral part of the HSP superscalar project. HSP is a superscalar architecture currently being researched at the University of Hertfordshire with the aim of using compile-time instruction scheduling to achieve an order of magnitude speed-up over traditional RISC architectures for a suite of non-numeric benchmark programs.

This paper explains a method and tool for conformance testing of X.25 packet level protocol, and DTE equipment based on X.25 protocols. The method uses standard test suites, and standardized TTCN (Tree and Tabular Combined Notation).

This paper explains the character code recognition with the Boolean classifier. The binary values are used both for inputs and outputs, while the learning of the circuit with a set of patterns is done by modified algorithms used in some Boolean neural networks. The use of the fuzzy logic approach offers the possibility of creating a character recognition theory which is fault-tolerant and applicable to all sorts of typefaces and fonts. It provides several examples of patterns scanned with different resolutions and learned with a part of the same set of samples which demonstrates the quality of the fuzzy Boolea classifier.

In this paper we conduct a detailed performance analysis of four distinct member protocols from the Internet TCP/IP family, these being the user datagram protocol (UDP), transmission control protocol (TCP), the remote procedure call system (RPC) and data transmission aspects of the network file system (NFS). We discuss the trends in computer development which have led to the widespread use of distributed workstation environments interconnected by local area networks, the motivation for implementing parallel distributed programs on such systems and the impact that protocol-selection can have on the overall efficiency of such an application.

Query optimization in object-oriented databases requires new techniques for supporting features such as methods, path expressions, and so on. In this paper we address the optimization of path predicates in object-oriented queries. We apply the genetic search strategies to our optimization problem, and show that our formulation is well-suited to genetic algorithms.

The problem of defining a general scheme for interfacing replication for software fault tolerance (diverse software versions) and system replication techniques (distributed execution of process replicas) is investigated. An algorithm, called Minimum Information Algorithm, is defined in order to couple object copies and process replicas.

An algorithm for multicast connection setup based on the distributed Takahashi-Matsuyama algorithm is reviewed. Additional level of unexplored parallelism that allows better time performance has been identified. The described improvement is based on the adaptive balancing of the growing Steiner tree during the connection construction process. A simulation study on the time complexity indicates a speedup with regard to the original algorithm as well as to our earlier improvement.

This paper gives an overview of an ongoing research project on the application of formal methods to high-level synthesis. The key idea is to embed a design representation used in an existing high-level synthesis system in a mechanical proof system. This approach has the following properties: First, we use a design representation proved applicable to high-level synthesis; Second, we can reason about design transformations used in an existing high-level synthesis system; Third, we allow formal reasoning about both control and data; and Fourth, we provide mechanical support for formal reasoning.

In this paper, a VLSI architecture for the computation of the 2-D N × N-point Discrete Cosine Transform (DCT) is presented, where N is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 Mpixels/sec.