Microprocessing and Microprogramming最新文献

This paper presents a method to estimate the clock cycle, taking into account the dead times of the operators, that influences the total execution time, and the number of control steps, that settles the control unit size. It accepts a module library and it considers the area importance versus time importance depending on user constraints.

This paper presents a study about rounding error arising in the addition of opposite sign floating point operands: the algebraic study of the adder functionalities provides the possibility to modify hardware in order to measure the rounding error effect in terms of error size and incoming rate.

This paper presents the potential for case-based reasoning in design problems, specifically as applied to relational database schema design. The proposed system relies on two case-bases that consist of a Domain Dependent Case-Base (DDCB) and a Domain Independent Case-Base (DICB). We focus on the DDCB in this paper. The organization of domain dependent cases and their features for design are identified. The strategies for retrieving the relevant cases, for building a rough solution, for repairing the rough solution, and for learning cases, currently under development, are also described.

Stack machines, or stack based processors, have long been pigeon-holed as FORTH processors; specialised devices with little relevance for high level language applications. The failure of stack machines to address the issue of high level language support, and C in particular, has prevented wider acceptance of this promising technology despite the potential benefits of simpler hardware and low gate counts. Our research has centred upon eliminating cache and memory dependence, reducing the limits imposed by external bandwidths^◊. Having previously introduced a compact multiple-instruction-per-word stack-based encoding strategy in [Bailey93a], we now present a revised model, assessing its performance with compiled C benchmarks^⧫, and stressing minimisation of memory dependence.

The most critical problem associated with implementing in multi-level secure database management systems (MLS/DBMSs) is a correct concurrency control under the constraints of multilevel security. This paper provides two concurrency control schemes, one based on multiversion scheme and the other based on the two-phase locking scheme.

This paper presents an environment for acquisition, filtering, compression and storage of images of historical documents.

The main objective of this paper is to present a newly developed high performance reconfigurable multitransputer heterogeneous topology architecture called HP-FLEXAR. The proposed architecture is aimed to be used for time critical applications, especially for performing such computational tasks which could be solved in separate heterogeneous topology execution units using parallel decomposition and allocation algorithms.

The HP-FLEXAR enables dynamic assignment of program tasks to the worker transputers of separate execution units. The heterogeneous topology of these units can be also dynamically changed (during a program execution) according to the run-time analysis performed in the HP-FLEXAR decision and distribution unit (a DD unit). A feedback between the execution and DD units is one of the most important features of the HP-FLEXAR architecture. This enables taking full advantage of its dynamic reconfiguration capabilities.

The HP-FLEXAR being a flexible architecture is not limited to the above applications. One of the other areas of its potential applications is support of development of architectural concepts and communication strategies aimed to increase the efficiency of reconfigurable multi-transputer systems. This can be achieved through direct mapping of different multi-transputer architectural designs onto the HP-FLEXAR structure.

If buffer retention effect is taken into account, validation schemes for optimistic concurrency control (OCC) should be approached in some different point of view: rather than killing the conflicting transactions immediately in the middle of their execution, it would be better to allow them to run to their completion for bringing the required data objects into main memory. In this respect, we propose a new validation scheme for OCC called reordering serial equivalence (RSE) by introducing reverse serializability, which ensures the correctness of RSE when we allow the serialization in the reverse order of transactions' commits.