Microprocessing and Microprogramming最新文献

This paper is about a parallel and pipelined hardware system for real-time isolated speech recognition for medium-large Spanish vocabularies, based on Hidden Markov Models (HMMs). The system, relied on a VLSI circuit developed by the authors [1] that implements the Viterbi Algorithm, can keep-up with continuous input and is connected to a host Personal Computer. A software package controls the hardware and runs the user interface.

This paper presents a study about rounding error arising in the addition of opposite sign floating point operands: the algebraic study of the adder functionalities provides the possibility to modify hardware in order to measure the rounding error effect in terms of error size and incoming rate.

This paper presents the potential for case-based reasoning in design problems, specifically as applied to relational database schema design. The proposed system relies on two case-bases that consist of a Domain Dependent Case-Base (DDCB) and a Domain Independent Case-Base (DICB). We focus on the DDCB in this paper. The organization of domain dependent cases and their features for design are identified. The strategies for retrieving the relevant cases, for building a rough solution, for repairing the rough solution, and for learning cases, currently under development, are also described.

Determining the viability of livestock-embryos is an important procedure in minimizing the economic risk arising in case of transplantation of ‘engineered’ embryos into recipient animals. This evaluation is carried out at various segmentation phases of the embryos. In this paper we present a possible way to ease and/or automate the evaluation of embryo-viability for embryos being in their 8-cell stadium. We mention some grayscale morphological filtering techniques that has proved to be useful for the image segmentation in this stadium of the embryo segmentation. Meaningful circles (or circle-arcs) are fitted to the silhouette of the embryo and that of its constituent cells. Based on these circles morphological indices are calculated which are reported to be useful for the viability check.

In this paper, we describe a new transaction management scheme, MTM, for incorporating existing applications of local database systems into multidatabase applications. By capitalizing on the structural semantics of a global transaction, which can be specified in terms of intra-transaction dependencies, global transactions are modeled and executed as open-nested transactions. We design and implement a middleware facility to address issues related to managing transactions when they are described only with high-level operations which are explicitly exported by local database systems. We also describe a group checkpointing scheme to maintain MTM architecture tolerable from failures.

The conformance testing documents and their formal description in ACT ONE are briefly explained.

The main objective of this paper is to present a newly developed high performance reconfigurable multitransputer heterogeneous topology architecture called HP-FLEXAR. The proposed architecture is aimed to be used for time critical applications, especially for performing such computational tasks which could be solved in separate heterogeneous topology execution units using parallel decomposition and allocation algorithms.

The HP-FLEXAR enables dynamic assignment of program tasks to the worker transputers of separate execution units. The heterogeneous topology of these units can be also dynamically changed (during a program execution) according to the run-time analysis performed in the HP-FLEXAR decision and distribution unit (a DD unit). A feedback between the execution and DD units is one of the most important features of the HP-FLEXAR architecture. This enables taking full advantage of its dynamic reconfiguration capabilities.

The HP-FLEXAR being a flexible architecture is not limited to the above applications. One of the other areas of its potential applications is support of development of architectural concepts and communication strategies aimed to increase the efficiency of reconfigurable multi-transputer systems. This can be achieved through direct mapping of different multi-transputer architectural designs onto the HP-FLEXAR structure.

Methods and tools for fault tolerance in network based parallel computing are analyzed. Different communications libraries are now available which make it possible to use a local area network as a parallel computer. These libraries provide different services, however only little attention is devoted to the problem of fault tolerance. Using the fact that most of parallel applications exhibit a regular structure it is shown that to provide fault tolerance to this type of computation is much more simple than to provide fault tolerance in a general concurrent program. The primitives which are necessary to support the proposed design, and general implementation problems with respect to shared virtual memory and message passing communications models are briefly considered.

If buffer retention effect is taken into account, validation schemes for optimistic concurrency control (OCC) should be approached in some different point of view: rather than killing the conflicting transactions immediately in the middle of their execution, it would be better to allow them to run to their completion for bringing the required data objects into main memory. In this respect, we propose a new validation scheme for OCC called reordering serial equivalence (RSE) by introducing reverse serializability, which ensures the correctness of RSE when we allow the serialization in the reverse order of transactions' commits.