Microprocessing and Microprogramming最新文献

Wormhole message routing is supported by the communication hardware of several distributed memory machines. This particular method of message routing has numerous advantages but creates the problem of a routing deadlock. When long messages compete for the same channels in the network, some messages will be blocked until the first message is fully consumed by the processor at the destination of the message. A deadlock occurs if a set of messages mutually blocks, and no message can progress towards its destination. Most deadlock free routing schemes previously known are designed to work on regular binary hypercubes, a very special case of multicomputer interconnection networks. However, these routing schemes do not provide enough flexibility to deal with the irregular 2-D-tori and attached auxiliary cells found on many newer parallel systems.

To handle irregular topologies elegantly, a simple proof is necessary to verify the router code. The new proof given in this report is carried out directly on the network graph. It is constructive in the sense that it reveals the design options to deal with irregularities and shows how additional flexibility can be used to achieve better load balancing.

Based on the modified routing model, a set of deadlock free router functions relevant to the iWarp system configurations are described and proven to be correct.

We consider the problem of mapping tasks onto processors in a reconfigurable array architecture. We assume a directed acyclic task graph as input. The node weights in the task graph represent their computational requirement; the weight on an edge (i, j) is an estimate of the communication requirement between tasks i and j. The problem is to (a) estimate the minimum number of processors p to execute all the tasks with the highest possible efficiency, (b) bind each task to a processor, (c) schedule the tasks within each processor, and (d) carry out link allocation among processors. We assume a realistic model of reconfigurable parallel processors, where each processor can be connected to at most d other processors through bidirectional links. The objective of the problem is to minimize the total overall execution time, which includes the time spent by the processors in computation, communication, and idling. The mapping problem is computationally hard, and we present two algorithms for obtaining near-optimal solutions. The first algorithm is a heuristic algorithm based on the critical path method and as soon as possible scheduling. The second algorithm uses the Boltzmann machine model of artificial neural networks to solve the mapping problem. We have implemented both the algorithms on a Sun/SPARC workstation. Experimental results on a set of benchmark problems indicate that the neural algorithm generates better solutions than the heuristic algorithm, but takes significantly larger amounts of time than the latter. The number of neurons required in the algorithm is equal to n.p and hence the connection matrix is np × np; thus the neural algorithm is also memory intensive and I/O intensive due to swapping. We have devised a parallel divide-and-conquer algorithm which decomposes a large mapping problem into several smaller ones and solves the subproblems concurrently on a network of Sun workstations.

This paper presents a new global scheduling algorithm for automatic synthesis of the control blocks of special-purpose microprocessors. The main distinction of the proposed algorithm is that it exploits the inheritances of structured programs. The optimization goal is to maximize the speedup of the processor and minimize the size of the control block. If compared with existing global scheduling algorithms such as Trace scheduling, Tree compaction, and Percolation scheduling, the proposed algorithm consistently achieves better results in terms of the speedup of the processor and the size of the control block.

In this paper we describe a parallel version of the Hestenes algorithm for computing the singular value decomposition. We also describe a corresponding implementation on a transputer network. The implementation has been used to accelerate some programs for financial ratio analysis. Empirical results regarding the efficiency of our implementation are also presented.

Functional, object-oriented and logic programming are widely regarded as the three most dominant programming paradigms nowadays. For the past decade, many attempts have been made to integrate these three paradigms into a single language. This paper is a survey of this new breed of multiparadigm languages. First we give a succinct introduction to the three paradigms. Then we discuss a variety of approaches to the integration of the three paradigms through an overview of some of the existing multiparadigm languages. All possible combinations of the three paradigms, namely logic + object-oriented, functional + logic, functional + object-oriented, and object-oriented + logic + functional, are considered separately. For the purpose of classification, we have proposed a design space of programming languages called the FOOL-space.

Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interconnect delays across chips, by bringing the interconnect delays closer in magnitude to the on-chip delays. The problem here is to partition a circuit across multiple chips, producing MCMs. Partitioning is a combinatorial optimization problem. One of the methods to solve the problem is by the use of Genetic Algorithms (GAs), which are based on genetics. GAs can be used to solve both combinatorial as well as functional optimization problems. This paper solves the problem of partitioning using the GA approach. The performance of GAs is compared with that of Simulated Annealing (SA), by executing the algorithms on three benchmark circuits. The effect of varying the parameters of the algorithm on the performance of GAs is studied.

The application of parallelism considering the field of image processing is an alternative to implement real time image processing. The data parallelism found in array processors simplify the mapping of this kind of problem as each processing element works on part of the image. The GAPP board (Geometric Arithmetic Parallel Processor) is a near-neighbor mesh architecture with 144 processors interconnected as a 12 × 12 bidimensional array. This work analyzes the performance of the GAPP board regarding image processing. The implementation of two image convolution algorithms and the analyses of the obtained results, as well as the utilization of the GAPP board in this kind of application and the performance achieved are discussed. The results found in this work are also compared to the results presented in [11]. Some ways to achieve a better performance of the GAPP array in this kind of application are also presented.

Lack of I/O performance is fast becoming a limiting factor in many computing systems. The yearly doubling of CPU speeds is not being matched by corresponding gains in I/O performance. This paper explores one aspect of the architecture of a high performance fault-tolerant cached RAID subsystem for a multiprocessor. The disk write cache is implemented as a memory-mapped stable memory. The features of a VRAM-based stable memory and its associated RAID controller are discussed.