Microprocessing and Microprogramming最新文献

In this paper, we consider a class of log N stage interconnection networks called Bit-Permute Multistage Interconnection Networks (BPMIN's) where the ports of each switch of a stage are different at only one bit position of their labels. We describe the decomposition structure of the BPMIN's and prove that all of the BPMIN's are topologically equivalent and some of them are functionally equivalent. We also identify a class of 2 log N stage rearrangeable networks called symmetric BPMIN's where two log N stage BPMIN's are connected in sequence. The symmetric BPMIN's are either symmetric or asymmetric and regular or irregular in their inter-stage connections and can be reduced into 2 log N-1 stages by combining the two center stages. We show that the symmetric BPMIN's constitute larger class of rearrangeable networks than ever known. We also propose a general routing algorithm for the symmetric BPMIN's by modifying slightly the looping algorithm of the Benes network.

This paper describes a new scheduling algorithm for automatic synthesis of the control blocks of control-dominated circuits. The proposed scheduling algorithm is distinctive in its approach to partition a control/data flow graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplication, and unification. The optimization goal is to schedule each execution path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.

The mutual range-join of k sets, S₁, S₂,…, S_k, is the set containing all tuples (s₁, s₂…, s_k) that satisfy ${}_1\text{≤ ¦s}{}_{\mathrm{i}}\text{− s}{}_{\mathrm{j}}$ ¦ ≤ e₂ for all 1 ≤i≠j≤k, where s_i ϵ S_i and e₁ ≤ e₂ are fixed constants. This paper presents an efficient parallel algorithm for computing the k-set mutual range-join in hypercube computers. The proposed algorithm uses a fast method to determine whether the differences of all pair numbers among k given numbers are within a given range and applies the technique of permutation-based range-join [11]. To compute the mutual range-join of k sets S₁,S₂,…, S_k in a hypercube of p processors with O(∑^k_{i = 1}n_in_i/p) local memory, $\text{p ≤ ¦S}{}_{\mathrm{i}}\text{¦ = n}{}_{\mathrm{i}}$ and 1 ≤ i ≤ k, our algorithm requires at most O((k log k/p)π^k_{i = 1}n_i) data comparisons in the worst case. The algorithm is implemented in PVM and its performance is extensively evaluated on various input data.

We describe the design of a kernel for an inexpensive front-end processor to run the lower layers of common communication protocols. Implementing a full fledged kernel on a card requires large memory, expensive hardware and heavy processing overhead. We studied the requirements of the layers of communication protocols which generally run as a part of the host kernel. We realised that a workable kernel for the front-end processor which has a subset of the features of the host kernel, could be implemented within reasonable time. This could provide the functions required by the communication protocol layers and run them within the constraints of inexpensive hardware. The aims of this research were manifold:

• 1.

  (1) To explore the general set of requirements of common connection-oriented and connectionless protocols.

• 2.

  (2) To design and present algorithms of a kernel which can satisfy such requirements. Since the kernel is based on this general set of requirements, it will be generic and not specific to only the protocol running on the card. Thus it can be used to download different protocols on the card.

• 3.

  (3) Suggest implementation techniques so as to reduce memory and processing overhead on the host and to improve the performance of the protocols running in the kernel.

• 4.

  (4) To actually run a protocol on this kernel and compare its performance with an existing design.

Representing finite state systems by means of finite state machines is a common approach in VLSI circuit design. BDD-based algorithms have made possible the manipulation of FSMs with very large state spaces; however, when the representation of the set of reachable states grows too much, the original FSM is no longer manageable as a whole, and it needs to be decomposed into smaller sub-machines. Structural analysis of the circuit from which the FSM has been extracted has shown to be very effective to determine good state variable partitions which induce FSM decomposition for logic synthesis and formal verification applications. In this paper we propose FSM analysis techniques based on connectivity and spectral characteristics of the state machine which take into account the mutual dependency of the state variables, but which are no longer dependent on the structure of the underlying circuit; therefore, they may be used in a context different from sequential logic optimization and FSM verification. Experimental results are presented and discussed for the mcnc'91 FSM benchmarks and for the iscas'89 sequential circuits.

Programmable video signal processor ICs (VSPs) and dedicated programming tools have been developed for the real-time processing of digital video signals. A large number of applications have been developed with boards containing several of these processors. Currently two implementations of the general architecture exist: VSP1 and VSP2. A single VSP chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is carried out with signal flow graphs. These signal flow graphs can conveniently express multi-rate algorithms. These algorithms are then mapped onto a network of processors. Mapping is decomposed into delay management, partitioning and scheduling. The solution strategies for the partitioning problem and the scheduling problem are illustrated. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications. Results of the mapping are presented for a number of algorithms in the field of TV processing.

The problem of automatically generating programs for massively parallel computers is a very complicated one, mainly because there are many architectures, each of them seeming to pose its own particular compilation problem. The purpose of this paper is to propose a framework in which to discuss the compilation process, and to show that the features which affect it are few and generate a small number of combinations. The paper is oriented toward fine-grained parallelization of static control programs, with emphasis on dataflow analysis, scheduling and placement. When going from there to more general programs and to coarser parallelism, one encounters new problems, some of which are discussed in the conclusion.