Circuits, Systems and Signal Processing最新文献

The robust guaranteed cost composite anti-bump (L_2)-gain control for switched systems is investigated in this paper. By constructing a convex combination of positive definite matrices and segmenting the switching interval, a novel multiple convex Lyapunov function suitable for composite anti-bump switching (ABS) control problem is proposed. A new definition of composite ABS performance is presented without reference signals, which restrains the control and rate bumps of the system caused by switchings only at switching instants. Then, imposing a dwell time on the state-dependent switching law, a mixed state-dependent switching scheme is presented based on the multiple convex Lyapunov function. Robust guaranteed cost composite anti-bump control strategy is established for a class of switched systems to overcome the conflicts among guaranteed cost performance, composite bumpless switching performance and (L_2)-gain performance. Eventually, an actual aircraft engine model is employed to demonstrate the validity of the proposed approach.

The moth flame optimization (MFO) method has been introduced as a means to approximate single–input–single–output (SISO) complex high-order linear time-invariant systems (CHOLTIS). Initially, the unknown parameters within the denominator and numerator of the reduced-order linear time-invariant system (ROLTIS) are determined through balanced truncation. This process establishes the initial values of the parameters for MFO. To confine the exploration space of MFO around the coefficients derived from the balanced truncated model, a strategic constant is employed. This constant defines the lower and upper bounds, effectively constraining the search area of MFO. Consequently, MFO can focus its optimization efforts within a targeted range, improving efficiency and efficacy. The optimization process with MFO is then applied to fine-tune the unknown parameters of the ROLTIS. Through iterative optimization, MFO adjusts these parameters to minimize the error between the step response of CHOLTIS and the desired ROLTIS. This iterative process ensures that the resulting reduced-order system closely approximates the original high-order system. Moreover, to enhance the accuracy of the approximation, a gain adjustment factor is introduced after the optimization process. This factor enables the ROLTIS to match the steady-state response with that of the CHOLTIS. By fine-tuning the gain, the methodology ensures that the reduced-order system maintains consistent behavior with the original system under steady-state conditions. The efficacy of the proposed methodology is validated by applying it to four distinct high-order systems sourced from the literature. These systems encompass various configurations, including those with only real poles, real and imaginary poles, and repeated poles. Through testing on variety of systems, the proposed methodology consistently produces optimal and stable reduced-order systems with the lowest error indices, demonstrating its versatility and reliability across different system types and complexities.

In this paper, a grounded meminductor emulator has been proposed using six MOSFETs (3NMOS and 3PMOS) only. Three transconductance stages and two capacitors are generally required to realize a meminductor emulator. Meminductor is considered as an inductor having memory. In the proposed design of meminductor emulator, the gyrator circuit is realized using common-source and common-gate amplifiers with one capacitor. The first capacitor is used to obtain the behaviour of inductance while the second capacitor is used for charge storage which acts as a memory element. In the proposed design of meminductor emulator, the gate-to-source capacitor of MOSFET is utilized in place of external capacitor for memory element. Therefore, the proposed design is free from the requirement of passive components as the required capacitor is formed by MOSFET. Also, the frequency characteristics of proposed meminductor are found to be satisfactory up to 100 MHz. The other essential characteristics such as non-volatility test, temperature analysis, tunability, Monte Carlo, and corner analysis are also found to be satisfactory. The proposed design of meminductor emulator is compared with other existing meminductor emulators. The performance of the emulator is successfully verified through the realization of chaotic oscillator circuit.

In this paper, a novel dual-sparse parallel nested array (DS-PNA) is proposed for high-accuracy two-dimensional (2D) direction of arrival (DOA) estimation. The DS-PNA contains three subarrays, and the inter-antenna spacings of subarrays and those between subarrays are all enlarged with specific rates in 2D space (both of which are far larger than half-wavelength), for mutual coupling reduction and array aperture extension in physical array domain. Based on it, there is a systematic procedure to determine the number and positions of antennas in each subarray to achieve the maximum degrees of freedom in difference coarray domain, for improving the performance of DOA estimation. Numerical results are provided to demonstrate the superior performance of the DS-PNA for 2D DOA estimation over the state-of-the-art approaches, in the case of practical mutual coupling model.

In this technical note, we investigate the practical exponential stability of a positive switched linear system with impulses and all subsystems unstable. By constructing two types of switched discretized Lyapunov functions, we give some new sufficient conditions such that the system achieves practical exponential stability under mode-dependent range dwell time switching. Following this, we apply these results to the practical consensus of multi-agent system under switching topologies. The mathematical analysis is validated by a set of numerical examples.

Human action detection in static images is a hot and challenging field within computer vision. Given the limited features of a single image, achieving precision detection results require the full utilization of the image’s intrinsic features, as well as the integration of methods from other fields to process the images for generating additional features. In this paper, we propose a novel dual pathway model for action detection, whose main pathway employs a convolutional neural network to extract image features and predict the probability of the image belonging to each respective action. Meanwhile, the auxiliary pathway uses a pose estimate algorithm to obtain human key points and connection information for constructing a graphical human model for each image. These graphical models are then transformed into graph data and input into a graph neural network for features extracting and probability prediction. Finally, a corresponding connected neural network propose by us is used to fusing the probability vectors generated from the two pathways, which learns the weight of each action class in each vector to enable their subsequent fusion. It is noted that transfer learning is also used in our model to improve the training speed and detection accuracy of it. Experimental results upon three challenging datasets: Stanford40, PPMI and MPII illustrate the superiority of the proposed method.

This research article introduces an innovative 1-bit full adder design, leveraging grounded keeper circuitry. To implement full adder, keeper based XOR-XNOR cell -based design approach is used. Achieving full swing output voltage is one of the critical challenges in the designing of full adder. In this paper 8-T XOR-XNOR cell is proposed and simulated using HSPICE software at 90 nm technology node. The introduction of keeper circuit, which decreases propagation delay and offer full output voltage swing, is the primary focus of this research. Furthermore, this work puts forth an original design for a voltage-resilient ultra high-speed low-power keeper-based 1-bit full adder (UHSLPFA). Our research delves into a comprehensive comparison of various full adder designs, focusing on power dissipation (PWR), propagation delay (tp), and power-delay product (PDP). Notably, our proposed 20-T full adder design boasts notably reduced propagation delay and power consumption when compared to the existing counterparts. The envisioned application scope for this voltage-resilient ultra-high-speed-low-power keeper-based 1-bit full adder extends to the development of arithmetic logic units, multipliers, calculators, and graphical processing units. To gauge its voltage resilience, our proposed UHSLPFA is subjected to simulation across a range of supply voltages, from 0.6 to 1.5 V. This evaluation uncovers variations in PWR, tp, and PDP, showcasing the superior resilience of our design compared to contemporary state-of-the-art alternatives. The performance of the proposed full adder is also evaluated in 4-bit ripple carry adder.

The degree of freedom (DOF) parameter plays a crucial role in the Student’s t distribution as it affects the thickness of the distribution tails. Therefore, choosing an appropriate DOF parameter is essential for accurately modeling heavy-tailed noise. To improve estimation accuracy, this paper introduces a new robust Kalman filter based on moving window estimation to handle heavy-tailed noise. First, a sliding window based on Moving Horizon Estimation (MHE) is designed. By continuously utilizing the latest measurement information through the silding window, outliers that cause heavy-tailed noise can be better identified. Second, the noise is modeled as a Student’s t distribution, and an appropriate conjugate prior distribution is selected for the unknown noise covariance matrix. The Variational Bayesian (VB) method is combined with the proposed MHE framework to jointly infer the unknown parameters, updating the DOF parameter to a Gamma distribution. Finally, through simulation experiments, the optimal number of iterations and MHE window length are determined to ensure estimation accuracy while reducing computational complexity. The simulation results show that the proposed filtering algorithm exhibits better robustness in handling heavy-tailed noise compared to traditional filters.

The passive non-linear components, such as capacitors and inductors, lack inherent memory, thus limiting their applications to circuit functions like chaotic oscillators and waveform generators. In this research, it has been explored that these non-linear capacitors/inductors (NLC/I) may be transformed into functional memelements through appropriate modifications to the circuit configuration. Along with this motivation, it has been determined that achieving a universal emulator capable of replicating all three memelements with just a single alteration at a specific port is impractical. In such scenarios, at least one of the realized elements will inevitably retain characteristics of NLC or NLI. To address this challenge, proposed mutators have been developed to convert these unwantedly occurring NLC/I into functional memelements like flux-controlled memristor or charge-controlled memristor, which are valuable for memristive applications. Moreover, the proposed circuits are characterized by a compact design and utilize readily available off-the-shelf components. PSPICE-generated simulation results effectively illustrate the operational behavior of the memristors derived from mutations of NLC/I simulators. The simulation results are further validated through commercial ICs based implementation and experimental findings are depicted.

The existing rain streaks removal methods provide better deraining results, but it cannot be implemented on the low-light images due to the poor visual quality. To solve this problem, this paper presents a novel rain streaks removal approach using m fold infimal convolution of oscillating TGV((ICTGV^{osci})) regularization and Retinex theory for low-light images. Experiments on a number of challenging low-light rainy images are presented to demonstrate the efficiency and the flexibility of the proposed approaches in comparison with state-of-the-art methods.