This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch (({g}_{meff,latch})). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm2 allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s.
{"title":"Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications","authors":"Zahra Mehrabi Moghadam, Mohammad Reza Salehi, Salman Roudgar Nashta, Ebrahim Abiri","doi":"10.1007/s00034-024-02818-8","DOIUrl":"https://doi.org/10.1007/s00034-024-02818-8","url":null,"abstract":"<p>This paper presents an ultra-low power comparator with minimum delay and low offset, used in successive approximation register analog-to-digital converters (SAR ADCs) for biomedical system-on-chips (SoCs). To reduce the power consumption, the proposed comparator is designed with a minimum supply voltage in the sub-threshold region. Additionally, intermediate switches are utilized in the design to serve two purposes: 1) breaking the connection between the latch and preamplifier parts during the pre-charge phase to reduce power consumption, 2) reducing the parasitic resistance of the discharge path during the evaluation phase to enhance effective transconductance of the latch (<span>({g}_{meff,latch})</span>). Furthermore, the proposed design incorporates, two transistors as auxiliary paths to increase the speed of discharging in the latching process. Overall, the proposed design aims to achieve a low power and high-performance comparator simulated at a frequency of 50 kHz using TSMC 65nm CMOS technology. The post-layout simulation results show that the proposed structure enjoyed from an ultra-low power consumption of 141.4 pW as well as excellent delay and offset with 357 ns and 3.32 mV values, respectively. The occupied area of the designed layout for the proposed comparator is 106.8 μm<sup>2</sup> allowed us to embed it in multi-channel recording system on chips (SoCs). The Figure of Merit (FoM) of the proposed comparator is 0.000463 fVW/Hz. Moreover, the proposed comparator has been validated by using it in successive approximation conversion algorithm with a sampling frequency of 1 kS/s.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"8 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1007/s00034-024-02802-2
Morgana M. A. da Rosa, Eduardo A. C. da Costa, Rafael Soares, Sergio Bampi
Digital watermarking conceals data within host images to safeguard against unauthorized distribution of multimedia content. It offers content protection and anti-piracy measures, maintaining content quality by embedding invisible information. This process involves inserting and extracting watermarks. We introduce a robust algorithm, combining discrete Haar wavelet transform (DHWT) and discrete cosine transform (DCT), yielding effective watermarking with high resistance to extraction without data loss. This combination of transforms represents a hybrid approach that we call HyDHWCT in this work. Evaluations reveal our approach’s superior accuracy compared to state-of-the-art methods. Our hardware watermarking solution excels in robustness and energy efficiency, even under diverse attack scenarios. FPGA and ASIC assessments show our HyDHWCT’s exceptional area and power performance, with the algorithm achieving a lossless watermark extraction (NC = 1), outperforming prior methods in accuracy-quality, and energy-, and area-savings (approximately (2.621times ) and (1.174times ), respectively). Accuracy-quality results confirm a perfect extraction rate (NC = 1), ensuring 100% accuracy in watermark extraction.
{"title":"Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design","authors":"Morgana M. A. da Rosa, Eduardo A. C. da Costa, Rafael Soares, Sergio Bampi","doi":"10.1007/s00034-024-02802-2","DOIUrl":"https://doi.org/10.1007/s00034-024-02802-2","url":null,"abstract":"<p>Digital watermarking conceals data within host images to safeguard against unauthorized distribution of multimedia content. It offers content protection and anti-piracy measures, maintaining content quality by embedding invisible information. This process involves inserting and extracting watermarks. We introduce a robust algorithm, combining discrete Haar wavelet transform (DHWT) and discrete cosine transform (DCT), yielding effective watermarking with high resistance to extraction without data loss. This combination of transforms represents a hybrid approach that we call HyDHWCT in this work. Evaluations reveal our approach’s superior accuracy compared to state-of-the-art methods. Our hardware watermarking solution excels in robustness and energy efficiency, even under diverse attack scenarios. FPGA and ASIC assessments show our HyDHWCT’s exceptional area and power performance, with the algorithm achieving a lossless watermark extraction (NC = 1), outperforming prior methods in accuracy-quality, and energy-, and area-savings (approximately <span>(2.621times )</span> and <span>(1.174times )</span>, respectively). Accuracy-quality results confirm a perfect extraction rate (NC = 1), ensuring 100% accuracy in watermark extraction.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"98 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1007/s00034-024-02824-w
Venkatesh Akula, Ilaiah Kavati
In recent years, there has been an increase in demand for intelligent automatic surveillance systems to detect abnormal activities at various places, such as schools, hospitals, prisons, psychiatric centers, and public gatherings. The availability of video surveillance cameras in such places enables techniques for automatically identifying violent actions and alerting the authorities to minimize loss. Deep learning-based models, such as Convolutional Neural Networks (CNNs), have shown better performance in detecting violent activities by utilizing the spatiotemporal features of video frames. In this work, we propose a violence detection model based on 3D CNN, which employs a DenseNet architecture for enhanced spatiotemporal feature capture. First, the video’s redundant frames are discarded by identifying the key frames in the video. We exploit the Multi-Scale Structural Similarity Index Measure (MS-SSIM) technique to identify the key frames of the video, which contain significant information about the video. Key frame identification helps to reduce the complexity of the model. Next, the identified video key frames with the lowest MS-SSIM are forwarded to 3D CNN to extract spatiotemporal features. Furthermore, we exploit the Convolutional Block Attention Module (CBAM) to increase the representational capabilities of the 3D CNN. The results on different benchmark datasets show that the proposed violence detection method performs better than most of the existing methods. The source code for the proposed method is publicly available at https://github.com/venkateshakula19/violence-detection-using-keyframe-extraction-and-CNN-with-attention-CBAM
近年来,在学校、医院、监狱、精神病治疗中心和公共集会等各种场所检测异常活动的智能自动监控系统的需求不断增加。在这些场所安装视频监控摄像头,可实现自动识别暴力行为并向当局发出警报的技术,从而将损失降到最低。基于深度学习的模型,如卷积神经网络(CNN),通过利用视频帧的时空特征,在检测暴力活动方面表现出了更好的性能。在这项工作中,我们提出了一种基于 3D CNN 的暴力检测模型,该模型采用 DenseNet 架构来增强时空特征捕捉。首先,通过识别视频中的关键帧,剔除视频中的冗余帧。我们利用多尺度结构相似性指数测量(MS-SSIM)技术来识别视频中包含重要视频信息的关键帧。关键帧识别有助于降低模型的复杂性。接下来,MS-SSIM 值最低的已识别视频关键帧将被转发到 3D CNN,以提取时空特征。此外,我们还利用卷积块注意力模块(CBAM)来提高 3D CNN 的表征能力。在不同基准数据集上的结果表明,所提出的暴力检测方法的性能优于大多数现有方法。建议方法的源代码可在 https://github.com/venkateshakula19/violence-detection-using-keyframe-extraction-and-CNN-with-attention-CBAM 上公开获取。
{"title":"Human Violence Detection in Videos Using Key Frame Identification and 3D CNN with Convolutional Block Attention Module","authors":"Venkatesh Akula, Ilaiah Kavati","doi":"10.1007/s00034-024-02824-w","DOIUrl":"https://doi.org/10.1007/s00034-024-02824-w","url":null,"abstract":"<p>In recent years, there has been an increase in demand for intelligent automatic surveillance systems to detect abnormal activities at various places, such as schools, hospitals, prisons, psychiatric centers, and public gatherings. The availability of video surveillance cameras in such places enables techniques for automatically identifying violent actions and alerting the authorities to minimize loss. Deep learning-based models, such as Convolutional Neural Networks (CNNs), have shown better performance in detecting violent activities by utilizing the spatiotemporal features of video frames. In this work, we propose a violence detection model based on 3D CNN, which employs a DenseNet architecture for enhanced spatiotemporal feature capture. First, the video’s redundant frames are discarded by identifying the key frames in the video. We exploit the Multi-Scale Structural Similarity Index Measure (MS-SSIM) technique to identify the key frames of the video, which contain significant information about the video. Key frame identification helps to reduce the complexity of the model. Next, the identified video key frames with the lowest MS-SSIM are forwarded to 3D CNN to extract spatiotemporal features. Furthermore, we exploit the Convolutional Block Attention Module (CBAM) to increase the representational capabilities of the 3D CNN. The results on different benchmark datasets show that the proposed violence detection method performs better than most of the existing methods. The source code for the proposed method is publicly available at https://github.com/venkateshakula19/violence-detection-using-keyframe-extraction-and-CNN-with-attention-CBAM</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"58 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1007/s00034-024-02813-z
Ahmed Haddi, Mohamed El Azzouzi, Mohamed Laabissi
We present a novel design methodology for a fractional model error compensator (FMEC) that addresses the challenge of model errors in fractional dynamical systems with polytopic uncertainty and disturbances. The FMEC can effectively compensate for model errors, thereby enhancing the performance of control systems. This approach leverages a combination of (mathcal{H}_infty )-norm criteria and the Particle Swarm Optimization (PSO) algorithm to optimize the compensator design. The methodology integrates (mathcal{H}_infty )-norm criteria for robust performance evaluation and PSO for optimization. The proposed FMEC design is validated through numerical simulations conducted on a fractional dynamical system. These simulations demonstrate that the design successfully compensates for model errors and improves the overall performance of the control system. This study offers a practical solution for designing robust FMECs applicable in various engineering fields, particularly for systems susceptible to polytopic uncertainty and disturbances.
{"title":"A design approach of fractional model error compensator for fractional dynamical systems with polytopic uncertainty and disturbance","authors":"Ahmed Haddi, Mohamed El Azzouzi, Mohamed Laabissi","doi":"10.1007/s00034-024-02813-z","DOIUrl":"https://doi.org/10.1007/s00034-024-02813-z","url":null,"abstract":"<p>We present a novel design methodology for a fractional model error compensator (FMEC) that addresses the challenge of model errors in fractional dynamical systems with polytopic uncertainty and disturbances. The FMEC can effectively compensate for model errors, thereby enhancing the performance of control systems. This approach leverages a combination of <span>(mathcal{H}_infty )</span>-norm criteria and the Particle Swarm Optimization (PSO) algorithm to optimize the compensator design. The methodology integrates <span>(mathcal{H}_infty )</span>-norm criteria for robust performance evaluation and PSO for optimization. The proposed FMEC design is validated through numerical simulations conducted on a fractional dynamical system. These simulations demonstrate that the design successfully compensates for model errors and improves the overall performance of the control system. This study offers a practical solution for designing robust FMECs applicable in various engineering fields, particularly for systems susceptible to polytopic uncertainty and disturbances.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"7 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-13DOI: 10.1007/s00034-024-02823-x
Yumeng Chen, Juan Li
The time–frequency analysis (TFA) method is an effective tool to separate and extract main components for non-stationary signals such as vibration signals and seismic signals, which are time-varying and affected by high noise. However, suffering from the Heisenberg uncertainty principle and cross terms of time–frequency result, conventional TFA methods usually produce vague time–frequency representations (TFRs). As a branch of the TFA method, current redistributive compressive transforms enable to generate clear TFR. However, these techniques are limited to a singular type of signal, which is not applicable to deal with complicated signals in production. In order to enhance the applicability and the time–frequency (TF) aggregation capability, this paper proposes a promoted TFA method 2D-FTSST2 based on the synchrosqueezing transform combining two-dimensional information of time and frequency domains. For an accurate IF estimate, we also define a time redistribution operator, which can describe strong time and frequency-varying signals. This algorithm not only provides a high-resolution decomposition of multicomponent signals but also enables to extract main features in noisy environments. Experiments on simulated signals and real data confirm the validity and effectiveness of the proposed algorithm.
{"title":"2D Second-Order Time–Frequency Synchrosqueezing Transform: For Non-stationary Signals Well-Localized Components Extraction and Separation","authors":"Yumeng Chen, Juan Li","doi":"10.1007/s00034-024-02823-x","DOIUrl":"https://doi.org/10.1007/s00034-024-02823-x","url":null,"abstract":"<p>The time–frequency analysis (TFA) method is an effective tool to separate and extract main components for non-stationary signals such as vibration signals and seismic signals, which are time-varying and affected by high noise. However, suffering from the Heisenberg uncertainty principle and cross terms of time–frequency result, conventional TFA methods usually produce vague time–frequency representations (TFRs). As a branch of the TFA method, current redistributive compressive transforms enable to generate clear TFR. However, these techniques are limited to a singular type of signal, which is not applicable to deal with complicated signals in production. In order to enhance the applicability and the time–frequency (TF) aggregation capability, this paper proposes a promoted TFA method 2D-FTSST2 based on the synchrosqueezing transform combining two-dimensional information of time and frequency domains. For an accurate IF estimate, we also define a time redistribution operator, which can describe strong time and frequency-varying signals. This algorithm not only provides a high-resolution decomposition of multicomponent signals but also enables to extract main features in noisy environments. Experiments on simulated signals and real data confirm the validity and effectiveness of the proposed algorithm.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"25 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-07DOI: 10.1007/s00034-024-02799-8
Praveen Kumar, Pankaj Rai, Amit Kumar Choudhary
Since decades mathematicians have been designing the transfer function for the available physical models followed by the involvement of control engineers to work on it. Through the study of the offered representations, many systems were found to be of higher order which are nevertheless not easy to study and analyze in their core form. Furthermore, again uncertainties within the system was found that cannot be ignored. All these increases the complexities for analysis of the physical systems. This demands a technique for order reduction to derive an approximate lower order representation of the higher order systems. In continuation, this paper is an attempt to propose a computationally efficient approach for obtaining the reduced interval model based on Routh Approximation technique. The proposed approach is a novel method for discrete-time interval system and is discussed in detail in the article content ahead. The provided examples offer the desired explanation for the effectiveness of the proposed algorithm.
{"title":"Order Reduction of z-Domain Interval Systems by Advanced Routh Approximation Method","authors":"Praveen Kumar, Pankaj Rai, Amit Kumar Choudhary","doi":"10.1007/s00034-024-02799-8","DOIUrl":"https://doi.org/10.1007/s00034-024-02799-8","url":null,"abstract":"<p>Since decades mathematicians have been designing the transfer function for the available physical models followed by the involvement of control engineers to work on it. Through the study of the offered representations, many systems were found to be of higher order which are nevertheless not easy to study and analyze in their core form. Furthermore, again uncertainties within the system was found that cannot be ignored. All these increases the complexities for analysis of the physical systems. This demands a technique for order reduction to derive an approximate lower order representation of the higher order systems. In continuation, this paper is an attempt to propose a computationally efficient approach for obtaining the reduced interval model based on <i>Routh Approximation</i> technique. The proposed approach is a novel method for discrete-time interval system and is discussed in detail in the article content ahead. The provided examples offer the desired explanation for the effectiveness of the proposed algorithm.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"374 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose an energy-efficient design of architecture for digit-serial multiplication over generic GF((2^m)), which could be used for different fields as and when required and to enhance the security by changing the fields. An efficient input scheduling scheme is proposed to reduce the required number of input pins and a digit extraction circuit for digit-serial multiplication. Besides, to reduce the dynamic power consumption, we have proposed a simple technique using an array of m AND gates that minimizes the output bit-switching. To study the impact of digit size, the digit-serial multipliers for (m=163) and 233 are synthesised by Xilinx Vivado for FPGA implementation. It is found that the required number of slices, power consumption, and energy per multiplication increase while the computational delay falls with the increase in digit size. Therefore, larger digit sizes could be considered only when fast multiplication is necessary. The array of AND gates for output bit control helps in reducing the dynamic power consumption and energy per multiplication, respectively, by 50.4% and 57.7% for (m=163) and (49.8%) and (51.8%), for (m=233), on average, for different digit sizes over the conventional least-significant-digit-first design.
在本文中,我们为通用 GF((2^m))上的数字串行乘法提出了一种高能效的架构设计,它可以根据需要用于不同的字段,并通过改变字段来增强安全性。我们提出了一种高效的输入调度方案,以减少数字串行乘法所需的输入引脚和数字提取电路的数量。此外,为了降低动态功耗,我们提出了一种使用 m AND 门阵列的简单技术,可最大限度地减少输出位切换。为了研究数位大小的影响,我们用 Xilinx Vivado 合成了 (m=163) 和 233 的数位串行乘法器,用于 FPGA 实现。结果发现,随着位数的增加,每次乘法所需的片数、功耗和能量都会增加,而计算延迟则会下降。因此,只有在需要快速乘法的情况下,才可以考虑更大的数字大小。与传统的最小有效数字优先设计相比,用于输出位控制的AND门阵列有助于在不同位数大小的情况下,在(m=163)和(m=233)的情况下,将每次乘法的动态功耗和能耗分别平均降低50.4%和57.7%,在(m=49.8%)和(m=51.8%)的情况下,将每次乘法的动态功耗和能耗分别平均降低50.4%和57.7%。
{"title":"Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields","authors":"Dibakar Pradhan, Pramod Kumar Meher, Bimal Kumar Meher","doi":"10.1007/s00034-024-02793-0","DOIUrl":"https://doi.org/10.1007/s00034-024-02793-0","url":null,"abstract":"<p>In this paper, we propose an energy-efficient design of architecture for digit-serial multiplication over generic GF(<span>(2^m)</span>), which could be used for different fields as and when required and to enhance the security by changing the fields. An efficient input scheduling scheme is proposed to reduce the required number of input pins and a digit extraction circuit for digit-serial multiplication. Besides, to reduce the dynamic power consumption, we have proposed a simple technique using an array of <i>m</i> AND gates that minimizes the output bit-switching. To study the impact of digit size, the digit-serial multipliers for <span>(m=163)</span> and 233 are synthesised by Xilinx Vivado for FPGA implementation. It is found that the required number of slices, power consumption, and energy per multiplication increase while the computational delay falls with the increase in digit size. Therefore, larger digit sizes could be considered only when fast multiplication is necessary. The array of AND gates for output bit control helps in reducing the dynamic power consumption and energy per multiplication, respectively, by 50.4% and 57.7% for <span>(m=163)</span> and <span>(49.8%)</span> and <span>(51.8%)</span>, for <span>(m=233)</span>, on average, for different digit sizes over the conventional least-significant-digit-first design.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"16 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-07DOI: 10.1007/s00034-024-02803-1
W. Yasmeen, G. N. Swamy, K. Padma Priya
A low-noise amplifier (LNA) is one of the most crucial components of a communication system. The current low-noise amplifier design faces challenges due to intrinsic noise sources in CMOS transistors and trade-offs to maximize gain and bandwidth. Hence the Optimal design of a low-power ultra-wideband low-noise transconductance amplifier in 0.18 µm CMOS is introduced to minimize the noise figure of the amplifier. Ultra wideband (UWB) signals cover a wide frequency range making it challenging to achieve good input and output matching across the entire band. Thus, Cascode inductive degenerative using pi matching network enhances input–output matching by providing impedance transformation, matching source impedance to low input impedance, and improving power transfer rate. However, the cascode configuration with pi matching offers superior performance over a wide frequency range, but it requires careful consideration of gain and noise figures. Therefore, a current reuse technique is utilized to improve gain and reduce noise figures by optimizing the distribution of bias currents and enhancing the overall performance of the amplifier. Furthermore, the main design challenge for LNAs is achieving high linearity in interference-filled environments. Hence novel Cascade inductive degenerative using T matching network addresses low-frequency signal interference by utilizing multiple amplifier stages for gain and high linearity. Thus, the result obtained showed that the proposed model outperforms the existing design with high gain of 17.7 dB, high input return loss of 10.6 dB, high FOM of 24.4 and low noise figures of 0.573 dB, thus improves the overall performance of the system.
低噪声放大器(LNA)是通信系统最关键的组件之一。目前的低噪声放大器设计面临着 CMOS 晶体管固有噪声源以及增益和带宽最大化权衡带来的挑战。因此,我们采用 0.18 µm CMOS 对低功耗超宽带低噪声跨导放大器进行了优化设计,以最大限度地降低放大器的噪声系数。超宽带 (UWB) 信号覆盖的频率范围很广,因此在整个频段内实现良好的输入和输出匹配具有挑战性。因此,使用π匹配网络的级联电感变性通过提供阻抗变换、将源阻抗匹配到低输入阻抗以及提高功率传输速率来增强输入输出匹配。不过,带 pi 匹配的级联配置在较宽的频率范围内性能优越,但需要仔细考虑增益和噪声系数。因此,我们采用了电流重复使用技术,通过优化偏置电流的分布来提高增益和降低噪声系数,从而提高放大器的整体性能。此外,低噪声放大器的主要设计挑战是在充满干扰的环境中实现高线性度。因此,采用 T 匹配网络的新型级联电感式退变通过利用多级放大器实现增益和高线性度,从而解决了低频信号干扰问题。结果表明,所提出的模型优于现有设计,具有 17.7 dB 的高增益、10.6 dB 的高输入回损、24.4 的高 FOM 和 0.573 dB 的低噪声,从而提高了系统的整体性能。
{"title":"Optimal Design of Low-Power Ultra-Wideband Low-Noise Transconductance Amplifier in 0.18 µm CMOS","authors":"W. Yasmeen, G. N. Swamy, K. Padma Priya","doi":"10.1007/s00034-024-02803-1","DOIUrl":"https://doi.org/10.1007/s00034-024-02803-1","url":null,"abstract":"<p>A low-noise amplifier (LNA) is one of the most crucial components of a communication system. The current low-noise amplifier design faces challenges due to intrinsic noise sources in CMOS transistors and trade-offs to maximize gain and bandwidth. Hence the Optimal design of a low-power ultra-wideband low-noise transconductance amplifier in 0.18 µm CMOS is introduced to minimize the noise figure of the amplifier. Ultra wideband (UWB) signals cover a wide frequency range making it challenging to achieve good input and output matching across the entire band. Thus, Cascode inductive degenerative using pi matching network enhances input–output matching by providing impedance transformation, matching source impedance to low input impedance, and improving power transfer rate. However, the cascode configuration with pi matching offers superior performance over a wide frequency range, but it requires careful consideration of gain and noise figures. Therefore, a current reuse technique is utilized to improve gain and reduce noise figures by optimizing the distribution of bias currents and enhancing the overall performance of the amplifier. Furthermore, the main design challenge for LNAs is achieving high linearity in interference-filled environments. Hence novel Cascade inductive degenerative using T matching network addresses low-frequency signal interference by utilizing multiple amplifier stages for gain and high linearity. Thus, the result obtained showed that the proposed model outperforms the existing design with high gain of 17.7 dB, high input return loss of 10.6 dB, high FOM of 24.4 and low noise figures of 0.573 dB, thus improves the overall performance of the system.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"22 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A robust finite-time state tracking issue for a class of linear semi-Markovian jump systems in the presence of unknown disturbance and uncertainties is scrutinized in this study. A lumped disturbance estimator, which bears the consequence of disturbance signals and uncertainties, is devised to ease the required tracking results and to estimate the external input and model perturbations simultaneously. More precisely, in this work, a composite lumped disturbance rejection and robust finite-time state tracking strategy is proposed to get the required result. Additionally, a list of sufficient requirements is constructed within the context of linear matrix inequalities using Lyapunov stability theory to guarantee that the trajectories of the resulting tracking error system are stable in finite-time span. Eventually, the efficacy and practicability of the designed control strategy are validated by using two numerical examples including switched boost converter circuit model.
{"title":"Composite State Tracking Control Protocol for Semi-Markovian Jump Systems with Time-Varying Delays","authors":"Harshavarthini Shanmugam, Sakthivel Rathinasamy, Anusuya Sundaram, Mohammadzadeh Ardashir","doi":"10.1007/s00034-024-02773-4","DOIUrl":"https://doi.org/10.1007/s00034-024-02773-4","url":null,"abstract":"<p>A robust finite-time state tracking issue for a class of linear semi-Markovian jump systems in the presence of unknown disturbance and uncertainties is scrutinized in this study. A lumped disturbance estimator, which bears the consequence of disturbance signals and uncertainties, is devised to ease the required tracking results and to estimate the external input and model perturbations simultaneously. More precisely, in this work, a composite lumped disturbance rejection and robust finite-time state tracking strategy is proposed to get the required result. Additionally, a list of sufficient requirements is constructed within the context of linear matrix inequalities using Lyapunov stability theory to guarantee that the trajectories of the resulting tracking error system are stable in finite-time span. Eventually, the efficacy and practicability of the designed control strategy are validated by using two numerical examples including switched boost converter circuit model.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"30 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-07DOI: 10.1007/s00034-024-02808-w
Merzouk Younsi, Moussa Diaf, Patrick Siarry
Human detection and tracking from infrared image sequences has received considerable attention in many practical applications, ranging from security and surveillance to automated health-care monitoring. However, most of the systems currently reported in the literature assume that humans are in an upright standing or walking posture in the monitored scene, which may not be true in some real-world surveillance scenarios, as humans can move in other abnormal postures, such as creeping and crawling. To overcome this limitation and enable human detection even in the presence of posture changes, this paper proposes a novel system based on locating human head–shoulder Ω-like part and two legs. For tracking purposes, a particle filter and an adaptive combination of different cues, namely spatial, intensity, texture and motion velocity are used. Then, to better describe the posture of the detected human and thus enable its effective recognition over time, three different features, namely Krawtchouk moments, chain code histograms and geometry-based features are first extracted, and then fed into a dendrogram-based support vector machine classifier for posture recognition. The results of posture recognition, in combination with the tracking information, are finally exploited to analyze the behavior of the detected human in the monitored scene. The proposed system was evaluated by performing extensive experiments using several infrared image sequences taken in a real outdoor nighttime environment. The obtained results are satisfactory and demonstrate the feasibility and effectiveness of the proposed system for the automatic detection of moving humans and the analysis of their behavior.
{"title":"Posture-Invariant Human Detection and Tracking for Outdoor Night-Time Surveillance","authors":"Merzouk Younsi, Moussa Diaf, Patrick Siarry","doi":"10.1007/s00034-024-02808-w","DOIUrl":"https://doi.org/10.1007/s00034-024-02808-w","url":null,"abstract":"<p>Human detection and tracking from infrared image sequences has received considerable attention in many practical applications, ranging from security and surveillance to automated health-care monitoring. However, most of the systems currently reported in the literature assume that humans are in an upright standing or walking posture in the monitored scene, which may not be true in some real-world surveillance scenarios, as humans can move in other abnormal postures, such as creeping and crawling. To overcome this limitation and enable human detection even in the presence of posture changes, this paper proposes a novel system based on locating human head–shoulder Ω-like part and two legs. For tracking purposes, a particle filter and an adaptive combination of different cues, namely spatial, intensity, texture and motion velocity are used. Then, to better describe the posture of the detected human and thus enable its effective recognition over time, three different features, namely Krawtchouk moments, chain code histograms and geometry-based features are first extracted, and then fed into a dendrogram-based support vector machine classifier for posture recognition. The results of posture recognition, in combination with the tracking information, are finally exploited to analyze the behavior of the detected human in the monitored scene. The proposed system was evaluated by performing extensive experiments using several infrared image sequences taken in a real outdoor nighttime environment. The obtained results are satisfactory and demonstrate the feasibility and effectiveness of the proposed system for the automatic detection of moving humans and the analysis of their behavior.</p>","PeriodicalId":10227,"journal":{"name":"Circuits, Systems and Signal Processing","volume":"58 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141949391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}