Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993690
T. Noji, T. Suzuki
Stable operation of production facilities and equipment is essential for efficient production. Currently, however changes in equipment operation often cause problems in production processes. To prevent these problems, we studied and developed a system that continuously monitors process states. We first selected equipment parameters that are most likely to affect process characteristics and monitored these parameters. A comparison between the monitored data and the standard process characteristics revealed that the voltage for opening the wafer-cooling gas pressure control valve ("valve opening voltage") was positively correlated with the intra-wafer uniformity of the etching rate. We have developed a system that can indirectly detect changes of the uniformity of the etching rate by continuously monitoring the valve opening voltages.
{"title":"Establishment of process monitoring for production availability improvement","authors":"T. Noji, T. Suzuki","doi":"10.1109/ISSM.2000.993690","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993690","url":null,"abstract":"Stable operation of production facilities and equipment is essential for efficient production. Currently, however changes in equipment operation often cause problems in production processes. To prevent these problems, we studied and developed a system that continuously monitors process states. We first selected equipment parameters that are most likely to affect process characteristics and monitored these parameters. A comparison between the monitored data and the standard process characteristics revealed that the voltage for opening the wafer-cooling gas pressure control valve (\"valve opening voltage\") was positively correlated with the intra-wafer uniformity of the etching rate. We have developed a system that can indirectly detect changes of the uniformity of the etching rate by continuously monitoring the valve opening voltages.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125620494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993618
Ying-Jen Chen, G. Yu., Kuo-sung Huang, Ivan Wang
We demonstrate a next-queue rule in the real time dispatcher developed in MXIC FAB I. The outline of this system is presented first, then, the dispatching rule design logic is described. The real time dispatching system makes lot-dispatching work easy for operators. A next queue algorithm was developed in the implementation of the real time dispatcher. Finally, it has been proved that the dispatching algorithm not only improves FAB utilization but also reduces cycle time. Implementation of the real time dispatching system keeps reducing of cycle time and improves tool utilization by 7% from Q2 1999 to now.
{"title":"A next queue algorithm in real time dispatching system of semiconductor manufacturing","authors":"Ying-Jen Chen, G. Yu., Kuo-sung Huang, Ivan Wang","doi":"10.1109/ISSM.2000.993618","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993618","url":null,"abstract":"We demonstrate a next-queue rule in the real time dispatcher developed in MXIC FAB I. The outline of this system is presented first, then, the dispatching rule design logic is described. The real time dispatching system makes lot-dispatching work easy for operators. A next queue algorithm was developed in the implementation of the real time dispatcher. Finally, it has been proved that the dispatching algorithm not only improves FAB utilization but also reduces cycle time. Implementation of the real time dispatching system keeps reducing of cycle time and improves tool utilization by 7% from Q2 1999 to now.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"353 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113982829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993631
S.A. Wu, Y.K. Wang, Y. Cheng, J.K. Wang, G. Wang, M. Yo, C.T. Lee, T. Lu, S. Wang, J. Li, Chen-Ho Lai
As feature size shrinks to the deep sub-micron regime, the RC delay of metal interconnection will increase and limit the performance of high-speed devices. To address this problem, fluorine-doped silicon dioxide (SiOF) has been introduced in advanced IMD applications. Many deposition methods have been studied, including PECVD and HDP CVD. HDP CVD was finally applied to most deep sub-micron processes because it can meet the gap-filling requirement. However, the fluorine-doped silicon dioxide film is an unstable film. It suffers from high water absorption and a fluorine instability problem. This problem will cause a device reliability issue and even defects to appear at the final alloy step. In this paper, the fluorine-doped silicon dioxide deposition temperature and post-thermal processes, including N2 alloy and vacuum-bake have been studied, find a way to overcome these problems. The fluorine-doped silicon dioxide film properties including the fluorine concentration, RI, and film thickness will be compared to the as-deposition after film is alloyed. The film SIMS and TDS data have also been studied in this paper. The result of the experiments show that a lower deposition temperature has a poorer film property and the post-thermal process can degas the unstable fluorine. The optimized combination of conditions, of fluorine-doped silicon dioxide deposition temperature and post-thermal treatment can create a good quality fluorine-doped silicon dioxide without a reliability issue.
{"title":"The study of fluorine-doped silicon dioxide (FSG) films property after thermal alloy for different film deposition temperature for sub-0.18 um logic yield improvement","authors":"S.A. Wu, Y.K. Wang, Y. Cheng, J.K. Wang, G. Wang, M. Yo, C.T. Lee, T. Lu, S. Wang, J. Li, Chen-Ho Lai","doi":"10.1109/ISSM.2000.993631","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993631","url":null,"abstract":"As feature size shrinks to the deep sub-micron regime, the RC delay of metal interconnection will increase and limit the performance of high-speed devices. To address this problem, fluorine-doped silicon dioxide (SiOF) has been introduced in advanced IMD applications. Many deposition methods have been studied, including PECVD and HDP CVD. HDP CVD was finally applied to most deep sub-micron processes because it can meet the gap-filling requirement. However, the fluorine-doped silicon dioxide film is an unstable film. It suffers from high water absorption and a fluorine instability problem. This problem will cause a device reliability issue and even defects to appear at the final alloy step. In this paper, the fluorine-doped silicon dioxide deposition temperature and post-thermal processes, including N2 alloy and vacuum-bake have been studied, find a way to overcome these problems. The fluorine-doped silicon dioxide film properties including the fluorine concentration, RI, and film thickness will be compared to the as-deposition after film is alloyed. The film SIMS and TDS data have also been studied in this paper. The result of the experiments show that a lower deposition temperature has a poorer film property and the post-thermal process can degas the unstable fluorine. The optimized combination of conditions, of fluorine-doped silicon dioxide deposition temperature and post-thermal treatment can create a good quality fluorine-doped silicon dioxide without a reliability issue.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121456694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993665
Y. Higuchi, Y. Kawaguchi, T. Sakazume
Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.
{"title":"Analysis TAT reduction by using emission-leakage failure analysis system","authors":"Y. Higuchi, Y. Kawaguchi, T. Sakazume","doi":"10.1109/ISSM.2000.993665","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993665","url":null,"abstract":"Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115129723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993670
H. Wakamatsu, M. Matsuki, N. Tanaka, H. Ogata, H. Iba, K. Murata
We have developed a new cooled-type 2-stage high-speed air washer treating technique to remove the high-concentration airborne molecular contaminants (AMC) in the outside air. This technique was applied in an air-conditioning system to treat the intake air of the clean room. The new air conditioning system can treat the AMC to a sufficiently lower concentration, which does not influence a semiconductor manufacturing process. By a new B-factor analysis, the effectiveness of the 1st-stage of the cooling condensation coil was found and the chemical ion removal mechanism of the new system was solved. The new system can remove both chemical contaminants of the water-solube and water-insolube variety. This new system can operate at almost the same initial and running costs as the conventional air-conditioning system without chemical contaminant countermeasures.
{"title":"High efficiency airborne molecular contaminants removal technology by a new cooled-type 2-stage high-speed air washer method","authors":"H. Wakamatsu, M. Matsuki, N. Tanaka, H. Ogata, H. Iba, K. Murata","doi":"10.1109/ISSM.2000.993670","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993670","url":null,"abstract":"We have developed a new cooled-type 2-stage high-speed air washer treating technique to remove the high-concentration airborne molecular contaminants (AMC) in the outside air. This technique was applied in an air-conditioning system to treat the intake air of the clean room. The new air conditioning system can treat the AMC to a sufficiently lower concentration, which does not influence a semiconductor manufacturing process. By a new B-factor analysis, the effectiveness of the 1st-stage of the cooling condensation coil was found and the chemical ion removal mechanism of the new system was solved. The new system can remove both chemical contaminants of the water-solube and water-insolube variety. This new system can operate at almost the same initial and running costs as the conventional air-conditioning system without chemical contaminant countermeasures.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115500925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993620
K. Takagaki, N. Matsumoto, L. Idera, T. Ishijima, Y. Ueda
We present a feed back process control model on a PC based process control support tool which was applied to the bottleneck of overlay and expose process in optical lithography process. It was successful in breaking the bottleneck.
{"title":"Breaking FAB constraint with implementing feedback process control","authors":"K. Takagaki, N. Matsumoto, L. Idera, T. Ishijima, Y. Ueda","doi":"10.1109/ISSM.2000.993620","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993620","url":null,"abstract":"We present a feed back process control model on a PC based process control support tool which was applied to the bottleneck of overlay and expose process in optical lithography process. It was successful in breaking the bottleneck.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993628
M. Kiyotoshi, S. Yamazaki, J. Nakahira, K. Eguchi, K. Hieda, H. Yamamoto, T. Umehara, K. Hasebe, T. Asano, K. Nakao, T. Arikado, K. Okumura
A hot-wall batch type BST-CVD tool with fast thermal processing (FTP) furnace and individual vaporizing liquid source supply system (ILSS) was developed for uniform deposition of BST. We also employed an in-situ multi-step (IMS) process that is sequential repetition of thin amorphous BST deposition and its crystallization in the same reactor to reconcile conformal BST deposition and good electrical performances. BST deposited by our hot-wall CVD shows slight substrate dependence (metal coated or not), therefore hotwall CVD is superior to a single slice tool for reduction of test wafer running. IMS deposited BST shows almost 100% step coverage, lower carbon impurity concentration than single step deposited BST and sufficient electrical characteristics (leakage current <10/sup -7/ A/cm/sup 2/, Teq<0.5 nm) for both SRO and Ru electrodes.
{"title":"Hot-wall batch-type CVD tool for high-k (Ba,Sr)TiO/sub 3/ capacitors","authors":"M. Kiyotoshi, S. Yamazaki, J. Nakahira, K. Eguchi, K. Hieda, H. Yamamoto, T. Umehara, K. Hasebe, T. Asano, K. Nakao, T. Arikado, K. Okumura","doi":"10.1109/ISSM.2000.993628","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993628","url":null,"abstract":"A hot-wall batch type BST-CVD tool with fast thermal processing (FTP) furnace and individual vaporizing liquid source supply system (ILSS) was developed for uniform deposition of BST. We also employed an in-situ multi-step (IMS) process that is sequential repetition of thin amorphous BST deposition and its crystallization in the same reactor to reconcile conformal BST deposition and good electrical performances. BST deposited by our hot-wall CVD shows slight substrate dependence (metal coated or not), therefore hotwall CVD is superior to a single slice tool for reduction of test wafer running. IMS deposited BST shows almost 100% step coverage, lower carbon impurity concentration than single step deposited BST and sufficient electrical characteristics (leakage current <10/sup -7/ A/cm/sup 2/, Teq<0.5 nm) for both SRO and Ru electrodes.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130027516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993636
Y. Kiuchi, M. Iji
A new environmentally friendly, self-extinguishing epoxy-resin compound with no flame-retardants (such as halogen derivatives) has been developed for integrated circuit (IC) packaging. This compound mainly consists of phenol-aralkyl-type epoxy resin and hardener both of which contain a multi-aromatic substituent, fused silica powder, and additives. The compound has a high flame retardancy resulting from the formation of a stable foam layer, which retards heat transfer on the surface of the resin compound during combustion. Furthermore, the compound shows other excellent characteristics as a molding compound for IC packages. In fact, its packaging-reliability characteristics, those including resistance to humidity, soldering heat, and the effects of high-temperature storage, are better than those of current molding compounds used for large-scale integration (LSI) packaging. The new molding compound has thus already been applied to IC packages such as ball grid arrays (BGAs).
{"title":"Environmentally conscious IC molding compound without toxic flame-retardants","authors":"Y. Kiuchi, M. Iji","doi":"10.1109/ISSM.2000.993636","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993636","url":null,"abstract":"A new environmentally friendly, self-extinguishing epoxy-resin compound with no flame-retardants (such as halogen derivatives) has been developed for integrated circuit (IC) packaging. This compound mainly consists of phenol-aralkyl-type epoxy resin and hardener both of which contain a multi-aromatic substituent, fused silica powder, and additives. The compound has a high flame retardancy resulting from the formation of a stable foam layer, which retards heat transfer on the surface of the resin compound during combustion. Furthermore, the compound shows other excellent characteristics as a molding compound for IC packages. In fact, its packaging-reliability characteristics, those including resistance to humidity, soldering heat, and the effects of high-temperature storage, are better than those of current molding compounds used for large-scale integration (LSI) packaging. The new molding compound has thus already been applied to IC packages such as ball grid arrays (BGAs).","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126629280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993616
D. Ganz, A. Charles, S. Hornig, G. Hraschan, Wolfram Koestler, J. Maltabes, T. Schedel, S. Schmidt, K. Mautz, R. Schuster
We study the performance of the current 300mm lithography tool set for sub 0.2 /spl mu/m processes. The results are discussed in terms of process capability and stability. It was determined that the non-linear errors which are much higher on 300 mm wafers than on 200 mm wafers had an influence, and this is discussed in detail. We determine the root causes for the stronger appearance of these effects and propose solutions to improve the overlay performance.
{"title":"Sub 0.2 /spl mu/m lithography on 300 mm wafer","authors":"D. Ganz, A. Charles, S. Hornig, G. Hraschan, Wolfram Koestler, J. Maltabes, T. Schedel, S. Schmidt, K. Mautz, R. Schuster","doi":"10.1109/ISSM.2000.993616","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993616","url":null,"abstract":"We study the performance of the current 300mm lithography tool set for sub 0.2 /spl mu/m processes. The results are discussed in terms of process capability and stability. It was determined that the non-linear errors which are much higher on 300 mm wafers than on 200 mm wafers had an influence, and this is discussed in detail. We determine the root causes for the stronger appearance of these effects and propose solutions to improve the overlay performance.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133875358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993622
F. J. Sànchez
Why is it that some people can perform a task with greater precision and accuracy than others? What knowledge do they possess that qualifies them as experts? How do they consistently outperform peers who follow the same set of procedures? In the past experts were interviewed to get the answers to these questions, but this was not always effective because often experts "don't know what they know." A method was needed to capture the subconscious knowledge of the expert as well as skill proficiency. Accelerated breakthrough systems (ABS) is a methodology that was developed to do just that. The goal is to capture expert knowledge and document best-known methods (BKMs) through video based observation, raising an entire work group's performance to the expert level. The ABS process is a proven methodology for capturing expert knowledge. The six-phase method is a documented system that can be applied to a variety of knowledge and tasks, making it transferable across any function. The process is lead by a certified ABS specialist. Organizations can apply the process to close performance gaps on critical tasks dealing with equipment, process, operations or abstract dynamic skills. The key is to identify and document expert subconscious knowledge. ABS "taps in" via videotape analysis.
{"title":"Capturing expert knowledge [semiconductor manufacturing]","authors":"F. J. Sànchez","doi":"10.1109/ISSM.2000.993622","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993622","url":null,"abstract":"Why is it that some people can perform a task with greater precision and accuracy than others? What knowledge do they possess that qualifies them as experts? How do they consistently outperform peers who follow the same set of procedures? In the past experts were interviewed to get the answers to these questions, but this was not always effective because often experts \"don't know what they know.\" A method was needed to capture the subconscious knowledge of the expert as well as skill proficiency. Accelerated breakthrough systems (ABS) is a methodology that was developed to do just that. The goal is to capture expert knowledge and document best-known methods (BKMs) through video based observation, raising an entire work group's performance to the expert level. The ABS process is a proven methodology for capturing expert knowledge. The six-phase method is a documented system that can be applied to a variety of knowledge and tasks, making it transferable across any function. The process is lead by a certified ABS specialist. Organizations can apply the process to close performance gaps on critical tasks dealing with equipment, process, operations or abstract dynamic skills. The key is to identify and document expert subconscious knowledge. ABS \"taps in\" via videotape analysis.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133080429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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