Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492476
Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, H. Yoo
An energy-efficient floating-point DNN training processor is proposed with heterogenous bfloat16 computing architecture using exponent computing-in-memory (CIM) and mantissa processing engine. Mantissa free exponent calculation enables pipelining of exponent and mantissa operation for heterogenous bfloat16 computing while reducing MAC power by 14.4 %. 6T SRAM exponent computing-in-memory with bitline charge reusing reduces memory access power by 46.4 %. The processor fabricated in 28 nm CMOS technology and occupies 1.62×3.6 mm2 die area. It achieves 13.7 TFLOPS/W energy efficiency which is 274× higher than the previous floating-point CIM processor.
{"title":"A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory","authors":"Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, H. Yoo","doi":"10.23919/VLSICircuits52068.2021.9492476","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492476","url":null,"abstract":"An energy-efficient floating-point DNN training processor is proposed with heterogenous bfloat16 computing architecture using exponent computing-in-memory (CIM) and mantissa processing engine. Mantissa free exponent calculation enables pipelining of exponent and mantissa operation for heterogenous bfloat16 computing while reducing MAC power by 14.4 %. 6T SRAM exponent computing-in-memory with bitline charge reusing reduces memory access power by 46.4 %. The processor fabricated in 28 nm CMOS technology and occupies 1.62×3.6 mm2 die area. It achieves 13.7 TFLOPS/W energy efficiency which is 274× higher than the previous floating-point CIM processor.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116697215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492453
Junjie Mu, Yuqi Su, Bongjin Kim
Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.
{"title":"A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems","authors":"Junjie Mu, Yuqi Su, Bongjin Kim","doi":"10.23919/VLSICircuits52068.2021.9492453","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492453","url":null,"abstract":"Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121678073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492374
Rohit Rothe, Minchang Cho, K. Choo, Seokhyeon Jeong, D. Sylvester, D. Blaauw
We present an acoustic analog front-end with a 100TΩ feedback resistance that is robust to PT variation (1.8× deviation across –40 to 80°C and 0.035× σ/µ across 16 measured samples) and achieves a 3.3× reduction in input referred noise (IRN). It eliminates an input frequency and phase dependent systematic offset introduced by a similar previous technique [5] and introduces automatic saturation detection and feedback resistance modulation for fast amplifier restabilization, yielding 10× improvement in artifact recovery time. The technique was implemented in a 192 nW LNA + PGA + ADC chain.
{"title":"A 192 nW 0.02 Hz High Pass Corner Acoustic Analog Front-End with Automatic Saturation Detection and Recovery","authors":"Rohit Rothe, Minchang Cho, K. Choo, Seokhyeon Jeong, D. Sylvester, D. Blaauw","doi":"10.23919/VLSICircuits52068.2021.9492374","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492374","url":null,"abstract":"We present an acoustic analog front-end with a 100TΩ feedback resistance that is robust to PT variation (1.8× deviation across –40 to 80°C and 0.035× σ/µ across 16 measured samples) and achieves a 3.3× reduction in input referred noise (IRN). It eliminates an input frequency and phase dependent systematic offset introduced by a similar previous technique [5] and introduces automatic saturation detection and feedback resistance modulation for fast amplifier restabilization, yielding 10× improvement in artifact recovery time. The technique was implemented in a 192 nW LNA + PGA + ADC chain.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492472
E. Shim, Kyungho Lee, J. Pyo, Wooseok Choi, Jungbin Yun, T. Jung, Kyungduck Lee, Seyoung Kim, Chanhee Lee, Seungki Baek, Hyuncheol Kim, Sungsoo Choi, Junseok Yang, Kyoungmok Son, Jongwon Choi, Howoo Park, Bumsuk Kim, JungChak Ahn, Duckhyun Chang
We developed a dual pixel with accurate and all-directional auto focus (AF) performance in CMOS image sensor (CIS). The optimized in-pixel deep trench isolation (DTI) provided accurate AF data and good image quality in the entire image area and over whole visible wavelength range. Furthermore, the horizontal-vertical (HV) dual pixel with the slanted in-pixel DTI enabled the acquisition of all-directional AF information by the conventional dual pixel readout method. These technologies were demonstrated in 1.4μm dual pixel and will be applied to the further shrunken pixels.
{"title":"All-Directional Dual Pixel Auto Focus Technology in CMOS Image Sensors","authors":"E. Shim, Kyungho Lee, J. Pyo, Wooseok Choi, Jungbin Yun, T. Jung, Kyungduck Lee, Seyoung Kim, Chanhee Lee, Seungki Baek, Hyuncheol Kim, Sungsoo Choi, Junseok Yang, Kyoungmok Son, Jongwon Choi, Howoo Park, Bumsuk Kim, JungChak Ahn, Duckhyun Chang","doi":"10.23919/VLSICircuits52068.2021.9492472","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492472","url":null,"abstract":"We developed a dual pixel with accurate and all-directional auto focus (AF) performance in CMOS image sensor (CIS). The optimized in-pixel deep trench isolation (DTI) provided accurate AF data and good image quality in the entire image area and over whole visible wavelength range. Furthermore, the horizontal-vertical (HV) dual pixel with the slanted in-pixel DTI enabled the acquisition of all-directional AF information by the conventional dual pixel readout method. These technologies were demonstrated in 1.4μm dual pixel and will be applied to the further shrunken pixels.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127463555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492480
Do-Yeon Yoon, Sonal Pinto, SungWon Chung, P. Merolla, Thong-Wei Koh, D. Seo
A fully implantable brain-machine interface (BMI) targeting clinical applications has stringent size and power requirements. In this paper we present a 5×4mm2 neural system-on-chip (SoC) capable of recording and stimulating from 1024 implanted electrodes via a serial digital link. The design has on-chip configurable spike detection that can reduce off-chip bandwidth by 1250×. With fully integrated power management circuitry with power-on-reset and brown-out detection, our design consumes 24.7mW total power consumption, making it the lowest-power, highest-density AC-coupled neural SoC reported for recording both local field potential (LFP) and action potential (AP) with a 5Hz-10kHz bandwidth.
{"title":"A 1024-Channel Simultaneous Recording Neural SoC with Stimulation and Real-Time Spike Detection","authors":"Do-Yeon Yoon, Sonal Pinto, SungWon Chung, P. Merolla, Thong-Wei Koh, D. Seo","doi":"10.23919/VLSICircuits52068.2021.9492480","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492480","url":null,"abstract":"A fully implantable brain-machine interface (BMI) targeting clinical applications has stringent size and power requirements. In this paper we present a 5×4mm2 neural system-on-chip (SoC) capable of recording and stimulating from 1024 implanted electrodes via a serial digital link. The design has on-chip configurable spike detection that can reduce off-chip bandwidth by 1250×. With fully integrated power management circuitry with power-on-reset and brown-out detection, our design consumes 24.7mW total power consumption, making it the lowest-power, highest-density AC-coupled neural SoC reported for recording both local field potential (LFP) and action potential (AP) with a 5Hz-10kHz bandwidth.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127490601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492341
Kyung-Sik Choi, J. Ko, Sang-Gug Lee
This work presents a current-mode inverse Class-D digital PA (DPA) with enhanced power back-off (PBO) efficiency. The PA adopts extra switches, which allows the scaling in the output voltage swing by half, leading to (theoretically) 6 dB enhancement in PBO efficiency while maintaining (ideally) 100% drain efficiency (DE). Implemented in a 65 nm CMOS, the proposed DPA shows the improvement in DE by ×1.5 at 4.2 dB PBO in comparison with normalized Class-B PA while requiring only one transformer and single-supply voltage.
这项工作提出了一种具有增强功率回退(PBO)效率的电流模式逆d类数字PA (DPA)。PA采用额外的开关，允许将输出电压摆幅缩放一半，导致PBO效率(理论上)提高6 dB，同时保持(理想)100%漏极效率(DE)。在65nm CMOS上实现的DPA在4.2 dB PBO下的DE比标准化的b类PA提高×1.5，而只需要一个变压器和单电源电压。
{"title":"A Single-Supply Single-Core Inverse Class-D Digital Power Amplifier with Enhanced Power Back-Off Efficiency Adopting Output Power Scaling Technique","authors":"Kyung-Sik Choi, J. Ko, Sang-Gug Lee","doi":"10.23919/VLSICircuits52068.2021.9492341","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492341","url":null,"abstract":"This work presents a current-mode inverse Class-D digital PA (DPA) with enhanced power back-off (PBO) efficiency. The PA adopts extra switches, which allows the scaling in the output voltage swing by half, leading to (theoretically) 6 dB enhancement in PBO efficiency while maintaining (ideally) 100% drain efficiency (DE). Implemented in a 65 nm CMOS, the proposed DPA shows the improvement in DE by ×1.5 at 4.2 dB PBO in comparison with normalized Class-B PA while requiring only one transformer and single-supply voltage.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127952118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492366
Sujin Park, Hyungil Chae, Seonghwan Cho
This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) ∆Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP ∆Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs.
{"title":"A 3.68aFrms Resolution 183dB FoMs 4th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS","authors":"Sujin Park, Hyungil Chae, Seonghwan Cho","doi":"10.23919/VLSICircuits52068.2021.9492366","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492366","url":null,"abstract":"This paper presents an ultra-high-resolution energy-efficient 4th-order continuous-time (CT) bandpass (BP) ∆Σ capacitance-to-digital converter (CDC) where thermal noise folding is avoided by CT operation and power is saved by using a BP ∆Σ architecture. The proposed CDC achieves a resolution of 3.68 aFrms at room temperature while achieving a Schreier figure-of-merit (FoMS) of 183dB which is more than 2x improvement over the state-of-the-art CDCs.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492419
Yu Zhao, B. Razavi
A PLL samples both the rising and falling edges of the reference clock and employs a new retiming method in the feedback divider. Fabricated in 28-nm CMOS technology, the prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of −66 dBc while consuming 12 mW.
{"title":"A 19-GHz PLL with 20.3-fs Jitter","authors":"Yu Zhao, B. Razavi","doi":"10.23919/VLSICircuits52068.2021.9492419","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492419","url":null,"abstract":"A PLL samples both the rising and falling edges of the reference clock and employs a new retiming method in the feedback divider. Fabricated in 28-nm CMOS technology, the prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of −66 dBc while consuming 12 mW.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492505
Keonhee Cho, Heekyung Choi, I. Jung, J. Oh, Tae Woo Oh, Kiryong Kim, Gi-Kryang Kim, T. Choi, Changsoo Sim, T. Song, Seong-ook Jung
This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.
{"title":"SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling","authors":"Keonhee Cho, Heekyung Choi, I. Jung, J. Oh, Tae Woo Oh, Kiryong Kim, Gi-Kryang Kim, T. Choi, Changsoo Sim, T. Song, Seong-ook Jung","doi":"10.23919/VLSICircuits52068.2021.9492505","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492505","url":null,"abstract":"This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131082936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492467
Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, E. Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, P. Upadhyaya, Y. Frans
This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate voltage-mode transmitter implements delay based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC PLL is distributed to eight transceiver channels. In each channel, an ILO generates eight-phase clocks that feed an 8-bit CMOS PI. The transceiver achieves <1e-12 BER over 30mm channel @106.25Gb/s and over 20mm channel @112Gb/s.
{"title":"A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET","authors":"Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, E. Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, P. Upadhyaya, Y. Frans","doi":"10.23919/VLSICircuits52068.2021.9492467","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492467","url":null,"abstract":"This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12 data slicers and 2 error slicers. The quad-rate voltage-mode transmitter implements delay based sub-UI two-tap FFE and digital I/Q and DCC clock calibration. A single-phase clock from a wideband LC PLL is distributed to eight transceiver channels. In each channel, an ILO generates eight-phase clocks that feed an 8-bit CMOS PI. The transceiver achieves <1e-12 BER over 30mm channel @106.25Gb/s and over 20mm channel @112Gb/s.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132574360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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