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Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm Versa:一个以数据流为中心的多处理器,具有36个收缩期ARM Cortex-M4F内核和可重构的28纳米交叉条形内存结构
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492391
Sung Kim, Morteza Fayazi, A. Daftardar, Kuan-Yu Chen, Jielun Tan, S. Pal, T. Ajayi, Yan Xiong, T. Mudge, C. Chakrabarti, D. Blaauw, R. Dreslinski, Hun-Seok Kim
We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristics in order to optimize bandwidth, access latency, and data reuse. Measured on a set of kernels with diverse data access, control, and synchronization characteristics, reconfiguration between different Versa modes yields median energy-efficiency improvements of 11.6× and 37.2× over mobile CPU and GPU baselines, respectively.
我们提出了Versa,一个具有36个收缩ARM Cortex-M4F内核和运行时可重构内存层次结构的节能处理器。Versa利用特定于算法的特性来优化带宽、访问延迟和数据重用。在一组具有不同数据访问、控制和同步特性的内核上进行测量,不同Versa模式之间的重新配置比移动CPU和GPU基线分别产生11.6倍和37.2倍的中位数能效改进。
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引用次数: 3
A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier 带级联无负载电容式插值DAC和6.24V/μs慢速缓冲放大器的12位移动OLED/μLED显示驱动IC
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492490
Gyeong-Gu Kang, Seok-Tae Koh, W. Jang, Ji-Hun Lee, Seongjoo Lee, O. Kwon, K. Jung, Hyunsik Kim
This paper presents an OLED/μLED display driver IC with cascaded loading-free capacitive interpolation (LFCI) DAC and a high-slew buffer amplifier. The 12-bit color-depth is realized by a combination of 7-bit R-DAC and proposed 5-bit LFCI DAC while occupying only 295×17μm2, which is ×2 reduction compared to the state-of-the-art. In-pixel MSB-conversion is also presented to reduce chip size further. 5V amplifier offers a slew-rate of 6.24V/μs at 80pF with a static current of 2μA. The chip fabricated in 180-nm achieved the measured 0.43LSB (DNL), 0.95LSB (INL), and 7.9mV (DVO).
提出了一种采用级联无负载电容式插值(LFCI) DAC和高摆位缓冲放大器的OLED/μLED显示驱动集成电路。12位色深是由7位R-DAC和建议的5位LFCI DAC的组合实现的,而仅占用295×17μm2,与最先进的相比减少了×2。为了进一步减小芯片尺寸,还提出了像素内的msb转换。5V放大器在80pF时的自变速率为6.24V/μs,静态电流为2μA。该芯片在180纳米制程上实现了0.43LSB (DNL)、0.95LSB (INL)和7.9mV (DVO)的测量值。
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引用次数: 4
HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing HERMES Core -基于14nm CMOS和pcm的内存计算核心,采用300ps/LSB线性化cco adc阵列和本地数字处理
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492362
R. Khaddam-Aljameh, M. Stanisavljevic, J. F. Mas, G. Karunaratne, M. Braendli, Femg Liu, Abhairaj Singh, S. M. Müller, U. Egger, A. Petropoulos, T. Antonakopoulos, K. Brew, Samuel Choi, I. Ok, F. Lie, N. Saulnier, V. Chan, I. Ahsan, V. Narayanan, S. Nandakumar, M. L. Gallo, P. Francese, A. Sebastian, E. Eleftheriou
We present a 256×256 in-memory compute (IMC) core designed and fabricated in 14nm CMOS with backend-integrated multi-level phase-change memory (PCM). It comprises 256 linearized current controlled oscillator (CCO)-based ADCs at a compact 4µm pitch and a local digital processing unit performing affine scaling and ReLU operations A novel frequency-linearization technique for CCOs is introduced, leading to accurate on-chip matrix-vector-multiply (MVM) when operating over 1 GHz. Measured classification accuracies on MNIST and CIFAR-10 datasets are presented when two cores are employed for deep learning (DL) inference The measured energy efficiency is 10.5 TOPS/W at a performance density of 1.59 TOPS/mm2.
我们提出了一种基于后端集成多级相变存储器(PCM)的14nm CMOS设计和制造的256×256内存计算(IMC)内核。它包括256个基于线性化电流控制振荡器(CCO)的adc,间距紧凑,为4µm,以及一个执行仿射缩放和ReLU操作的本地数字处理单元。介绍了用于CCO的新型频率线性化技术,当工作频率超过1 GHz时,可实现精确的片上矩阵矢量乘法(MVM)。在MNIST和CIFAR-10数据集上,当使用两个核心进行深度学习推理时,测量到的分类精度为10.5 TOPS/W,性能密度为1.59 TOPS/mm2。
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引用次数: 52
[VLSI Circuits 2021 Front cover] [VLSI电路2021封面]
Pub Date : 2021-06-13 DOI: 10.23919/vlsicircuits52068.2021.9492433
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引用次数: 0
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning n - core -一种高效和可扩展的深度学习方法
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492395
Ken Namura, Johannes Maximilian Kühn, T. Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian K. Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino
MN-Core is a highly efficient deep learning training accelerator reaching in excess of 1 TFLOPS/W (half-precision) at board level in real-world mixed-precision workloads. To reach and sustain this level of performance, the design is partitioned and packaged as four-die MCM package exceeding 3000mm2 of die area.
MN-Core是一款高效的深度学习训练加速器,在实际的混合精度工作负载中,在板级达到超过1 TFLOPS/W(半精度)。为了达到并维持这一性能水平,该设计被分割并封装为超过3000mm2的四模MCM封装。
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引用次数: 1
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA PETRA:一个22nm的6.97TFLOPS/W aib支持的可配置矩阵和卷积加速器,集成了Intel Stratix 10 FPGA
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492517
Sung-gun Cho, Wei-Chien Tang, Chester Liu, Zhengya Zhang
PETRA is a configurable FP16 matrix multiplication and convolution accelerator designed to be 2.5D integrated using Advanced Interface Bus (AIB). PETRA is built upon four 16×16 systolic arrays, but it employs a configurable H-tree accumulation to improve both the latency and the utilization by up to 8×. A 22nm 3.04mm2 PETRA prototype provides 1.433TFLOPS in computing matrix-matrix multiplication (MMM) and convolution (conv) at 0.88V, and it achieves a 6.97TFLOPS/W peak efficiency at 0.7V. PETRA is integrated with an Intel Stratix 10 FPGA in a multi-chip package (MCP) to provide the flexibility of FPGA and the performance and efficiency of PETRA.
PETRA是一款可配置的FP16矩阵乘法和卷积加速器,设计为2.5D集成,使用高级接口总线(AIB)。PETRA建立在4个16×16收缩阵列上,但它采用可配置的h树积累来提高延迟和利用率,最高可达8倍。一个22nm的3.04mm2 PETRA原型在0.88V下提供1.433TFLOPS计算矩阵乘法(MMM)和卷积(conv),在0.7V下实现6.97TFLOPS/W的峰值效率。PETRA与Intel Stratix 10 FPGA集成在一个多芯片封装(MCP)中,以提供FPGA的灵活性和PETRA的性能和效率。
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引用次数: 2
16MB High Density Embedded PCM macrocell for automotive-grade microcontroller in 28nm FD-SOI, featuring extension to 24MB for Over-The-Air software update 16MB高密度嵌入式PCM macrocell用于28nm FD-SOI的汽车级微控制器,具有扩展到24MB的无线软件更新功能
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492465
F. Disegni, A. Ventre, A. Molgora, P. Cappelletti, R. Badalamenti, P. Ferreira, G. Castagna, A. Cathelin, A. Gandolfo, A. Redaelli, D. Manfrè, A. Maurelli, C. Torti, F. Piazza, M. Carfì, F. Arnaud, M. Perroni, M. Caruso, S. Pezzini, R. Annunziata, G. Piazza, O. Weber, M. Peri
This paper proposes a 16MB e-NVM macrocell for automotive grade 0 microcontroller based on a PCM cell with a Bipolar Transistor (BJT) selector. The solution is developed in proprietary 28nm FD-SOI CMOS technology, with a Super-STI scheme that has enabled high dense e-NVM with 0.019µm2 cell size [1]. Macrocell organization offers the capability to be configured by application either for Over-The-Air (OTA) mode up to 24MB, or for 16MB extra reliability mode, with two cells per bit, still resulting in an extremely competitive equivalent bit-cell size (0.038µm2). Cell Mode configuration can be dynamically tuned, with a unique set of features for flexible assisted OTA software update. The integration of a 16MB PCM cell array, extensible up to 24MB, in an automotive grade product-like test vehicle chip is presented here as the evolution of the first Embedded PCM macrocell for automotive [2], complementing, the fulfillment of all criteria in the demanding automotive environment [3] [4].
本文提出了一种用于汽车0级微控制器的16MB e-NVM宏单元,该宏单元基于带双极晶体管(BJT)选择器的PCM单元。该解决方案采用专有的28nm FD-SOI CMOS技术开发,采用Super-STI方案,实现了0.019µm2电池尺寸的高密度e-NVM[1]。Macrocell组织提供了可根据应用进行配置的功能,无论是高达24MB的无线(OTA)模式,还是16MB的额外可靠性模式,每比特两个单元,仍然产生极具竞争力的等效位单元大小(0.038µm2)。Cell Mode配置可以动态调整,具有一组独特的功能,可灵活辅助OTA软件更新。将16MB PCM单元阵列集成到汽车级产品级测试车辆芯片中,可扩展到24MB,这是第一个用于汽车的嵌入式PCM宏单元的演变[2],补充了苛刻的汽车环境中的所有标准[3][4]。
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引用次数: 2
A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS 基于电磁耦合d类LC振荡器的2.3GHz全集成DC-DC变换器,在22nm FDSOI CMOS中实现78.1%的效率
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492491
Alessandro Novello, Gabriele Atzeni, Giorgio Cristiano, Mathieu Coustans, Taekwang Jang
A fully integrated DC-DC converter based on electromagnetically coupled class-D LC oscillators achieving 0.42-3.2W/mm2 power density and 69.4-78.1% efficiency is demonstrated in a 22nm FDSOI CMOS technology. This work proposes on-chip 8-shaped and vertically stacked transformers, which are orthogonally placed for the high-power density, low undesired coupling coefficient and small electromagnetic interference (EMI) radiation. In addition, the output ripple is <10mV without attaching any output capacitor thanks to the 4-phase electromagnetic power delivery scheme. The converter also offers a duty cycled operation mode that enables <2% efficiency degradation down to 100μW. The total chip area is 0.59mm2 for 5.9nH inductance (high efficiency version) and 0.22mm2 for 3.9nH (high power density versions).
采用22nm FDSOI CMOS技术,实现了一种基于电磁耦合d类LC振荡器的全集成DC-DC变换器,功率密度为0.42-3.2W/mm2,效率为69.4-78.1%。本工作提出了片上8形垂直堆叠变压器,其正交放置具有高功率密度,低期望耦合系数和小电磁干扰(EMI)辐射。此外,由于采用4相电磁供电方案,在不附加任何输出电容的情况下,输出纹波<10mV。转换器还提供了一个占空比工作模式,使<2%的效率下降到100μW。对于5.9nH电感(高效率版本),总芯片面积为0.59mm2,对于3.9nH电感(高功率密度版本),总芯片面积为0.22mm2。
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引用次数: 1
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope 峰值功率2.5 μ w、无锁相环WiFi后向散射通信的无电池物联网传感器节点
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492358
Longyang Lin, K. Ahmed, P. Salamani, M. Alioto
A system on chip including 802.11b WiFi communications is introduced to demonstrate battery-less operation for low-cost mm-scale sensor nodes. µW peak power is enabled by PLL-less WiFi backscattering communications and event-driven frequency regulation to compensate environmental variations. A 180nm testchip integrating the entire signal chain from any of four sensor interfaces to wireless communications with a commercial WiFi router exhibits 2.5µW total power.
介绍了一种包含802.11b WiFi通信的片上系统,以演示低成本毫米级传感器节点的无电池操作。µW峰值功率通过无锁相环WiFi后向散射通信和事件驱动频率调节来补偿环境变化。180nm测试芯片集成了从四个传感器接口中的任何一个到与商用WiFi路由器无线通信的整个信号链,总功率为2.5 μ W。
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引用次数: 10
A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application 一款28nm嵌入式闪存,具有100MHz读取操作和7.42Mb/mm2, 0.85V,适用于汽车应用
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492384
Hyunjin Shin, Myeonghee Oh, Jaeseung Choi, T. Song, J. Kye
A 28nm embedded Flash memory in this paper is designed for the Automotive application in Foundry. Through Temperature Auto-Tracking Sense Amplifier using the Bit line Charge Boost (BCB) and Bit line Leakage current Compensation (BLC) technology, it succeeded in implementing under 10ns read operation (>100MHz) and size improvement (7.42Mb/mm2). Also Word Line and YMUX Gate Boost (WYGB) is applied to secure a sensing margin at a low voltage (0.85V). These techniques enable 10ns reading operation of 288 bits (26.8Gb/s) at a time based on 16Mb memory size by improving sensing margin in temperature range of -40~150’C. It also implemented a competitive minimum IP size and we have secured high yield that enough to mass production as a result of Silicon validation. Based on competitive advantage through technology differentiation, it will be provided to various customers in all eFlash IP Foundry markets including Automotive business.
本文设计了一种28nm嵌入式快闪存储器,用于汽车代工应用。通过采用位线电荷增强(BCB)和位线漏电流补偿(BLC)技术的温度自动跟踪感测放大器,成功地实现了10ns读取操作(>100MHz)和尺寸改进(7.42Mb/mm2)。此外,字线和YMUX栅极升压(WYGB)用于确保低电压(0.85V)下的感应裕度。这些技术通过提高在-40~150℃温度范围内的感知裕度,在16Mb内存大小的基础上实现了10ns读取288位(26.8Gb/s)的操作。它还实现了具有竞争力的最小IP尺寸,并且由于硅验证,我们已经获得了足以大规模生产的高产量。基于技术差异化的竞争优势,它将提供给包括汽车业务在内的所有eFlash IP代工市场的各种客户。
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引用次数: 2
期刊
2021 Symposium on VLSI Circuits
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