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2021 Symposium on VLSI Circuits最新文献

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A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW 一个紧凑的8位,8 GS/s 8×TI SAR ADC, 16nm, 45dB SNDR和5ghz ERBW
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492512
E. Martens, D. Dermit, M. Shrivas, Shun Nagata, J. Craninckx
We present a time-interleaved (TI) SAR ADC with 8 channels realizing 8-bit conversion at 1 GS/s each. SNDR is 45 dB at low frequency with an ERBW of 5 GHz limited by sampler distortion. Conventional SAR conversion at high speed with minimum degradation is achieved by leveraging techniques such as early quantization, minimum delay logic, DAC redundancy and gain and offset compensation via the DAC. At 8 GS/s the ADC consumes 26 mW resulting in an efficiency of 30 fJ/conv.-step.
我们提出了一个具有8个通道的时间交错(TI) SAR ADC,每个通道实现1 GS/s的8位转换。低频时SNDR为45 dB,受采样器失真限制,ERBW为5 GHz。通过利用早期量化、最小延迟逻辑、DAC冗余以及通过DAC的增益和偏移补偿等技术,实现了具有最小退化的高速传统SAR转换。在8gs /s时,ADC的功耗为26mw,效率为30fj /转换步。
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引用次数: 6
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density 全数字自校准解码器,亚µW, 1.6fJ/convstep和0.0075mm2每个受体缩放到类似人类的触觉感应密度
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492329
Prachi Agarwal, V. Rajanna, Toh Wei Da, Benjamin C. K. Tee, M. Alioto
This work presents an area- and energy-efficient decoder for tactile e-skin sensing encoding to scale up receptor density to the human scale. A fully-digital signal-adaptive receptor interface and event decoder architecture are introduced, leveraging temporal/spatial tactile signal sparsity to dynamically reduce activity and time resolution at negligible accuracy degradation. A novel reference-less self-calibrating senseamp is introduced to cancel offset by exploiting the statistical balance of spread-spectrum tactile pulses and noise. The 40nm testchip shows 1.6-fJ/convstep energy (0.0075mm2 area) per receptor with 50X (5X) improvement over prior art, and 80-receptor e-skin aggregation on a single pad.
这项工作提出了一种面积和节能的解码器,用于触觉电子皮肤传感编码,将受体密度扩大到人体尺度。介绍了全数字信号自适应受体接口和事件解码器架构,利用时间/空间触觉信号稀疏性在可忽略不计的精度退化下动态减少活动和时间分辨率。利用扩频触觉脉冲和噪声的统计平衡,提出了一种新的无参考自校准传感器来抵消偏移量。40nm测试芯片显示每个受体1.6 fj /convstep能量(0.0075mm2面积),比现有技术提高50倍(5X),并在单个衬垫上聚集80个受体电子皮肤。
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引用次数: 0
A New Era of Tailored Computing 定制计算的新时代
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492400
M. Papermaster, S. Kosonocky, G. Loh, S. Naffziger
The worldwide computing market grew tremendously over the past decades, and looking toward the future, these trends do not appear to be slowing down. Moore’s Law coupled with incredible innovation in hardware and software are engines driving this growth. However, the entire industry faces a barrage of challenges including the slowing of Moore’s Law, stringent power and energy constraints, an always-connected society, and disruptions from the on-going artificial intelligence revolution. To continue delivering ever higher-performance computing solutions amid these difficulties, the industry needs to pivot to a new mindset of "Tailored Computing." The need for and opportunities to tailor our technologies in all aspects of future compute will propel the industry toward heterogeneity in everything it does.
在过去的几十年里,全球计算市场增长迅猛,展望未来,这些趋势似乎不会放缓。摩尔定律加上令人难以置信的硬件和软件创新是推动这一增长的引擎。然而,整个行业面临着一系列挑战,包括摩尔定律的放缓、严格的电力和能源限制、始终连接的社会,以及正在进行的人工智能革命带来的破坏。为了在这些困难中继续提供更高性能的计算解决方案,业界需要转向“量身定制计算”的新思维。在未来计算的各个方面定制我们的技术的需求和机会将推动行业在其所做的一切中实现异构。
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引用次数: 2
Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process 在零变化45纳米CMOS-SOI工艺中用于内窥镜成像的完全集成电子-光子超声接收器阵列
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492412
P. Zarkos, S. Buchbinder, C. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, J. Whinnery, Pavan Bhargava, V. Stojanović
This paper presents the first fully integrated 2-D array of electronic-photonic ultrasound sensors targeting low-power miniaturized ultrasound probes for endoscopic applications. Fabricated in a zero-change 45nm CMOS-SOI technology this Electronic-Photonic System on Chip (EPSoC), utilizes micro-ring resonators (MRRs) as ultrasound sensors instead of the traditional piezoelectric or capacitive micromachined transducers (PMUTs or CMUTs). The photonic nature of the sensor enables remoting the power-hungry receive electronics outside the probe tip, lowering the power dissipation inside the human body, eliminates the electrical cabling and reduces fiber count by 4x using wavelength division multiplexed (WDM) MRR sensors coupled onto the same waveguide. The photonic sensing element demonstrates >30 MHz bandwidth, and 7.3 mV/kPa sensitivity, while consuming 0.43 mW of power.
本文介绍了第一个完全集成的二维电子-光子超声传感器阵列,目标是用于内窥镜应用的低功耗小型化超声探头。该电子-光子片上系统(EPSoC)采用零变化45nm CMOS-SOI技术制造,利用微环谐振器(mrr)代替传统的压电或电容式微机械换能器(PMUTs或CMUTs)作为超声传感器。该传感器的光子特性使其能够将耗电的接收电子设备移至探头尖端之外,降低人体内部的功耗,消除了电缆,并使用耦合在同一波导上的波分复用(WDM) MRR传感器将光纤数量减少了4倍。该光子传感元件带宽>30 MHz,灵敏度为7.3 mV/kPa,功耗为0.43 mW。
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引用次数: 2
Ultra High Power Cooling Solution for 3D-ICs 3d - ic超高功率散热解决方案
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492489
C. J. Wu, S. Hsiao, J. Wang, W. H. Lin, C. W. Chang, T. Shao, C. Tung, Doug C. H. Yu
A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.
提出了一种采用熔合硅盖的直接硅水冷却方案。作为一种有效的散热解决方案,它在单个SoC上的总功率>2600 W,相当于4.8 W/mm2的功率密度。低温逻辑芯片与硅盖熔合,硅盖采用沟槽/栅格冷却结构,使有源器件与冷却水之间的热阻最小,冷却效率最佳。逻辑芯片硅背面的直接水冷也已被证明功率密度优于7 W/mm2。
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引用次数: 5
A ±2A/15A Current Sensor with 1.4 μA Supply Current and ±0.35%/0.6% Gain Error From −40 to 85°C using an Analog Temperature-Compensation Scheme ±2A/15A电流传感器,1.4 μA电源电流,±0.35%/0.6%增益误差,−40至85°C,采用模拟温度补偿方案
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492361
R. Zamparette, K. Makinwa
This paper presents a ±2A fully-integrated current sensor with a 20 mΩ on-chip shunt (resistor). It employs an energy-efficient hybrid sigma-delta ADC with an FIR-DAC and consumes only 1.4 μA, a 3× improvement on the state-of-the-art. A tunable analog non-linear temperature-compensation scheme (TCS) allows ±2A currents to be digitized with 0.35% gain error from −40 to 85°C. With a 3 mΩ PCB shunt, ±15A currents can be digitized with slightly more (0.6%) gain error. In a 0.18 μm CMOS process, the sensor occupies 1.6 mm2.
本文介绍了一个±2A全集成电流传感器与20 mΩ片上分流(电阻)。它采用具有FIR-DAC的高能效混合σ - δ ADC,功耗仅为1.4 μA,是目前最先进产品的3倍。可调谐模拟非线性温度补偿方案(TCS)允许±2A电流在−40至85°C范围内数字化,增益误差为0.35%。使用3 mΩ PCB分流器,±15A电流可以数字化,增益误差略大(0.6%)。在0.18 μm CMOS工艺中,传感器占地1.6 mm2。
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引用次数: 8
A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement 基于失配补偿和随机噪声增强的0.186 pj / Bit锁存真随机数发生器
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492474
Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, F. Yang, Kunyang Liu, H. Shinohara
A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3~1.0 V) and temperature (−20~100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).
提出了一种基于校准和反馈无控制锁存的真随机数发生器(TRNG)。它具有失配自补偿和随机噪声增强技术,大大提高了噪声与失配比。通过使用4位熵源的异或函数,该TRNG可以在宽电压(0.3~1.0 V)和温度(- 20~100°C)范围内有效地工作。采用8位冯·诺伊曼等待后处理技术(VN8W)提取全熵比特流,并通过NIST-SP 800-22随机测试验证。同时还证明了该方法对电源噪声注入攻击的鲁棒性。所提出的TRNG采用130纳米CMOS技术制造,在0.3 V下实现了0.186 pJ/bit的最新能量,核心面积为661 um2 (0.039 MF2)。
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引用次数: 6
[VLSI Circuits 2021 Welcome] [VLSI电路2021欢迎]
Pub Date : 2021-06-13 DOI: 10.23919/vlsicircuits52068.2021.9492389
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引用次数: 0
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range 在>100mV供电范围内实现≤0.12% INL/范围的前馈和反馈等斜率28nm CMOS数模变换器
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492452
Peng Chen, Feifei Zhang, Suoping Hu, R. Staszewski
Advanced techniques focusing on ultra-low jitter and spurs in integer-N PLLs, such as subsampling, injection locking and type-I architectures, have been extensively explored in the last decade. To accommodate new communication protocols, it is more attractive to push these high performance PLLs to a fractional-N operation. One major issue related to the fractional-N PLLs are fractional spurs, especially the in-band spurs that cannot be simply filtered out by the PLL loop but which can ruin the spectral performance. Phase interpolators (PI) and digital-to-time converters (DTC) are commonly used to assist in reducing the phase detection quantization error. The linearity, range, jitter and power are the main trade-offs in these blocks’ design. A DTC with >9-b (<0.2% INL/range) linearity is favored in the fractional-N PLLs targeting <-50dBc in-band fractional spurs. This work presents techniques to minimize the nonlinearities and power in the proposed constant slope DTC. Figure 1 shows the complete schematic of the proposed design. With feedforward (FF) and feedback (FB) techniques and nonlinearity cancellation, the implemented DTC runs at 50MHz and features 543ps delay range, 0.11% INL/Range, 36uW power consumption.
在过去的十年中,针对整数n锁相环的超低抖动和杂散的先进技术,如子采样、注入锁定和i型结构,已经得到了广泛的探索。为了适应新的通信协议,将这些高性能锁相环推向分数n操作更具吸引力。与分数n锁相环相关的一个主要问题是分数杂散,特别是带内杂散,它不能被锁相环简单地滤除,但会破坏频谱性能。相位插补器(PI)和数字时间转换器(DTC)通常用于帮助减少相位检测量化误差。线性度,范围,抖动和功率是这些模块设计中的主要权衡。线性度>9-b (<0.2% INL/range)的DTC在针对<-50dBc带内分数阶杂散的分数n锁相环中更受青睐。这项工作提出的技术,以尽量减少非线性和功率在拟议的恒斜率直接转矩控制。图1显示了建议设计的完整示意图。采用前馈(FF)和反馈(FB)技术以及非线性消除,实现的DTC工作频率为50MHz,延迟范围为543ps, INL/ range为0.11%,功耗为36w。
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引用次数: 1
A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing 一种5nm高k金属栅极fet CMOS 16Kb反熔丝一次性可编程存储器,具有自启动高压方案、读端点检测和伪差分传感
Pub Date : 2021-06-13 DOI: 10.23919/VLSICircuits52068.2021.9492438
S. Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, P. Fan, Chia-En Huang, Y. Chih, Yih Wang, Jonathan Chang
A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb for in-field programming in 5nm SoC and 10 years of data retention at 125°C.
首次在5nm高k金属栅极FinFET CMOS中制备了16Kb一次性可编程(OTP)防熔丝存储器。采用自引导高压方案(BHVS)、读取端点检测(REPD)和伪差分传感(PDS),实现了5nm SoC现场编程的内在误码率(BER)低于1ppb,并在125°C下保持了10年的数据。
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引用次数: 0
期刊
2021 Symposium on VLSI Circuits
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