Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492329
Prachi Agarwal, V. Rajanna, Toh Wei Da, Benjamin C. K. Tee, M. Alioto
This work presents an area- and energy-efficient decoder for tactile e-skin sensing encoding to scale up receptor density to the human scale. A fully-digital signal-adaptive receptor interface and event decoder architecture are introduced, leveraging temporal/spatial tactile signal sparsity to dynamically reduce activity and time resolution at negligible accuracy degradation. A novel reference-less self-calibrating senseamp is introduced to cancel offset by exploiting the statistical balance of spread-spectrum tactile pulses and noise. The 40nm testchip shows 1.6-fJ/convstep energy (0.0075mm2 area) per receptor with 50X (5X) improvement over prior art, and 80-receptor e-skin aggregation on a single pad.
{"title":"Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density","authors":"Prachi Agarwal, V. Rajanna, Toh Wei Da, Benjamin C. K. Tee, M. Alioto","doi":"10.23919/VLSICircuits52068.2021.9492329","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492329","url":null,"abstract":"This work presents an area- and energy-efficient decoder for tactile e-skin sensing encoding to scale up receptor density to the human scale. A fully-digital signal-adaptive receptor interface and event decoder architecture are introduced, leveraging temporal/spatial tactile signal sparsity to dynamically reduce activity and time resolution at negligible accuracy degradation. A novel reference-less self-calibrating senseamp is introduced to cancel offset by exploiting the statistical balance of spread-spectrum tactile pulses and noise. The 40nm testchip shows 1.6-fJ/convstep energy (0.0075mm2 area) per receptor with 50X (5X) improvement over prior art, and 80-receptor e-skin aggregation on a single pad.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132620067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492489
C. J. Wu, S. Hsiao, J. Wang, W. H. Lin, C. W. Chang, T. Shao, C. Tung, Doug C. H. Yu
A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.
{"title":"Ultra High Power Cooling Solution for 3D-ICs","authors":"C. J. Wu, S. Hsiao, J. Wang, W. H. Lin, C. W. Chang, T. Shao, C. Tung, Doug C. H. Yu","doi":"10.23919/VLSICircuits52068.2021.9492489","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492489","url":null,"abstract":"A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492455
H. Prabhu, Liang Liu, F. Sheikh, O. Edfors
A 2.2 mm2 full digital baseband SoC with four heterogeneous cores for 128-node 8-users distributed massive MIMO is presented. Two specialized DSPs perform rapid over-the-air synchronization within 0.1ms. A highly optimized 8-complex lane MIMO vector processor provides 4x hardware efficiency improvement over general-purpose processors. Circuit optimizations and the use of body-bias result in 1070 pJ/b measured energy at 169 Mb/s detection rate.
{"title":"A 1070 pJ/b 169 Mb/s Quad-core Digital Baseband SoC for Distributed and Cooperative Massive MIMO in 28 nm FD-SOI","authors":"H. Prabhu, Liang Liu, F. Sheikh, O. Edfors","doi":"10.23919/VLSICircuits52068.2021.9492455","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492455","url":null,"abstract":"A 2.2 mm2 full digital baseband SoC with four heterogeneous cores for 128-node 8-users distributed massive MIMO is presented. Two specialized DSPs perform rapid over-the-air synchronization within 0.1ms. A highly optimized 8-complex lane MIMO vector processor provides 4x hardware efficiency improvement over general-purpose processors. Circuit optimizations and the use of body-bias result in 1070 pJ/b measured energy at 169 Mb/s detection rate.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115139839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492436
Minglei Zhang, Yan Zhu, Chi-Hang Chan, R. Martins
This paper demonstrates a background timing skew calibration for the time-interleaved (TI) ADCs using a direct time-based estimation to facilitate the input-independent and fast convergence features. It suppresses the timing spurs of a 20GS/s 8× TI-ADC below ‒50dB at a Nyquist input regardless of the calibrating input condition with 24 calibration cycles. The 8b time-domain TI-ADC achieves a 91.3fJ/conv.-step FoMWalden and >16GHz bandwidth.
{"title":"A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration","authors":"Minglei Zhang, Yan Zhu, Chi-Hang Chan, R. Martins","doi":"10.23919/VLSICircuits52068.2021.9492436","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492436","url":null,"abstract":"This paper demonstrates a background timing skew calibration for the time-interleaved (TI) ADCs using a direct time-based estimation to facilitate the input-independent and fast convergence features. It suppresses the timing spurs of a 20GS/s 8× TI-ADC below ‒50dB at a Nyquist input regardless of the calibrating input condition with 24 calibration cycles. The 8b time-domain TI-ADC achieves a 91.3fJ/conv.-step FoMWalden and >16GHz bandwidth.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492400
M. Papermaster, S. Kosonocky, G. Loh, S. Naffziger
The worldwide computing market grew tremendously over the past decades, and looking toward the future, these trends do not appear to be slowing down. Moore’s Law coupled with incredible innovation in hardware and software are engines driving this growth. However, the entire industry faces a barrage of challenges including the slowing of Moore’s Law, stringent power and energy constraints, an always-connected society, and disruptions from the on-going artificial intelligence revolution. To continue delivering ever higher-performance computing solutions amid these difficulties, the industry needs to pivot to a new mindset of "Tailored Computing." The need for and opportunities to tailor our technologies in all aspects of future compute will propel the industry toward heterogeneity in everything it does.
{"title":"A New Era of Tailored Computing","authors":"M. Papermaster, S. Kosonocky, G. Loh, S. Naffziger","doi":"10.23919/VLSICircuits52068.2021.9492400","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492400","url":null,"abstract":"The worldwide computing market grew tremendously over the past decades, and looking toward the future, these trends do not appear to be slowing down. Moore’s Law coupled with incredible innovation in hardware and software are engines driving this growth. However, the entire industry faces a barrage of challenges including the slowing of Moore’s Law, stringent power and energy constraints, an always-connected society, and disruptions from the on-going artificial intelligence revolution. To continue delivering ever higher-performance computing solutions amid these difficulties, the industry needs to pivot to a new mindset of \"Tailored Computing.\" The need for and opportunities to tailor our technologies in all aspects of future compute will propel the industry toward heterogeneity in everything it does.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492343
K. Kang, Byungjun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Y. Chong, J. Sim
This work presents a qubit controller IC based on the direct synthesis. The IC consists of six independently-working pulse modulators utilizing the same LO frequency. We propose a sinusoid-shaping nonlinear DAC followed by a linear interpolating DAC to improve both of energy and hardware efficiencies. The implemented IC in 40nm CMOS is verified by superconducting qubit operations with Rabi and Ramsey oscillations while consuming power of < 1/60 compared with the previous state-of-the-art.
{"title":"A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers","authors":"K. Kang, Byungjun Kim, Gahyun Choi, Sun-Kyung Lee, Jisoo Choi, Jaeho Lee, Seokhyeong Kang, Moonjoo Lee, Ho-Jin Song, Y. Chong, J. Sim","doi":"10.23919/VLSICircuits52068.2021.9492343","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492343","url":null,"abstract":"This work presents a qubit controller IC based on the direct synthesis. The IC consists of six independently-working pulse modulators utilizing the same LO frequency. We propose a sinusoid-shaping nonlinear DAC followed by a linear interpolating DAC to improve both of energy and hardware efficiencies. The implemented IC in 40nm CMOS is verified by superconducting qubit operations with Rabi and Ramsey oscillations while consuming power of < 1/60 compared with the previous state-of-the-art.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492403
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.
{"title":"PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference","authors":"Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soon-Chan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo","doi":"10.23919/VLSICircuits52068.2021.9492403","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492403","url":null,"abstract":"We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"17 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113970775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492332
Taeyoung Chung, Sooa Kim, Jehyung Yoon, Hee-Min Han, K. Park, Hokyu Lee, Ho-Young Yoon, Sun-Kyu Lee, Jongyoon Lim, Yongjin Kwon, Jungbong Lee, Sung-Ung Kwak
The on-board voltage regulator in the DDR5 memory module is required to resiliently supply current at large load transient events and alleviate output noise at the same time. We present an adaptive on-time (AOT) buck regulator with a turbo dual-phase interleaving logic for stable regulation and on-time control with dithered pseudo-constant switching frequency to suppress output harmonics by 6dB. The voltage regulator delivers up to 10A with a peak efficiency of 92.5% and covers 10A/μs steep load transients.
{"title":"A 10A/μs Fast Transient AOT Voltage Regulator on DDR5 DIMM with Dithered Pseudo-Constant Switching Frequency Achieving -6dB Harmonic Suppression","authors":"Taeyoung Chung, Sooa Kim, Jehyung Yoon, Hee-Min Han, K. Park, Hokyu Lee, Ho-Young Yoon, Sun-Kyu Lee, Jongyoon Lim, Yongjin Kwon, Jungbong Lee, Sung-Ung Kwak","doi":"10.23919/VLSICircuits52068.2021.9492332","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492332","url":null,"abstract":"The on-board voltage regulator in the DDR5 memory module is required to resiliently supply current at large load transient events and alleviate output noise at the same time. We present an adaptive on-time (AOT) buck regulator with a turbo dual-phase interleaving logic for stable regulation and on-time control with dithered pseudo-constant switching frequency to suppress output harmonics by 6dB. The voltage regulator delivers up to 10A with a peak efficiency of 92.5% and covers 10A/μs steep load transients.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126219964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492412
P. Zarkos, S. Buchbinder, C. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, J. Whinnery, Pavan Bhargava, V. Stojanović
This paper presents the first fully integrated 2-D array of electronic-photonic ultrasound sensors targeting low-power miniaturized ultrasound probes for endoscopic applications. Fabricated in a zero-change 45nm CMOS-SOI technology this Electronic-Photonic System on Chip (EPSoC), utilizes micro-ring resonators (MRRs) as ultrasound sensors instead of the traditional piezoelectric or capacitive micromachined transducers (PMUTs or CMUTs). The photonic nature of the sensor enables remoting the power-hungry receive electronics outside the probe tip, lowering the power dissipation inside the human body, eliminates the electrical cabling and reduces fiber count by 4x using wavelength division multiplexed (WDM) MRR sensors coupled onto the same waveguide. The photonic sensing element demonstrates >30 MHz bandwidth, and 7.3 mV/kPa sensitivity, while consuming 0.43 mW of power.
{"title":"Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process","authors":"P. Zarkos, S. Buchbinder, C. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, J. Whinnery, Pavan Bhargava, V. Stojanović","doi":"10.23919/VLSICircuits52068.2021.9492412","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492412","url":null,"abstract":"This paper presents the first fully integrated 2-D array of electronic-photonic ultrasound sensors targeting low-power miniaturized ultrasound probes for endoscopic applications. Fabricated in a zero-change 45nm CMOS-SOI technology this Electronic-Photonic System on Chip (EPSoC), utilizes micro-ring resonators (MRRs) as ultrasound sensors instead of the traditional piezoelectric or capacitive micromachined transducers (PMUTs or CMUTs). The photonic nature of the sensor enables remoting the power-hungry receive electronics outside the probe tip, lowering the power dissipation inside the human body, eliminates the electrical cabling and reduces fiber count by 4x using wavelength division multiplexed (WDM) MRR sensors coupled onto the same waveguide. The photonic sensing element demonstrates >30 MHz bandwidth, and 7.3 mV/kPa sensitivity, while consuming 0.43 mW of power.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131438542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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