Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492512
E. Martens, D. Dermit, M. Shrivas, Shun Nagata, J. Craninckx
We present a time-interleaved (TI) SAR ADC with 8 channels realizing 8-bit conversion at 1 GS/s each. SNDR is 45 dB at low frequency with an ERBW of 5 GHz limited by sampler distortion. Conventional SAR conversion at high speed with minimum degradation is achieved by leveraging techniques such as early quantization, minimum delay logic, DAC redundancy and gain and offset compensation via the DAC. At 8 GS/s the ADC consumes 26 mW resulting in an efficiency of 30 fJ/conv.-step.
我们提出了一个具有8个通道的时间交错(TI) SAR ADC，每个通道实现1 GS/s的8位转换。低频时SNDR为45 dB，受采样器失真限制，ERBW为5 GHz。通过利用早期量化、最小延迟逻辑、DAC冗余以及通过DAC的增益和偏移补偿等技术，实现了具有最小退化的高速传统SAR转换。在8gs /s时，ADC的功耗为26mw，效率为30fj /转换步。
{"title":"A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW","authors":"E. Martens, D. Dermit, M. Shrivas, Shun Nagata, J. Craninckx","doi":"10.23919/VLSICircuits52068.2021.9492512","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492512","url":null,"abstract":"We present a time-interleaved (TI) SAR ADC with 8 channels realizing 8-bit conversion at 1 GS/s each. SNDR is 45 dB at low frequency with an ERBW of 5 GHz limited by sampler distortion. Conventional SAR conversion at high speed with minimum degradation is achieved by leveraging techniques such as early quantization, minimum delay logic, DAC redundancy and gain and offset compensation via the DAC. At 8 GS/s the ADC consumes 26 mW resulting in an efficiency of 30 fJ/conv.-step.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129112648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492329
Prachi Agarwal, V. Rajanna, Toh Wei Da, Benjamin C. K. Tee, M. Alioto
This work presents an area- and energy-efficient decoder for tactile e-skin sensing encoding to scale up receptor density to the human scale. A fully-digital signal-adaptive receptor interface and event decoder architecture are introduced, leveraging temporal/spatial tactile signal sparsity to dynamically reduce activity and time resolution at negligible accuracy degradation. A novel reference-less self-calibrating senseamp is introduced to cancel offset by exploiting the statistical balance of spread-spectrum tactile pulses and noise. The 40nm testchip shows 1.6-fJ/convstep energy (0.0075mm2 area) per receptor with 50X (5X) improvement over prior art, and 80-receptor e-skin aggregation on a single pad.
{"title":"Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density","authors":"Prachi Agarwal, V. Rajanna, Toh Wei Da, Benjamin C. K. Tee, M. Alioto","doi":"10.23919/VLSICircuits52068.2021.9492329","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492329","url":null,"abstract":"This work presents an area- and energy-efficient decoder for tactile e-skin sensing encoding to scale up receptor density to the human scale. A fully-digital signal-adaptive receptor interface and event decoder architecture are introduced, leveraging temporal/spatial tactile signal sparsity to dynamically reduce activity and time resolution at negligible accuracy degradation. A novel reference-less self-calibrating senseamp is introduced to cancel offset by exploiting the statistical balance of spread-spectrum tactile pulses and noise. The 40nm testchip shows 1.6-fJ/convstep energy (0.0075mm2 area) per receptor with 50X (5X) improvement over prior art, and 80-receptor e-skin aggregation on a single pad.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132620067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492400
M. Papermaster, S. Kosonocky, G. Loh, S. Naffziger
The worldwide computing market grew tremendously over the past decades, and looking toward the future, these trends do not appear to be slowing down. Moore’s Law coupled with incredible innovation in hardware and software are engines driving this growth. However, the entire industry faces a barrage of challenges including the slowing of Moore’s Law, stringent power and energy constraints, an always-connected society, and disruptions from the on-going artificial intelligence revolution. To continue delivering ever higher-performance computing solutions amid these difficulties, the industry needs to pivot to a new mindset of "Tailored Computing." The need for and opportunities to tailor our technologies in all aspects of future compute will propel the industry toward heterogeneity in everything it does.
{"title":"A New Era of Tailored Computing","authors":"M. Papermaster, S. Kosonocky, G. Loh, S. Naffziger","doi":"10.23919/VLSICircuits52068.2021.9492400","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492400","url":null,"abstract":"The worldwide computing market grew tremendously over the past decades, and looking toward the future, these trends do not appear to be slowing down. Moore’s Law coupled with incredible innovation in hardware and software are engines driving this growth. However, the entire industry faces a barrage of challenges including the slowing of Moore’s Law, stringent power and energy constraints, an always-connected society, and disruptions from the on-going artificial intelligence revolution. To continue delivering ever higher-performance computing solutions amid these difficulties, the industry needs to pivot to a new mindset of \"Tailored Computing.\" The need for and opportunities to tailor our technologies in all aspects of future compute will propel the industry toward heterogeneity in everything it does.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492412
P. Zarkos, S. Buchbinder, C. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, J. Whinnery, Pavan Bhargava, V. Stojanović
This paper presents the first fully integrated 2-D array of electronic-photonic ultrasound sensors targeting low-power miniaturized ultrasound probes for endoscopic applications. Fabricated in a zero-change 45nm CMOS-SOI technology this Electronic-Photonic System on Chip (EPSoC), utilizes micro-ring resonators (MRRs) as ultrasound sensors instead of the traditional piezoelectric or capacitive micromachined transducers (PMUTs or CMUTs). The photonic nature of the sensor enables remoting the power-hungry receive electronics outside the probe tip, lowering the power dissipation inside the human body, eliminates the electrical cabling and reduces fiber count by 4x using wavelength division multiplexed (WDM) MRR sensors coupled onto the same waveguide. The photonic sensing element demonstrates >30 MHz bandwidth, and 7.3 mV/kPa sensitivity, while consuming 0.43 mW of power.
{"title":"Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Imaging Applications in a Zero-Change 45nm CMOS-SOI Process","authors":"P. Zarkos, S. Buchbinder, C. Adamopoulos, Sarika Madhvapathy, Olivia Hsu, J. Whinnery, Pavan Bhargava, V. Stojanović","doi":"10.23919/VLSICircuits52068.2021.9492412","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492412","url":null,"abstract":"This paper presents the first fully integrated 2-D array of electronic-photonic ultrasound sensors targeting low-power miniaturized ultrasound probes for endoscopic applications. Fabricated in a zero-change 45nm CMOS-SOI technology this Electronic-Photonic System on Chip (EPSoC), utilizes micro-ring resonators (MRRs) as ultrasound sensors instead of the traditional piezoelectric or capacitive micromachined transducers (PMUTs or CMUTs). The photonic nature of the sensor enables remoting the power-hungry receive electronics outside the probe tip, lowering the power dissipation inside the human body, eliminates the electrical cabling and reduces fiber count by 4x using wavelength division multiplexed (WDM) MRR sensors coupled onto the same waveguide. The photonic sensing element demonstrates >30 MHz bandwidth, and 7.3 mV/kPa sensitivity, while consuming 0.43 mW of power.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131438542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492489
C. J. Wu, S. Hsiao, J. Wang, W. H. Lin, C. W. Chang, T. Shao, C. Tung, Doug C. H. Yu
A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.
{"title":"Ultra High Power Cooling Solution for 3D-ICs","authors":"C. J. Wu, S. Hsiao, J. Wang, W. H. Lin, C. W. Chang, T. Shao, C. Tung, Doug C. H. Yu","doi":"10.23919/VLSICircuits52068.2021.9492489","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492489","url":null,"abstract":"A direct silicon water cooling solution using fusion bonded silicon lid is proposed. It is successfully demonstrated as an effective cooling solution with total power >2600 W on a single SoC, equivalent to power density of 4.8 W/mm2. Low temperature logic chip to silicon lid fusion bonding, with trench/grid cooling structure cutting into silicon lid enables minimal thermal resistance between active device and cooling water and best cooling efficiency. Direct water cooling on logic chip silicon backside has also been demonstrated with power density better than 7 W/mm2.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492361
R. Zamparette, K. Makinwa
This paper presents a ±2A fully-integrated current sensor with a 20 mΩ on-chip shunt (resistor). It employs an energy-efficient hybrid sigma-delta ADC with an FIR-DAC and consumes only 1.4 μA, a 3× improvement on the state-of-the-art. A tunable analog non-linear temperature-compensation scheme (TCS) allows ±2A currents to be digitized with 0.35% gain error from −40 to 85°C. With a 3 mΩ PCB shunt, ±15A currents can be digitized with slightly more (0.6%) gain error. In a 0.18 μm CMOS process, the sensor occupies 1.6 mm2.
{"title":"A ±2A/15A Current Sensor with 1.4 μA Supply Current and ±0.35%/0.6% Gain Error From −40 to 85°C using an Analog Temperature-Compensation Scheme","authors":"R. Zamparette, K. Makinwa","doi":"10.23919/VLSICircuits52068.2021.9492361","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492361","url":null,"abstract":"This paper presents a ±2A fully-integrated current sensor with a 20 mΩ on-chip shunt (resistor). It employs an energy-efficient hybrid sigma-delta ADC with an FIR-DAC and consumes only 1.4 μA, a 3× improvement on the state-of-the-art. A tunable analog non-linear temperature-compensation scheme (TCS) allows ±2A currents to be digitized with 0.35% gain error from −40 to 85°C. With a 3 mΩ PCB shunt, ±15A currents can be digitized with slightly more (0.6%) gain error. In a 0.18 μm CMOS process, the sensor occupies 1.6 mm2.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492474
Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, F. Yang, Kunyang Liu, H. Shinohara
A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3~1.0 V) and temperature (−20~100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).
{"title":"A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement","authors":"Ruilin Zhang, Xingyu Wang, Luying Wang, Xinpeng Chen, F. Yang, Kunyang Liu, H. Shinohara","doi":"10.23919/VLSICircuits52068.2021.9492474","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492474","url":null,"abstract":"A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3~1.0 V) and temperature (−20~100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"63 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492452
Peng Chen, Feifei Zhang, Suoping Hu, R. Staszewski
Advanced techniques focusing on ultra-low jitter and spurs in integer-N PLLs, such as subsampling, injection locking and type-I architectures, have been extensively explored in the last decade. To accommodate new communication protocols, it is more attractive to push these high performance PLLs to a fractional-N operation. One major issue related to the fractional-N PLLs are fractional spurs, especially the in-band spurs that cannot be simply filtered out by the PLL loop but which can ruin the spectral performance. Phase interpolators (PI) and digital-to-time converters (DTC) are commonly used to assist in reducing the phase detection quantization error. The linearity, range, jitter and power are the main trade-offs in these blocks’ design. A DTC with >9-b (<0.2% INL/range) linearity is favored in the fractional-N PLLs targeting <-50dBc in-band fractional spurs. This work presents techniques to minimize the nonlinearities and power in the proposed constant slope DTC. Figure 1 shows the complete schematic of the proposed design. With feedforward (FF) and feedback (FB) techniques and nonlinearity cancellation, the implemented DTC runs at 50MHz and features 543ps delay range, 0.11% INL/Range, 36uW power consumption.
{"title":"A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range","authors":"Peng Chen, Feifei Zhang, Suoping Hu, R. Staszewski","doi":"10.23919/VLSICircuits52068.2021.9492452","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492452","url":null,"abstract":"Advanced techniques focusing on ultra-low jitter and spurs in integer-N PLLs, such as subsampling, injection locking and type-I architectures, have been extensively explored in the last decade. To accommodate new communication protocols, it is more attractive to push these high performance PLLs to a fractional-N operation. One major issue related to the fractional-N PLLs are fractional spurs, especially the in-band spurs that cannot be simply filtered out by the PLL loop but which can ruin the spectral performance. Phase interpolators (PI) and digital-to-time converters (DTC) are commonly used to assist in reducing the phase detection quantization error. The linearity, range, jitter and power are the main trade-offs in these blocks’ design. A DTC with >9-b (<0.2% INL/range) linearity is favored in the fractional-N PLLs targeting <-50dBc in-band fractional spurs. This work presents techniques to minimize the nonlinearities and power in the proposed constant slope DTC. Figure 1 shows the complete schematic of the proposed design. With feedforward (FF) and feedback (FB) techniques and nonlinearity cancellation, the implemented DTC runs at 50MHz and features 543ps delay range, 0.11% INL/Range, 36uW power consumption.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"194 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132074914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-13DOI: 10.23919/VLSICircuits52068.2021.9492438
S. Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, P. Fan, Chia-En Huang, Y. Chih, Yih Wang, Jonathan Chang
A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb for in-field programming in 5nm SoC and 10 years of data retention at 125°C.
{"title":"A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing","authors":"S. Chou, Gu-Huan Li, Shawn Chen, Jun-Hao Chang, Wan-Hsueh Cheng, Shao-Ding Wu, P. Fan, Chia-En Huang, Y. Chih, Yih Wang, Jonathan Chang","doi":"10.23919/VLSICircuits52068.2021.9492438","DOIUrl":"https://doi.org/10.23919/VLSICircuits52068.2021.9492438","url":null,"abstract":"A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb for in-field programming in 5nm SoC and 10 years of data retention at 125°C.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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