Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437913
Abhiroop Bhattacharjee, Kavindra Kandpal
Charge amplifiers, characterized by their charge-sensitivity or charge gain, are essential components of a transducer-interfacing system that amplify charge signals emerging from various sensors and convert them into voltage signals. Today, with increased scaling of MOSFETs, it becomes challenging to obtain the charge amplifiers with high charge sensitivity and low power. Furthermore, if the charge amplifier is to be operated at lower bandwidth, then obtaining low noise at higher charge sensitivity is also difficult. In this paper, the authors propose a novel design of a charge-sensitive preamplifier in 90 nm CMOS technology that can be operated at the frequency range of 10 Hz-10 kHz, suitable for biosignals at lower frequencies. The opamp in the preamplifier is designed to have a folded-cascode structure with composite cascoding at its input transistors for low power operation. A feedback resistance of 185.20 GΩ for the preamplifier is actively realized using long-channel cascode MOSFET stage in the opamp, thereby eliminating the need for a large value of passive resistance on-chip. The preamplifier has a high charge sensitivity of 8.875 mV/fC at a low power consumption of 214.32 nW with input-referred noise of 256.89 μV for the bandwidth 10 Hz-10 kHz. The preamplifier operation is verified by interfacing the model of the preamplifier with the small-signal equivalent of a SPICE model of a Silicon Nanowire Field-effect Transistor (SiNW-FET) based biosensor which was proposed for impedimetric sensing of biomolecules.
{"title":"A low power, charge-sensitive preamplifier integrated with a silicon nanowire biosensor","authors":"Abhiroop Bhattacharjee, Kavindra Kandpal","doi":"10.1109/LAEDC51812.2021.9437913","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437913","url":null,"abstract":"Charge amplifiers, characterized by their charge-sensitivity or charge gain, are essential components of a transducer-interfacing system that amplify charge signals emerging from various sensors and convert them into voltage signals. Today, with increased scaling of MOSFETs, it becomes challenging to obtain the charge amplifiers with high charge sensitivity and low power. Furthermore, if the charge amplifier is to be operated at lower bandwidth, then obtaining low noise at higher charge sensitivity is also difficult. In this paper, the authors propose a novel design of a charge-sensitive preamplifier in 90 nm CMOS technology that can be operated at the frequency range of 10 Hz-10 kHz, suitable for biosignals at lower frequencies. The opamp in the preamplifier is designed to have a folded-cascode structure with composite cascoding at its input transistors for low power operation. A feedback resistance of 185.20 GΩ for the preamplifier is actively realized using long-channel cascode MOSFET stage in the opamp, thereby eliminating the need for a large value of passive resistance on-chip. The preamplifier has a high charge sensitivity of 8.875 mV/fC at a low power consumption of 214.32 nW with input-referred noise of 256.89 μV for the bandwidth 10 Hz-10 kHz. The preamplifier operation is verified by interfacing the model of the preamplifier with the small-signal equivalent of a SPICE model of a Silicon Nanowire Field-effect Transistor (SiNW-FET) based biosensor which was proposed for impedimetric sensing of biomolecules.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437929
I. Hernández, S. I. Garduño, A. Cerdeira, B. Iñiguez, M. Estrada
In this paper we present high mobility thin film transistors, using hafnium oxide as dielectric and amorphous Hafnium-Indium-Zinc Oxide as semiconductor, both deposited by radio frequency magnetron sputtering at room temperature. Devices operated within the voltage range of 2 V, with mobility above 300 cm2/Vs and a threshold voltage in the order of 0.6 V. When the value of the effective mobility is above 150 cm2/Vs, as the gate voltage increases, its behavior presents a maximum with a further reduction. This can be interpreted as a crystalline-like behavior, although the semiconductor layer completely is amorphous.
{"title":"High Mobility Hf-In-ZnO TFTs, with HfO2 as Dielectric for Low Voltage Operation Range","authors":"I. Hernández, S. I. Garduño, A. Cerdeira, B. Iñiguez, M. Estrada","doi":"10.1109/LAEDC51812.2021.9437929","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437929","url":null,"abstract":"In this paper we present high mobility thin film transistors, using hafnium oxide as dielectric and amorphous Hafnium-Indium-Zinc Oxide as semiconductor, both deposited by radio frequency magnetron sputtering at room temperature. Devices operated within the voltage range of 2 V, with mobility above 300 cm2/Vs and a threshold voltage in the order of 0.6 V. When the value of the effective mobility is above 150 cm2/Vs, as the gate voltage increases, its behavior presents a maximum with a further reduction. This can be interpreted as a crystalline-like behavior, although the semiconductor layer completely is amorphous.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437944
G. Wirth, M. B. da Silva, T. H. Both
We discuss how charge trapping produces random telegraph noise (RTN) and low-frequency noise (1/f noise), working towards unified statistical modeling and parameter extraction. Modeling is based on discrete device physics quantities, which cause variability in the electrical behavior of MOSFETs. It allows for the derivation of analytical formulations for 1/f noise (frequency domain) and RTN (time domain) using a single modeling framework, where model parameters are the same in frequency and time domain. In this work we focus on the observation window, in time and frequency domain. We discuss how it impacts the observed variance of the threshold voltage taken over time, and the number of traps observed (active) in the time window or frequency window of interest.
{"title":"Towards Unifying the Statistical Modeling of Charge Trapping in Time and Frequency Domain","authors":"G. Wirth, M. B. da Silva, T. H. Both","doi":"10.1109/LAEDC51812.2021.9437944","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437944","url":null,"abstract":"We discuss how charge trapping produces random telegraph noise (RTN) and low-frequency noise (1/f noise), working towards unified statistical modeling and parameter extraction. Modeling is based on discrete device physics quantities, which cause variability in the electrical behavior of MOSFETs. It allows for the derivation of analytical formulations for 1/f noise (frequency domain) and RTN (time domain) using a single modeling framework, where model parameters are the same in frequency and time domain. In this work we focus on the observation window, in time and frequency domain. We discuss how it impacts the observed variance of the threshold voltage taken over time, and the number of traps observed (active) in the time window or frequency window of interest.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125777484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437914
Nagel Amaguayo, Ariana Musello, P. Lopez, L. Trojman, L. Prócel, J. Bustamante
Controlled dielectric breakdown is becoming the main solid-state nanopore fabrication technique worldwide. This paper presents the construction of a system for the fabrication of a single solid-state nanopore in a membrane using this technique. We include a basic introduction to nanopore theory. We also detail the building process of the low-cost equipment for nanopore fabrication, so that this paper can be used as a guide for building a similar system. Finally, we include the results of the creation of two nanopores and their characterization.
{"title":"Fabrication of Nanopores Using the Controlled Dielectric Breakdown Technique","authors":"Nagel Amaguayo, Ariana Musello, P. Lopez, L. Trojman, L. Prócel, J. Bustamante","doi":"10.1109/LAEDC51812.2021.9437914","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437914","url":null,"abstract":"Controlled dielectric breakdown is becoming the main solid-state nanopore fabrication technique worldwide. This paper presents the construction of a system for the fabrication of a single solid-state nanopore in a membrane using this technique. We include a basic introduction to nanopore theory. We also detail the building process of the low-cost equipment for nanopore fabrication, so that this paper can be used as a guide for building a similar system. Finally, we include the results of the creation of two nanopores and their characterization.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131734661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437865
A. Lacaita, A. Spinelli, C. M. Compagnoni
This paper covers the recent evolution of high-density solid-state storage, which is the most prominent storage solution of the 21st century. The attention is focused on the two integrated technologies that more than any other are revolutionizing the storage landscape: the NAND Flash technology and the Phase-Change Memory (PCM) technology. The success of the NAND Flash technology has been the outcome of its strenuous attempt not only to maximize the bit storage density achievable with a cost-effective process over the surface of a silicon die, but also to increase that density at a regular pace thanks to favorable evolutionary approaches. In this way, NAND Flash memories have become the elective storage media for a wide variety of electronic applications, overwhelming hard-disk drives. The PCM technology represents, instead, a notable exploitation of a new memory concept to provide a novel trade-off among cost, performance and reliability. In particular, the PCM attempt to address performance more than cost needs is driving a shift in the traditional storage hierarchy, with storage-class memory finally becoming a reality.
{"title":"High-Density Solid-State Storage: A Long Path to Success","authors":"A. Lacaita, A. Spinelli, C. M. Compagnoni","doi":"10.1109/LAEDC51812.2021.9437865","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437865","url":null,"abstract":"This paper covers the recent evolution of high-density solid-state storage, which is the most prominent storage solution of the 21st century. The attention is focused on the two integrated technologies that more than any other are revolutionizing the storage landscape: the NAND Flash technology and the Phase-Change Memory (PCM) technology. The success of the NAND Flash technology has been the outcome of its strenuous attempt not only to maximize the bit storage density achievable with a cost-effective process over the surface of a silicon die, but also to increase that density at a regular pace thanks to favorable evolutionary approaches. In this way, NAND Flash memories have become the elective storage media for a wide variety of electronic applications, overwhelming hard-disk drives. The PCM technology represents, instead, a notable exploitation of a new memory concept to provide a novel trade-off among cost, performance and reliability. In particular, the PCM attempt to address performance more than cost needs is driving a shift in the traditional storage hierarchy, with storage-class memory finally becoming a reality.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125171488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437979
J. Raskin
Performances of RF and millimeter-wave integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range.
{"title":"SOI technologies for RF and millimeter-wave integrated circuits","authors":"J. Raskin","doi":"10.1109/LAEDC51812.2021.9437979","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437979","url":null,"abstract":"Performances of RF and millimeter-wave integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127195480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437970
Ahmed Alqurashi, M. Missous
The Resonant Tunneling Diode (RTD) is one of the most promising candidates for room temperature generation of terahertz (THz) radiation. Therefore, many attempts have been reported to increase the oscillation frequency beyond 1 THz either by reducing the mesa area or by thickening the collector spacer layer. Reducing the mesa area would reduce the Negative Differential Conductance (NDC), while increasing the thickness of the collector spacer layer would lead to an increase in the peak voltage value and increasing the emitter spacer thickness would increase the oscillation frequency while maintaining low peak voltage value. This work presents the physical modelling of asymmetric spacer resonant tunneling diodes (RTDs) to increase the oscillation frequency while still maintaining a low peak voltage, high NDC, and high output power. Different thicknesses of emitter spacer layer (7.5 nm and 10 nm) are simulated with varying thicknesses of the quantum well (3.5 nm, 3nm, and 2.5 nm) to study their effects on the DC and RF characteristics of the RTDs. Increasing the Indium concentration in the quantum well region has improved the oscillation frequency while maintaining a low peak voltage.
{"title":"Physical Modeling of Asymmetric Spacers Resonant Tunneling Diodes (RTDs)","authors":"Ahmed Alqurashi, M. Missous","doi":"10.1109/LAEDC51812.2021.9437970","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437970","url":null,"abstract":"The Resonant Tunneling Diode (RTD) is one of the most promising candidates for room temperature generation of terahertz (THz) radiation. Therefore, many attempts have been reported to increase the oscillation frequency beyond 1 THz either by reducing the mesa area or by thickening the collector spacer layer. Reducing the mesa area would reduce the Negative Differential Conductance (NDC), while increasing the thickness of the collector spacer layer would lead to an increase in the peak voltage value and increasing the emitter spacer thickness would increase the oscillation frequency while maintaining low peak voltage value. This work presents the physical modelling of asymmetric spacer resonant tunneling diodes (RTDs) to increase the oscillation frequency while still maintaining a low peak voltage, high NDC, and high output power. Different thicknesses of emitter spacer layer (7.5 nm and 10 nm) are simulated with varying thicknesses of the quantum well (3.5 nm, 3nm, and 2.5 nm) to study their effects on the DC and RF characteristics of the RTDs. Increasing the Indium concentration in the quantum well region has improved the oscillation frequency while maintaining a low peak voltage.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126379755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437978
Rabia Aqeel, A. Raza, Shaheer Ahmed, Muhammad Aashquin, Haider Ali
In the present study, effect of heat sink configuration on the performance of the thermoelectric refrigerator system is studied. Heat Sink is one of the important components of the thermoelectric system, the configuration of which can directly affect the heat removal from the refrigeration system. Three different fin configurations are considered for the small-scale vaccine thermoelectric refrigerator. The mathematical modelling for thermoelectric cooler and the heat sink design is carried out to study the effect of the fin configuration, on the performance of the thermoelectric refrigerator.
{"title":"Effect of Heat Sink Configuration on the Performance of Thermoelectric Refrigeration","authors":"Rabia Aqeel, A. Raza, Shaheer Ahmed, Muhammad Aashquin, Haider Ali","doi":"10.1109/LAEDC51812.2021.9437978","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437978","url":null,"abstract":"In the present study, effect of heat sink configuration on the performance of the thermoelectric refrigerator system is studied. Heat Sink is one of the important components of the thermoelectric system, the configuration of which can directly affect the heat removal from the refrigeration system. Three different fin configurations are considered for the small-scale vaccine thermoelectric refrigerator. The mathematical modelling for thermoelectric cooler and the heat sink design is carried out to study the effect of the fin configuration, on the performance of the thermoelectric refrigerator.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130471835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437922
R. Goel, Y. Chauhan
An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the sub-circuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.
{"title":"Compact Modeling of Flicker Noise in High Voltage MOSFETs and Experimental Validation","authors":"R. Goel, Y. Chauhan","doi":"10.1109/LAEDC51812.2021.9437922","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437922","url":null,"abstract":"An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the sub-circuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the SID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437934
Yiyi Yan, D. Flandre, V. Kilchytska, S. Faniel, Xiaohui Tang, J. Raskin
This work investigates different Al2O3-based dielectric stacks for various applications, including surface passivation of solar cells and photodetectors, replacement of SiO2 gate dielectric in advanced MOSFETs. Ultra-thin Al2O3/SiO2 (3/2 nm) stacks were deposited on silicon by using different techniques. A reference sample with only a single dry-grown SiO2 layer (3 nm) was prepared for comparison purpose. The effective carrier lifetimes were measured by the contactless photoconductance decay method. The lowest surface recombination velocity was calculated to be 34 cm/s in the Al2O3/SiO2 stack. The negative fixed charge density in the stacks was extracted from C–V characteristics. Our results reveal that the effective carrier lifetimes depend on the stacks deposition techniques and conditions, and provide a guideline for optimization.
{"title":"Determination of Carrier Lifetime in Silicon Using an Ultra-thin Al2O3/SiO2 Dielectric Stack","authors":"Yiyi Yan, D. Flandre, V. Kilchytska, S. Faniel, Xiaohui Tang, J. Raskin","doi":"10.1109/LAEDC51812.2021.9437934","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437934","url":null,"abstract":"This work investigates different Al2O3-based dielectric stacks for various applications, including surface passivation of solar cells and photodetectors, replacement of SiO2 gate dielectric in advanced MOSFETs. Ultra-thin Al2O3/SiO2 (3/2 nm) stacks were deposited on silicon by using different techniques. A reference sample with only a single dry-grown SiO2 layer (3 nm) was prepared for comparison purpose. The effective carrier lifetimes were measured by the contactless photoconductance decay method. The lowest surface recombination velocity was calculated to be 34 cm/s in the Al2O3/SiO2 stack. The negative fixed charge density in the stacks was extracted from C–V characteristics. Our results reveal that the effective carrier lifetimes depend on the stacks deposition techniques and conditions, and provide a guideline for optimization.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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