Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437924
C. Ascencio-Hurtado, A. Torres, M. Moreno, R. Ambrosio
Thin films of a-SiGe:H deposited by low-frequency plasma-enhanced chemical vapor deposition (LF PECVD) at 200 °C with improved conductivity are demonstrated. After thermal annealing at 500 °C, these films showed a-SiGe even better electrical conductivity than the obtained as PECVD deposited films. The annealing process to which the films were subjected was planned to enhance their transport properties while avoiding crystallization. After characterization by means of FTIR and Raman techniques, the solid phase of the thin film remained amorphous after annealing. The room-temperature electrical conductivity increased about three orders of magnitude from 2.27E-02 up to 2.47 S/cm for the non annealed to the annealed films. Because of the electrical and structural properties measured on the a-SiGe material here obtained, it is one of the best conductivity reached for intrinsic a-SiGe reported up to now. Its high electrical conductivity makes it suitable for its potential application in emerging and environment-friendly technologies such as flexible electronics, wearable electronics, and energy harvesting.
{"title":"High conductivity intrinsic a-SiGe films deposited at low-temperature","authors":"C. Ascencio-Hurtado, A. Torres, M. Moreno, R. Ambrosio","doi":"10.1109/LAEDC51812.2021.9437924","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437924","url":null,"abstract":"Thin films of a-SiGe:H deposited by low-frequency plasma-enhanced chemical vapor deposition (LF PECVD) at 200 °C with improved conductivity are demonstrated. After thermal annealing at 500 °C, these films showed a-SiGe even better electrical conductivity than the obtained as PECVD deposited films. The annealing process to which the films were subjected was planned to enhance their transport properties while avoiding crystallization. After characterization by means of FTIR and Raman techniques, the solid phase of the thin film remained amorphous after annealing. The room-temperature electrical conductivity increased about three orders of magnitude from 2.27E-02 up to 2.47 S/cm for the non annealed to the annealed films. Because of the electrical and structural properties measured on the a-SiGe material here obtained, it is one of the best conductivity reached for intrinsic a-SiGe reported up to now. Its high electrical conductivity makes it suitable for its potential application in emerging and environment-friendly technologies such as flexible electronics, wearable electronics, and energy harvesting.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437928
Lucas Mota Barbosa da Silva, M. de Souza
This work presents a simulation strategy to simulate Graded-Channel SOI MOSFET electrical characteristics using BSIM SOI SPICE model. The use of uniformly doped transistor model is possible by adjusting low field mobility, degradation mobility factors and parameters related to channel length modulation and DIBL effects. A good agreement with experimental data was achieved at device level. The simulation strategy is validated through the simulation of common-source current mirrors using adjusted SPICE model parameters, presenting the same trends of experimental results available in the literature.
本文提出了一种利用BSIM SOI SPICE模型模拟渐变通道SOI MOSFET电特性的仿真策略。通过调整低场迁移率、退化迁移率因子以及与通道长度调制和DIBL效应相关的参数，可以实现均匀掺杂晶体管模型的使用。在器件级得到了与实验数据吻合较好的结果。采用调整后的SPICE模型参数对共源电流镜进行仿真，验证了仿真策略的有效性，得到了与文献实验结果相同的趋势。
{"title":"Strategy for Simulation of Analog Circuits with GCSOI MOSFET using BSIM SOI model","authors":"Lucas Mota Barbosa da Silva, M. de Souza","doi":"10.1109/LAEDC51812.2021.9437928","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437928","url":null,"abstract":"This work presents a simulation strategy to simulate Graded-Channel SOI MOSFET electrical characteristics using BSIM SOI SPICE model. The use of uniformly doped transistor model is possible by adjusting low field mobility, degradation mobility factors and parameters related to channel length modulation and DIBL effects. A good agreement with experimental data was achieved at device level. The simulation strategy is validated through the simulation of common-source current mirrors using adjusted SPICE model parameters, presenting the same trends of experimental results available in the literature.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129535826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437947
Kevin Ordaz Santamaria, Joel Molina Reyes
This paper will introduce some of the most critical parameters, properties, and characteristics of a cell/electrolyte/electrode interface which, along with cell ion channels, electrode/cell coupling, and the instrumentation required for integrated MEA (microelectrode arrays), could enable sensing multiple signals for the detection of action potentials in time and space. A simple and generic fabrication process for MEA development is also introduced along with several conditions that must be met in order to maximize the electrical coupling for higher signal detection. This is applied for sensing multiple action potentials that originated at the sinus node of the heart.
{"title":"2D array microelectrodes for sensing the action potential of the sinoatrial node","authors":"Kevin Ordaz Santamaria, Joel Molina Reyes","doi":"10.1109/LAEDC51812.2021.9437947","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437947","url":null,"abstract":"This paper will introduce some of the most critical parameters, properties, and characteristics of a cell/electrolyte/electrode interface which, along with cell ion channels, electrode/cell coupling, and the instrumentation required for integrated MEA (microelectrode arrays), could enable sensing multiple signals for the detection of action potentials in time and space. A simple and generic fabrication process for MEA development is also introduced along with several conditions that must be met in order to maximize the electrical coupling for higher signal detection. This is applied for sensing multiple action potentials that originated at the sinus node of the heart.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124810424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437943
D. C. García, José Enrique Eirez Izquierdo, Marco R. Cavallari, Fernando Josepetti Fonseca
Irregular housing and, consequently, the discharge of sewage in water reservoirs lead to algae proliferation. After their decomposition, they release substances that cause flavor and odor to the water. In this context, this work focused on the development of organic thin film transistors for the analysis of water supplied by the Basic Sanitation Company of the State of São Paulo (SABESP). Electrical devices with fully patterned electrodes were processed over glass substrates. Seeking higher compatibility with flexible substrates, cross-linked poly(4-vinylphenol), a high dielectric constant material, was used. It was demonstrated that only the cross-linked polymer could withstand both electrode photolithography and semiconductor deposition. Subsequently, the performance of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) in gas sensors was investigated. Results obtained in triode regime showed high sensitivity to isoborneol. A current variation greater than 20% in response to 10 ppm of isoborneol represents an important step in the development of a low-cost electronic nose for real-time water quality monitoring.
{"title":"Cross-linked poly(4-vinylphenol) in thin-film transistors for water analysis","authors":"D. C. García, José Enrique Eirez Izquierdo, Marco R. Cavallari, Fernando Josepetti Fonseca","doi":"10.1109/LAEDC51812.2021.9437943","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437943","url":null,"abstract":"Irregular housing and, consequently, the discharge of sewage in water reservoirs lead to algae proliferation. After their decomposition, they release substances that cause flavor and odor to the water. In this context, this work focused on the development of organic thin film transistors for the analysis of water supplied by the Basic Sanitation Company of the State of São Paulo (SABESP). Electrical devices with fully patterned electrodes were processed over glass substrates. Seeking higher compatibility with flexible substrates, cross-linked poly(4-vinylphenol), a high dielectric constant material, was used. It was demonstrated that only the cross-linked polymer could withstand both electrode photolithography and semiconductor deposition. Subsequently, the performance of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) in gas sensors was investigated. Results obtained in triode regime showed high sensitivity to isoborneol. A current variation greater than 20% in response to 10 ppm of isoborneol represents an important step in the development of a low-cost electronic nose for real-time water quality monitoring.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127438055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437976
E. Moustafa, J. G, L. Marsal, J. Pallarès
In this research work, inverted organic solar cells (iOSCs) with the structure of ITO/ZnO /PTB7-Th: PC70BM/V2O5/Ag were investigated. Remarkable progress was achieved to fabricate efficient iOSCs using simple and low-cost spray pyrolysis (SP) technique to deposit a thin layer of ZnO as an Electron transporting layer (ETL). In addition, stability studies were performed for the fabricated devices. The stability study showed that the fabricated devices were possessed a low rate of degradation over time. Where the devices maintain 80 % of their initial efficiency over 5000 h. the key gain in this research was in combining the advantages of high stability along with high cell performance in addition to using mass production spray pyrolysis technique that might be a promising step for the commercialization of inverted organic solar cell.
{"title":"ZnO Thin Film Deposited by Spray Pyrolysis for Long-Term Stable Organic Solar Cells","authors":"E. Moustafa, J. G, L. Marsal, J. Pallarès","doi":"10.1109/LAEDC51812.2021.9437976","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437976","url":null,"abstract":"In this research work, inverted organic solar cells (iOSCs) with the structure of ITO/ZnO /PTB7-Th: PC70BM/V2O5/Ag were investigated. Remarkable progress was achieved to fabricate efficient iOSCs using simple and low-cost spray pyrolysis (SP) technique to deposit a thin layer of ZnO as an Electron transporting layer (ETL). In addition, stability studies were performed for the fabricated devices. The stability study showed that the fabricated devices were possessed a low rate of degradation over time. Where the devices maintain 80 % of their initial efficiency over 5000 h. the key gain in this research was in combining the advantages of high stability along with high cell performance in addition to using mass production spray pyrolysis technique that might be a promising step for the commercialization of inverted organic solar cell.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132445701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437941
A. Kloes
Today, for electrical simulation on different levels of abstraction there are mainly two simulation frameworks: TCAD enables the simulation of individual devices closely to device physics, possibly including quantum effects. Circuit simulators such as SPICE use compact models to represent individual devices in the simulation of a circuit with numerous transistors. For the very time consuming interaction of both environments in the sense of Design-Technology Co-Optimization (DTCO), compact models are used as one-way bridges: The parameters of a compact model are adapted to TCAD results and serve as input to a circuit simulation, followed by a feedback of circuit performance on the definition of the device structure. But can compact models serve as a bidirectional bridge between circuit and TCAD simulation? Is it possible and advantageous to integrate compact models in TCAD simulations to build a joined platform that enables a multiscale simulation from quantum physics to circuit simulation? In this paper, an example for the successful integration of a compact model into the numerical device simulation of an ultra-short channel double-gate MOSFET is discussed.
{"title":"Multiscale Simulation: Can Compact Models be More Than a One-Way Bridge Between TCAD and Circuit Simulation?","authors":"A. Kloes","doi":"10.1109/LAEDC51812.2021.9437941","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437941","url":null,"abstract":"Today, for electrical simulation on different levels of abstraction there are mainly two simulation frameworks: TCAD enables the simulation of individual devices closely to device physics, possibly including quantum effects. Circuit simulators such as SPICE use compact models to represent individual devices in the simulation of a circuit with numerous transistors. For the very time consuming interaction of both environments in the sense of Design-Technology Co-Optimization (DTCO), compact models are used as one-way bridges: The parameters of a compact model are adapted to TCAD results and serve as input to a circuit simulation, followed by a feedback of circuit performance on the definition of the device structure. But can compact models serve as a bidirectional bridge between circuit and TCAD simulation? Is it possible and advantageous to integrate compact models in TCAD simulations to build a joined platform that enables a multiscale simulation from quantum physics to circuit simulation? In this paper, an example for the successful integration of a compact model into the numerical device simulation of an ultra-short channel double-gate MOSFET is discussed.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123876522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437920
M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martín-Martínez, E. Roca, R. Castro-López, R. Rodríguez, P. Martín-Lloret, A. Toro-Frías, D. Mateo, E. Barajas, X. Aragonès, F. Fernández
The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.
{"title":"Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock","authors":"M. Nafria, J. Diaz-Fortuny, P. Saraza-Canflanca, J. Martín-Martínez, E. Roca, R. Castro-López, R. Rodríguez, P. Martín-Lloret, A. Toro-Frías, D. Mateo, E. Barajas, X. Aragonès, F. Fernández","doi":"10.1109/LAEDC51812.2021.9437920","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437920","url":null,"abstract":"The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126586876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437927
Mooli Shashank Reddy, Tejendra Dixit, K. P. Pradhan
The rapid increase in interest on Negative capacitance Field Effect Transistors(NCFETs) is due to its Low power applications. NCFETs stepsup the voltage between the oxide and ferroelectric capacitance due to reversing (i.e, amplification) effect of a ferroelectric (fe) layer[1]. These are designed in a way such that its Subthreshold swing overcomes the boltzmann limit. According to the Boltzmann theorem, carriers that can cross the barrier and increase current by a decade need a gate voltage increase of at least 60 mV[2]. This paper presents a new approach for designing NCFETS, where the target is a low subthreshold swing. The proposed model is validated against several experimental data for an double-gate FET architecture.
{"title":"Steep Subthreshold Swing in Double Gate NCFET:A Simulation Study","authors":"Mooli Shashank Reddy, Tejendra Dixit, K. P. Pradhan","doi":"10.1109/LAEDC51812.2021.9437927","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437927","url":null,"abstract":"The rapid increase in interest on Negative capacitance Field Effect Transistors(NCFETs) is due to its Low power applications. NCFETs stepsup the voltage between the oxide and ferroelectric capacitance due to reversing (i.e, amplification) effect of a ferroelectric (fe) layer[1]. These are designed in a way such that its Subthreshold swing overcomes the boltzmann limit. According to the Boltzmann theorem, carriers that can cross the barrier and increase current by a decade need a gate voltage increase of at least 60 mV[2]. This paper presents a new approach for designing NCFETS, where the target is a low subthreshold swing. The proposed model is validated against several experimental data for an double-gate FET architecture.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121894786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437945
A. Raol, Tom Jiao, Chandana Shashidhara, H. Wong
In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, εox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (εox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high VD, the NC effect disappears earlier than low VD.
{"title":"Fully-Coupled Simulation of the Temperature Effect on Negative Capacitance Ferroelectric Devices","authors":"A. Raol, Tom Jiao, Chandana Shashidhara, H. Wong","doi":"10.1109/LAEDC51812.2021.9437945","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437945","url":null,"abstract":"In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, εox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (εox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high VD, the NC effect disappears earlier than low VD.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123485834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437968
S. Salas-Rodríguez, J. Martínez-Castillo, F. López-Huerta, J. Molina-Reyes
This paper presents a review of the most recent and relevant works about ion sensitive systems based on Thin Film Transistors (TFTs) fabricated on flexible substrates at low temperatures. Currently, supervising ion concentrations in biological solutions such as body fluids is of great importance to evaluate the health condition of the human body in order to diagnostic diseases. Flexible and wearable ion sensors allow monitoring chemical status of an individual in real time and in a no-invasive way. Nowadays, TFTs are strong candidates to be employed for design of such applications, either in electrolytic gate or extended gate configuration, because of its fabrication process is relatively easy on flexible substrates at low temperatures, low cost and they can incorporate biocompatible sensing materials.
{"title":"Recent advances of Ion Sensing based on Flexible Low Temperature Thin Film Transistors","authors":"S. Salas-Rodríguez, J. Martínez-Castillo, F. López-Huerta, J. Molina-Reyes","doi":"10.1109/LAEDC51812.2021.9437968","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437968","url":null,"abstract":"This paper presents a review of the most recent and relevant works about ion sensitive systems based on Thin Film Transistors (TFTs) fabricated on flexible substrates at low temperatures. Currently, supervising ion concentrations in biological solutions such as body fluids is of great importance to evaluate the health condition of the human body in order to diagnostic diseases. Flexible and wearable ion sensors allow monitoring chemical status of an individual in real time and in a no-invasive way. Nowadays, TFTs are strong candidates to be employed for design of such applications, either in electrolytic gate or extended gate configuration, because of its fabrication process is relatively easy on flexible substrates at low temperatures, low cost and they can incorporate biocompatible sensing materials.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132334402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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