Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437918
F. Schwierz, M. Ziegler
The present paper guides the reader through six decades of research on 2D materials. It is shown that after a slow start and only little activity over many years, since 2004 the exploration of 2D materials advanced at an enormous pace. Our discussion focuses on the use of 2D materials for electronics and indicates that part of them are attractive for electronic devices. While some of the high expectations raised in what we call the golden era of graphene did not fulfil, certain electronic applications for 2D materials that originally were not on the agenda gain increasing attention now. Examples are stacked-channel 2D nanosheet transistors and 2D memristive devices.
{"title":"Six Decades of Research on 2D Materials: Progress, Dead Ends, and New Horizons","authors":"F. Schwierz, M. Ziegler","doi":"10.1109/LAEDC51812.2021.9437918","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437918","url":null,"abstract":"The present paper guides the reader through six decades of research on 2D materials. It is shown that after a slow start and only little activity over many years, since 2004 the exploration of 2D materials advanced at an enormous pace. Our discussion focuses on the use of 2D materials for electronics and indicates that part of them are attractive for electronic devices. While some of the high expectations raised in what we call the golden era of graphene did not fulfil, certain electronic applications for 2D materials that originally were not on the agenda gain increasing attention now. Examples are stacked-channel 2D nanosheet transistors and 2D memristive devices.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130251291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437940
M. K., M. J. Reddy, K. P. Pradhan, Tejendra Dixit
Herein, we report the effect of parametric variations on the plasmonic behavior of the transition metals i.e. Pd, Rh, Cr. UV plasmonics is critical for many applications like bio-molecule detection, surface-enhanced spectroscopies, photothermal therapies, photonic integrated circuits, etc especially in the UV region. Noble metals like Au, Ag, Pt are restricted to the visible region. Only there are very limited candidates for UV plasmonics viz. Al, Pt, etc. In order to explore prominent candidates for the UV region, the plasmonic properties of transition metals like Cr, Rh and Pd have been systematically studied. Rh has been found as a strong contender in the deep UV region. Particle size variation studies suggested that selectivity can be introduced in metals like Rh and Pd. This work will provide new insights in the development of UV plasmonics.
{"title":"Development of Multi-physics Modeling of Plasmonics in the UV Region Using Transition Metals","authors":"M. K., M. J. Reddy, K. P. Pradhan, Tejendra Dixit","doi":"10.1109/LAEDC51812.2021.9437940","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437940","url":null,"abstract":"Herein, we report the effect of parametric variations on the plasmonic behavior of the transition metals i.e. Pd, Rh, Cr. UV plasmonics is critical for many applications like bio-molecule detection, surface-enhanced spectroscopies, photothermal therapies, photonic integrated circuits, etc especially in the UV region. Noble metals like Au, Ag, Pt are restricted to the visible region. Only there are very limited candidates for UV plasmonics viz. Al, Pt, etc. In order to explore prominent candidates for the UV region, the plasmonic properties of transition metals like Cr, Rh and Pd have been systematically studied. Rh has been found as a strong contender in the deep UV region. Particle size variation studies suggested that selectivity can be introduced in metals like Rh and Pd. This work will provide new insights in the development of UV plasmonics.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131359033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437925
E. Gutiérrez-D.
Several materials used for the fabrication of semiconductor devices possess electrical, chemical, mechanical, magnetic, thermal, and physical properties in general that can be used for applications far beyond regular electron devices. In this work I introduce various materials and devices that are used as medical, agricultural, or environmental instrumentation that serves the purpose of helping humanity. This is the case of pH sensors for water quality and food production applications, or atomic-size thin layers and plasmonic devices for COVID-19 and biological applications.
{"title":"Semiconductor materials and devices for medical and environmental applications","authors":"E. Gutiérrez-D.","doi":"10.1109/LAEDC51812.2021.9437925","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437925","url":null,"abstract":"Several materials used for the fabrication of semiconductor devices possess electrical, chemical, mechanical, magnetic, thermal, and physical properties in general that can be used for applications far beyond regular electron devices. In this work I introduce various materials and devices that are used as medical, agricultural, or environmental instrumentation that serves the purpose of helping humanity. This is the case of pH sensors for water quality and food production applications, or atomic-size thin layers and plasmonic devices for COVID-19 and biological applications.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437921
P. Pandey, H. Kaur
In the present work, a detailed study has been carried out to examine the impact of fixed trap charges (FTC) on Polarity Controllable–Ferroelectric–Field Effect Transistor (PC-FE-FET). The device performance has been explored exhaustively and various characteristics such as potential, gain, total gate capacitance, subthreshold swing, threshold voltage and drain induced barrier lowering have been studied for both fresh and damaged devices. Due to presence of ferroelectric layer, the proposed device shows superior device performance over conventional device for both n- and p- operational modes. It has been demonstrated that n- mode device with negative trap charges (NTC) and p- mode device with positive trap charges (PTC) exhibits excellent steep subthreshold characteristics in comparison to fresh device in the presence of trap charges thereby implying that the proposed PC-FE-FET exhibits better performance and offers more reliability towards FTC in comparison to conventional device.
{"title":"Improved Device Performance of Polarity Controllable–Ferroelectric–Field Effect Transistor Under the Influence of Fixed Trap Charges","authors":"P. Pandey, H. Kaur","doi":"10.1109/LAEDC51812.2021.9437921","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437921","url":null,"abstract":"In the present work, a detailed study has been carried out to examine the impact of fixed trap charges (FTC) on Polarity Controllable–Ferroelectric–Field Effect Transistor (PC-FE-FET). The device performance has been explored exhaustively and various characteristics such as potential, gain, total gate capacitance, subthreshold swing, threshold voltage and drain induced barrier lowering have been studied for both fresh and damaged devices. Due to presence of ferroelectric layer, the proposed device shows superior device performance over conventional device for both n- and p- operational modes. It has been demonstrated that n- mode device with negative trap charges (NTC) and p- mode device with positive trap charges (PTC) exhibits excellent steep subthreshold characteristics in comparison to fresh device in the presence of trap charges thereby implying that the proposed PC-FE-FET exhibits better performance and offers more reliability towards FTC in comparison to conventional device.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116900972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437955
M. Vanbrabant, L. Nyssens, V. Kilchytska, J. Raskin
In this work, the compact model for FD SOI transistors and its limitations are assessed by comparing Spectre simulations to experimental measurements in a wide range of frequencies. The impact of two phenomena, namely self-heating (SH) and substrate effect (SE), on the frequency response of output conductance and capacitance and their respective modelling are studied. This work shows that the present version of compact model is not sufficient to accurately model the experimentally observed transitions in the output conductance and capacitance frequency response related to these two phenomena.
{"title":"Assessment of RF compact modelling of FD SOI transistors","authors":"M. Vanbrabant, L. Nyssens, V. Kilchytska, J. Raskin","doi":"10.1109/LAEDC51812.2021.9437955","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437955","url":null,"abstract":"In this work, the compact model for FD SOI transistors and its limitations are assessed by comparing Spectre simulations to experimental measurements in a wide range of frequencies. The impact of two phenomena, namely self-heating (SH) and substrate effect (SE), on the frequency response of output conductance and capacitance and their respective modelling are studied. This work shows that the present version of compact model is not sufficient to accurately model the experimentally observed transitions in the output conductance and capacitance frequency response related to these two phenomena.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127477863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437931
M. Ramírez-Como, A. Sacramento, José G. Sánchez, M. Estrada, V. S. Balderrama, L. Marsal
In this study, we report the use of poly [(9,9-bis (30- (N,N-dimethylamino) propyl) -2,7-fluorene) -alt-2,7- (9,9-dioctylfluorene) (PFN) as hole blocking layer (HBL) in inverted small-molecule solar cells (SM-iOSCs) using a bulk heterojunction of p-DTS(FBTTh2)2 as donor material and PC70BM as acceptor material. The behavior of these devices is compared to those SM-iOSCs where the HBL was zinc oxide (ZnO). Under 1 sun illumination, devices exhibited a power conversion efficiency (PCE) of 6.75%. It is demonstrated, through analysis of the external quantum efficiency (EQE), abortion UV-vis and atomic force microscopy of the active layer, that charge transport is the limiting factor in the performance of the cells, directly affecting the short circuit current (JSC).
{"title":"Impact of Hole Blocking Layer on the Performance of Solution-Processed Small Molecule Solar Cells","authors":"M. Ramírez-Como, A. Sacramento, José G. Sánchez, M. Estrada, V. S. Balderrama, L. Marsal","doi":"10.1109/LAEDC51812.2021.9437931","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437931","url":null,"abstract":"In this study, we report the use of poly [(9,9-bis (30- (N,N-dimethylamino) propyl) -2,7-fluorene) -alt-2,7- (9,9-dioctylfluorene) (PFN) as hole blocking layer (HBL) in inverted small-molecule solar cells (SM-iOSCs) using a bulk heterojunction of p-DTS(FBTTh2)2 as donor material and PC70BM as acceptor material. The behavior of these devices is compared to those SM-iOSCs where the HBL was zinc oxide (ZnO). Under 1 sun illumination, devices exhibited a power conversion efficiency (PCE) of 6.75%. It is demonstrated, through analysis of the external quantum efficiency (EQE), abortion UV-vis and atomic force microscopy of the active layer, that charge transport is the limiting factor in the performance of the cells, directly affecting the short circuit current (JSC).","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126198788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437935
Carlos H. S. Coelho, J. Martino, E. Simoen, A. Veloso, P. Agopian
This paper shows an experimental analysis of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around nanosheet pMOS devices (GAA-NS) for different channel lengths (L), in linear and saturation regions. The gate voltage at ZTC point (VZTC) experimental results are compared with the values obtained by analytical model (CM-ZTC model) in order to evaluate the behavior of the ZTC of the GAA-NS pMOS transistors. The comparison between the data from the CM-ZTC model and the experimental values resulted a difference smaller than 7% when operating in linear region, which means that the behavior of GAA-NS in ZTC point can be well described through the mobility degradation and threshold voltage shift basic models like in planar fully depleted SOI devices. However, in saturation region the difference increases substantially due to the high series resistance, and in case of 28 nm channel devices, due to the short-channel effect (SCE), which is not considered in the analytical model. But the experimental VZTC in saturation region does not change too much (|VZTZ| ≅ 0.75V with standard deviation ≅ 0.06V) for all studied devices (from 200 nm down to 28 nm channel lengths) which means that the GAA-NS is a trusted device for analog circuits biased at ZTC point.
{"title":"Analysis of the ZTC-Point for Vertically Stacked Nanosheet pMOS Devices","authors":"Carlos H. S. Coelho, J. Martino, E. Simoen, A. Veloso, P. Agopian","doi":"10.1109/LAEDC51812.2021.9437935","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437935","url":null,"abstract":"This paper shows an experimental analysis of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around nanosheet pMOS devices (GAA-NS) for different channel lengths (L), in linear and saturation regions. The gate voltage at ZTC point (VZTC) experimental results are compared with the values obtained by analytical model (CM-ZTC model) in order to evaluate the behavior of the ZTC of the GAA-NS pMOS transistors. The comparison between the data from the CM-ZTC model and the experimental values resulted a difference smaller than 7% when operating in linear region, which means that the behavior of GAA-NS in ZTC point can be well described through the mobility degradation and threshold voltage shift basic models like in planar fully depleted SOI devices. However, in saturation region the difference increases substantially due to the high series resistance, and in case of 28 nm channel devices, due to the short-channel effect (SCE), which is not considered in the analytical model. But the experimental VZTC in saturation region does not change too much (|VZTZ| ≅ 0.75V with standard deviation ≅ 0.06V) for all studied devices (from 200 nm down to 28 nm channel lengths) which means that the GAA-NS is a trusted device for analog circuits biased at ZTC point.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437916
Viswanath G. Akkili, R. Thangavel, V. Srivastava
Among the other p-type oxide materials, Tin Monoxide (SnO) is of much attention due to higher hole mobility and ambipolar characteristics. In Thin Film Transistors (TFTs), the channel defects and dielectric material play an important role in the device’s electrical performance. Still, the influence of SnO defects on the TFT performance is poorly understood. This paper analyses the influence of defects in the semiconductor layer and various dielectrics’ impact on the electrical characteristics of the p-channel TFTs using the 2D numerical simulator. Improved numerical simulation of SnO TFT using SiO2, HfO2, and Al2O3 dielectrics have been performed and compared their effect on transfer and output characteristics.
{"title":"Influence of Dielectrics and Channel Defects on the Electrical Performance of Oxide-based p-Channel TFTs for CMOS Applications","authors":"Viswanath G. Akkili, R. Thangavel, V. Srivastava","doi":"10.1109/LAEDC51812.2021.9437916","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437916","url":null,"abstract":"Among the other p-type oxide materials, Tin Monoxide (SnO) is of much attention due to higher hole mobility and ambipolar characteristics. In Thin Film Transistors (TFTs), the channel defects and dielectric material play an important role in the device’s electrical performance. Still, the influence of SnO defects on the TFT performance is poorly understood. This paper analyses the influence of defects in the semiconductor layer and various dielectrics’ impact on the electrical characteristics of the p-channel TFTs using the 2D numerical simulator. Improved numerical simulation of SnO TFT using SiO2, HfO2, and Al2O3 dielectrics have been performed and compared their effect on transfer and output characteristics.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133549281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437923
F. Bergamaschi, M. Pavanello
In this work, the effects of substrate biasing on the electrical behavior of n-type Ω-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width are analyzed. The analysis is carried over through 3D TCAD simulations calibrated with experimental data. Mobility degradation is observed for negative back bias due to surface-related scattering mechanisms on the front gate channel, while mobility increase is verified for positive back bias values that induce conduction in both front and back channels. High back bias values, however, which activate the back channel prior to the front one, lead to degradation in carrier mobility. On-state-off-state current ratio reduces for positive back bias due to degradation in the subthreshold slope, while DIBL is worsened due to the reduced front gate control when the substrate’s positive electric field takes ahold of the inversion charges.
{"title":"TCAD Evaluation of the Substrate Bias Influence on the Carrier Transport of Ω-Gate Nanowire MOS Transistors with Ultra-Thin BOX","authors":"F. Bergamaschi, M. Pavanello","doi":"10.1109/LAEDC51812.2021.9437923","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437923","url":null,"abstract":"In this work, the effects of substrate biasing on the electrical behavior of n-type Ω-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width are analyzed. The analysis is carried over through 3D TCAD simulations calibrated with experimental data. Mobility degradation is observed for negative back bias due to surface-related scattering mechanisms on the front gate channel, while mobility increase is verified for positive back bias values that induce conduction in both front and back channels. High back bias values, however, which activate the back channel prior to the front one, lead to degradation in carrier mobility. On-state-off-state current ratio reduces for positive back bias due to degradation in the subthreshold slope, while DIBL is worsened due to the reduced front gate control when the substrate’s positive electric field takes ahold of the inversion charges.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130991771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-19DOI: 10.1109/LAEDC51812.2021.9437948
S. Nayak, S. Lodha, S. Ganguly
Lateral double diffused MOSFET (LDMOSFET) with Stress engineering has been explored in this work with a calibrated Silicon (Si) simulation deck. Silicon Nitride (Si3N4) layer having intrinsic stress has been used to generate stress in the device. Hybrid gate dielectric with Silicon dioxide (SiO2) and the Si3N4 is used in this study. With the help of simulations (Process, Device and Mixed-mode), we observe the drain current improvement of 6%, decrease in terminal capacitance and specific on-resistance (Ron,sp) and increase in the transition frequency. This method can supplement the existing performance improvement techniques for an LDMOSFET device.
{"title":"Hybrid gate dielectric with Si3N4 stressor for LDMOSFET","authors":"S. Nayak, S. Lodha, S. Ganguly","doi":"10.1109/LAEDC51812.2021.9437948","DOIUrl":"https://doi.org/10.1109/LAEDC51812.2021.9437948","url":null,"abstract":"Lateral double diffused MOSFET (LDMOSFET) with Stress engineering has been explored in this work with a calibrated Silicon (Si) simulation deck. Silicon Nitride (Si3N4) layer having intrinsic stress has been used to generate stress in the device. Hybrid gate dielectric with Silicon dioxide (SiO2) and the Si3N4 is used in this study. With the help of simulations (Process, Device and Mixed-mode), we observe the drain current improvement of 6%, decrease in terminal capacitance and specific on-resistance (Ron,sp) and increase in the transition frequency. This method can supplement the existing performance improvement techniques for an LDMOSFET device.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133921313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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