Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090604
S. Eilert, Mark Leinwander, G. Crisenza
PCM is both a sustaining technology and a disruptive technology. These two aspects can be complementarily considered to speed up PCM market penetration. In addition PCM can be exploited by the memory system and by the convergence of consumer, computer and communication electronic systems. Some topics of PCM penetration in different memory systems have been described. The caching of the existing memory technologies, reducing the overall system cost and system complexity will be the compelling motivation. Bandwidth will drive the sustaining side of PCM in code and data transfer applications, while reduction in power dissipation will represent a further added value of this technology.
{"title":"Phase Change Memory: A New Memory Enables New Memory Usage Models","authors":"S. Eilert, Mark Leinwander, G. Crisenza","doi":"10.1109/IMW.2009.5090604","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090604","url":null,"abstract":"PCM is both a sustaining technology and a disruptive technology. These two aspects can be complementarily considered to speed up PCM market penetration. In addition PCM can be exploited by the memory system and by the convergence of consumer, computer and communication electronic systems. Some topics of PCM penetration in different memory systems have been described. The caching of the existing memory technologies, reducing the overall system cost and system complexity will be the compelling motivation. Bandwidth will drive the sustaining side of PCM in code and data transfer applications, while reduction in power dissipation will represent a further added value of this technology.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090603
G. Gay, G. Molas, M. Bocquet, E. Jalaguier, M. Gely, L. Masarotto, J. Colonna, H. Grampeix, F. Martin, P. Brianceau, V. Vidal, R. Kies, K. Yckache, B. De Salvo, G. Ghibaudo, T. Baron, C. Bongiorno, S. Lombardo
In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid Si-nc double layer/SiN layer charge trapping media. These devices show a good memory window and good retention (>3 V after 10 years) with small activation energy (0.35 eV up to 200degC), thus being promising for future high-temperature memory applications.
{"title":"Performance and Reliability of Si-Nanocrystal Double Layer Memory Devices with High-k Control Dielectrics","authors":"G. Gay, G. Molas, M. Bocquet, E. Jalaguier, M. Gely, L. Masarotto, J. Colonna, H. Grampeix, F. Martin, P. Brianceau, V. Vidal, R. Kies, K. Yckache, B. De Salvo, G. Ghibaudo, T. Baron, C. Bongiorno, S. Lombardo","doi":"10.1109/IMW.2009.5090603","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090603","url":null,"abstract":"In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid Si-nc double layer/SiN layer charge trapping media. These devices show a good memory window and good retention (>3 V after 10 years) with small activation energy (0.35 eV up to 200degC), thus being promising for future high-temperature memory applications.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122094909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090597
S. Z. Rahaman, S. Maikap, Hsien-Chin Chiu, C. Lin, T. Wu, Y. Chen, P. Tzeng, Frederick T. Chen, M. Kao, Ming-Jinn Tsai
Bipolar resistive switching memory device with a low power operation (200μA/1.3V) in a W/Ge0.4Se0.6/Cu/Al structure has been investigated. A stronger Cu chain formation can be observed by monitoring both the erase voltage and current. The low resistance state (RLow) decreases with increasing the programming current from 1nA to 500μA, which can be useful for multi-level of data storage. This resistive memory device has a large threshold voltage of ~0.5V, good resistance ratio (RHigh/RLow) of 1.6x10 2 , good endurance of >1.5x10 5 cycles, and excellent retention (>11 hours) with a resistance ratio of > 1.3×10 2 at 150 o C can be used in future nonvolatile memories.
{"title":"Low Power Operation of Resistive Switching Memory Device Using Novel W/Ge0.4Se0.6/Cu/Al Structure","authors":"S. Z. Rahaman, S. Maikap, Hsien-Chin Chiu, C. Lin, T. Wu, Y. Chen, P. Tzeng, Frederick T. Chen, M. Kao, Ming-Jinn Tsai","doi":"10.1109/IMW.2009.5090597","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090597","url":null,"abstract":"Bipolar resistive switching memory device with a low power operation (200μA/1.3V) in a W/Ge0.4Se0.6/Cu/Al structure has been investigated. A stronger Cu chain formation can be observed by monitoring both the erase voltage and current. The low resistance state (RLow) decreases with increasing the programming current from 1nA to 500μA, which can be useful for multi-level of data storage. This resistive memory device has a large threshold voltage of ~0.5V, good resistance ratio (RHigh/RLow) of 1.6x10 2 , good endurance of >1.5x10 5 cycles, and excellent retention (>11 hours) with a resistance ratio of > 1.3×10 2 at 150 o C can be used in future nonvolatile memories.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090588
H. Yang, L. P. Shi, R. Zhao, H. K. Lee, J. M. Li, K. G. Lim, T. Chong
Phase change RAM (PCRAM) is one of the best candidates for the next-generation nonvolatile memory. Recently lateral PCRAM using a thin phase change bridge was proposed as a promising approach to achieve high density due to simpler fabrication process and lower RESET current. This paper proposes a new lateral PCRAM structure - edge contact lateral structure, together with a Sb 7 Te 3 -GeTe super-lattice-like (SLL) phase change medium to reduce the contact area, improve thermal confinement and hence reduce current. Its RESET current of 1.23 mA is less than that of normal lateral PCRAM with SLL (1.5 mA). It also shows good stability and resistance ratio after 105 overwriting cycles. Testing results are consistent with the simulation results.
{"title":"Edge Contact Lateral Phase Change RAM with Super-Lattice-Like Phase Change Medium","authors":"H. Yang, L. P. Shi, R. Zhao, H. K. Lee, J. M. Li, K. G. Lim, T. Chong","doi":"10.1109/IMW.2009.5090588","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090588","url":null,"abstract":"Phase change RAM (PCRAM) is one of the best candidates for the next-generation nonvolatile memory. Recently lateral PCRAM using a thin phase change bridge was proposed as a promising approach to achieve high density due to simpler fabrication process and lower RESET current. This paper proposes a new lateral PCRAM structure - edge contact lateral structure, together with a Sb 7 Te 3 -GeTe super-lattice-like (SLL) phase change medium to reduce the contact area, improve thermal confinement and hence reduce current. Its RESET current of 1.23 mA is less than that of normal lateral PCRAM with SLL (1.5 mA). It also shows good stability and resistance ratio after 105 overwriting cycles. Testing results are consistent with the simulation results.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126670817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090587
P. Singh, G. Bisht, R. Hofmann, K. Singh, S. Mahapatra
Most of the current high-density Flash cells use multi-level-cell (MLC) technology to store 2-bits/cell to increase memory density. In this work, dual layer metal nanocrystal (NC) flash EEPROM device, with large memory window, good retention and 10 4 cycle endurance is reported. High-temperature retention, gate bias accelerated retention, read disturb and post- cycling retention measurements show excellent reliability of the NC devices which make them suitable for the MLC application.
{"title":"Dual Layer Pt Metal Nanocrystal Flash for Multi-Level-Cell NAND Application","authors":"P. Singh, G. Bisht, R. Hofmann, K. Singh, S. Mahapatra","doi":"10.1109/IMW.2009.5090587","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090587","url":null,"abstract":"Most of the current high-density Flash cells use multi-level-cell (MLC) technology to store 2-bits/cell to increase memory density. In this work, dual layer metal nanocrystal (NC) flash EEPROM device, with large memory window, good retention and 10\u0000 4\u0000 cycle endurance is reported. High-temperature retention, gate bias accelerated retention, read disturb and post- cycling retention measurements show excellent reliability of the NC devices which make them suitable for the MLC application.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"4615 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090578
D. Shum, G. Jaschke, M. Canning, R. Kakoschke, R. Duschl, R. Sikorski, F. Erler, M. Stiftinger, A. Duch, J. Power, G. Tempel, R. Strenz, R. Allinger
We present aluminum oxide (AI 2 O 3 ) as high-k Inter-Poly Dielectric (IPD) in a proven 0.13 mum based embedded Flash (eFlash) technology. Full functionality has been demonstrated from a 400Kbyte product demonstrator for the first time published so far. The AI 2 O 3 layer was formed through Atomic-Layer Deposition (ALD) and the influence of parameters such as precursor, deposition temperature, feed-time and Si content on the product functionality have been determined systematically. Vigorous industrial reliability assessment was conducted throughout and promising retention and endurance have been shown. The results demonstrate AI 2 O 3 IPD readiness for eFlash products without additional integration issues or yield degradation.
{"title":"ALD-Al2O3 as an Inter-Poly Dielectric for a Product Demonstrator in a Proven eFlash Technology","authors":"D. Shum, G. Jaschke, M. Canning, R. Kakoschke, R. Duschl, R. Sikorski, F. Erler, M. Stiftinger, A. Duch, J. Power, G. Tempel, R. Strenz, R. Allinger","doi":"10.1109/IMW.2009.5090578","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090578","url":null,"abstract":"We present aluminum oxide (AI 2 O 3 ) as high-k Inter-Poly Dielectric (IPD) in a proven 0.13 mum based embedded Flash (eFlash) technology. Full functionality has been demonstrated from a 400Kbyte product demonstrator for the first time published so far. The AI 2 O 3 layer was formed through Atomic-Layer Deposition (ALD) and the influence of parameters such as precursor, deposition temperature, feed-time and Si content on the product functionality have been determined systematically. Vigorous industrial reliability assessment was conducted throughout and promising retention and endurance have been shown. The results demonstrate AI 2 O 3 IPD readiness for eFlash products without additional integration issues or yield degradation.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133928699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090592
Ki-Heung Park, Young Min Kim, H. Kwon, S. Kong, Jong-Ho Lee
We have investigated a fully depleted double-gate 1-T DRAM cell device which has SONOS type storage node on control gate for nonvolatile memory function. Due to enlarged hole capacity by the large storage node and source/drain junction depth control in the floating body, we could improving data retention time, I s ,(write"1")/I s ,(write"0") and device scalability. Proposed device could be a very promising candidate for a future high density and high performance IT-DRAM cell.
{"title":"Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM","authors":"Ki-Heung Park, Young Min Kim, H. Kwon, S. Kong, Jong-Ho Lee","doi":"10.1109/IMW.2009.5090592","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090592","url":null,"abstract":"We have investigated a fully depleted double-gate 1-T DRAM cell device which has SONOS type storage node on control gate for nonvolatile memory function. Due to enlarged hole capacity by the large storage node and source/drain junction depth control in the floating body, we could improving data retention time, I s ,(write\"1\")/I s ,(write\"0\") and device scalability. Proposed device could be a very promising candidate for a future high density and high performance IT-DRAM cell.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125132105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090582
Jeong-Uk Han, Yong Kyu Lee, Changmin Jeon, Jido Ryu, Eunmi Hong, Seungjin Yang, Youngho Kim, Hyucksoo Yang, Hyun-Khe Yoo, Jaemin Yu, Hoonjin Bang, Seung-Woon Lee, B. Lee, Daesop Lee, E. Jung, C. Chung
We have firstly demonstrated a hybrid flash including both NOR and NAND cell in a single chip using 90 nm logic technology for S-SIM (Super-Subscriber Identity Module) application. The memory sizes are 16 MB NAND and 768 kB NOR flash, respectively. The flash memory cells exhibited over 10 k-cycle endurance and 10-year retention for the successful smart card application.
我们首次展示了一种混合闪存，包括在一个芯片上使用90纳米逻辑技术的NOR和NAND单元，用于S-SIM(超级用户身份模块)应用。内存大小分别为16mb NAND和768kb NOR flash。在智能卡的成功应用中，闪存细胞表现出超过10 k周期的耐久性和10年的保留率。
{"title":"Both NOR and NAND Embedded Hybrid Flash for S-SIM Application Using 90 nm Process Technology","authors":"Jeong-Uk Han, Yong Kyu Lee, Changmin Jeon, Jido Ryu, Eunmi Hong, Seungjin Yang, Youngho Kim, Hyucksoo Yang, Hyun-Khe Yoo, Jaemin Yu, Hoonjin Bang, Seung-Woon Lee, B. Lee, Daesop Lee, E. Jung, C. Chung","doi":"10.1109/IMW.2009.5090582","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090582","url":null,"abstract":"We have firstly demonstrated a hybrid flash including both NOR and NAND cell in a single chip using 90 nm logic technology for S-SIM (Super-Subscriber Identity Module) application. The memory sizes are 16 MB NAND and 768 kB NOR flash, respectively. The flash memory cells exhibited over 10 k-cycle endurance and 10-year retention for the successful smart card application.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"63 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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