Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090572
S. Tanakamaru, K. Takeuchi
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.
{"title":"A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs","authors":"S. Tanakamaru, K. Takeuchi","doi":"10.1109/IMW.2009.5090572","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090572","url":null,"abstract":"A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127205972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090585
Andrea Fantini, L. Perniola, Marilyn Armand, J. Nodin, V. Sousa, A. Persico, J. Cluzel, C. Jahan, S. Maitrejean, Sandrine Lhostis, A. Roule, C. Dressler, G. Reimbold, B. D. Salvo, Pascale Mazoyer, Daniel Bensahel, F. Boulanger
This work presents a thorough comparative assessment of undoped GST and GeTe active phase-change (PC) materials for application to embedded memory devices (in particular consumer and automotive products). The material screening and qualification is performed through optical reflectivity and 4-probes resistivity measurements. Electrical performances are then investigated through tests of lance-cell analytical PC memory cells. Reset current densities of GST and GeTe are comparable, while GeTe data-retention at high- temperature is significantly improved compared to GST, suggesting that GeTe-based compounds are promising candidates for embedded PC memory applications.
{"title":"Comparative Assessment of GST and GeTe Materials for Application to Embedded Phase-Change Memory Devices","authors":"Andrea Fantini, L. Perniola, Marilyn Armand, J. Nodin, V. Sousa, A. Persico, J. Cluzel, C. Jahan, S. Maitrejean, Sandrine Lhostis, A. Roule, C. Dressler, G. Reimbold, B. D. Salvo, Pascale Mazoyer, Daniel Bensahel, F. Boulanger","doi":"10.1109/IMW.2009.5090585","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090585","url":null,"abstract":"This work presents a thorough comparative assessment of undoped GST and GeTe active phase-change (PC) materials for application to embedded memory devices (in particular consumer and automotive products). The material screening and qualification is performed through optical reflectivity and 4-probes resistivity measurements. Electrical performances are then investigated through tests of lance-cell analytical PC memory cells. Reset current densities of GST and GeTe are comparable, while GeTe data-retention at high- temperature is significantly improved compared to GST, suggesting that GeTe-based compounds are promising candidates for embedded PC memory applications.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132541933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090580
Shu Li, Tong Zhang
This paper applies information theory to formulate and estimate the NAND flash memory storage efficiency bound, and shows a big gap between the theoretical bound and what is achievable today. We further present two techniques to reduce the gap and demonstrate their promising potential using 2 bits/cell NAND flash memories as a test vehicle.
{"title":"Approaching the Information Theoretical Bound of Multi-Level NAND Flash Memory Storage Efficiency","authors":"Shu Li, Tong Zhang","doi":"10.1109/IMW.2009.5090580","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090580","url":null,"abstract":"This paper applies information theory to formulate and estimate the NAND flash memory storage efficiency bound, and shows a big gap between the theoretical bound and what is achievable today. We further present two techniques to reduce the gap and demonstrate their promising potential using 2 bits/cell NAND flash memories as a test vehicle.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090594
D. Gilmer, N. Goel, H. Park, C. Park, J. Barnett, P. Kirsch, R. Jammy
We demonstrate for the first time molybdenum based oxygen-bearing electrodes for improved performance in MANOS (Metal-Alumina-Nitride-Oxide) charge-trap NVM, and also MIM-DRAM type devices. The meta-stable high work- function (Wfn) molybdenum-oxynitride (MoON) electrodes result in improved retention and erase saturation for the charge trap NVM devices and improved leakage for the MIM devices. Although some of the observed improvements, compared to conventional TaN or TIN electrodes, can be attributed to the higher effective Wfn of the MoON, the improvements are also attributed to free oxygen available during deposition, and also released from the MoON electrode during thermal processing, repairing defects in the respective dielectrics adjacent to the MoON electrodes.
{"title":"High Work-Function Oxygen-Bearing Electrodes for Improved Performance in MANOS Charge-Trap NVM and MIM-DRAM Type Devices","authors":"D. Gilmer, N. Goel, H. Park, C. Park, J. Barnett, P. Kirsch, R. Jammy","doi":"10.1109/IMW.2009.5090594","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090594","url":null,"abstract":"We demonstrate for the first time molybdenum based oxygen-bearing electrodes for improved performance in MANOS (Metal-Alumina-Nitride-Oxide) charge-trap NVM, and also MIM-DRAM type devices. The meta-stable high work- function (Wfn) molybdenum-oxynitride (MoON) electrodes result in improved retention and erase saturation for the charge trap NVM devices and improved leakage for the MIM devices. Although some of the observed improvements, compared to conventional TaN or TIN electrodes, can be attributed to the higher effective Wfn of the MoON, the improvements are also attributed to free oxygen available during deposition, and also released from the MoON electrode during thermal processing, repairing defects in the respective dielectrics adjacent to the MoON electrodes.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126125862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090600
Y. Koh
With the advent of prevailing mobile devices in our daily lives, the densities of nonvolatile memory, especially NAND Flash suitable for mobile devices become higher and higher, and Flash memory applications will be constantly increased in the future due to their non-volatility and high capacity. Therefore it is very meaningful and important to summarize where NAND Flash memory technology is now, what kinds of challenges have to be overcome, and what the promising candidates will be in the future. In this paper, we present the major scaling issues and performance requirements for NAND Flash with advancing technology nodes, and we also show directions for new emerging technologies beyond 20 nm technology node.
{"title":"NAND Flash Scaling Beyond 20nm","authors":"Y. Koh","doi":"10.1109/IMW.2009.5090600","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090600","url":null,"abstract":"With the advent of prevailing mobile devices in our daily lives, the densities of nonvolatile memory, especially NAND Flash suitable for mobile devices become higher and higher, and Flash memory applications will be constantly increased in the future due to their non-volatility and high capacity. Therefore it is very meaningful and important to summarize where NAND Flash memory technology is now, what kinds of challenges have to be overcome, and what the promising candidates will be in the future. In this paper, we present the major scaling issues and performance requirements for NAND Flash with advancing technology nodes, and we also show directions for new emerging technologies beyond 20 nm technology node.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122793495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090583
C. H. Liu, Y. M. Lin, D. Yin, G. Tseng, H. Liaw, H. Wei, S. H. Chen, C. Chao, H. Hwang, S. Pittikoun, S. Aritome
The various methods of multi-nitridation ONO to improve NAND flash memory have been demonstrated in this paper. Excellent cell performance and reliability are obtained compared to convention ONO: (1) 1.9 V program voltage reduction owing to 23 A EOT (equivalant oxide thickness) reduction (2) More than 20% tighter cell Vt distribution width and 30% narrower Vth shift after 10 K cycling can be achieved by supressing ONO bird's beak encroachment of gate re-oxidation by floating gate (FG)/top oxide nitridation. MN-ONO is a promising technology for high density NAND flash beyond 40 nm generation.
本文介绍了多氮化ONO改进NAND闪存的各种方法。与传统ONO相比，获得了优异的电池性能和可靠性:(1)由于23 A EOT(等效氧化物厚度)降低，程序电压降低1.9 V;(2)通过浮栅(FG)/顶部氧化物氮化抑制ONO鸟嘴侵蚀栅极再氧化，可实现10 K循环后电池Vt分布宽度缩短20%以上，Vth移位缩短30%以上。MN-ONO是一种很有前途的40纳米以上高密度NAND闪存技术。
{"title":"Bottom Nitridation Engineering of Multi-Nitridation ONO Interpoly Dielectric for Highly Reliable and High Performance NAND Flash Memory","authors":"C. H. Liu, Y. M. Lin, D. Yin, G. Tseng, H. Liaw, H. Wei, S. H. Chen, C. Chao, H. Hwang, S. Pittikoun, S. Aritome","doi":"10.1109/IMW.2009.5090583","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090583","url":null,"abstract":"The various methods of multi-nitridation ONO to improve NAND flash memory have been demonstrated in this paper. Excellent cell performance and reliability are obtained compared to convention ONO: (1) 1.9 V program voltage reduction owing to 23 A EOT (equivalant oxide thickness) reduction (2) More than 20% tighter cell Vt distribution width and 30% narrower Vth shift after 10 K cycling can be achieved by supressing ONO bird's beak encroachment of gate re-oxidation by floating gate (FG)/top oxide nitridation. MN-ONO is a promising technology for high density NAND flash beyond 40 nm generation.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131393644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090584
Eun-Seok Choi, Se-Jun Kim, Soon-Ok Seo, Hyunseung Yoo, Kyoung-Hwan Park, Sung-Wook Jung, Se-yun Lim, H. Joo, Gyo-Ji Kim, Sang-Bum Lee, Sang-Hyun Oh, J. Om, J. Yi, Seok-Kiu Lee
MT reliability of MANOS cell was examined from cell array. Lots of retention tail bits occurred even at RT. The fail cells were classified as the manner of q-loss. Defective cell lost abundant charge at early stage, while the q-loss rate of worse cell was faster and lasted in a certain period. Si-cluster in our nitride was supposed to make the worse cell, and this cell redeemed its retention capability by reducing shallow trap in Si-rich nitride.
{"title":"Chip Level Reliability of MANOS Cells under Operating Conditions","authors":"Eun-Seok Choi, Se-Jun Kim, Soon-Ok Seo, Hyunseung Yoo, Kyoung-Hwan Park, Sung-Wook Jung, Se-yun Lim, H. Joo, Gyo-Ji Kim, Sang-Bum Lee, Sang-Hyun Oh, J. Om, J. Yi, Seok-Kiu Lee","doi":"10.1109/IMW.2009.5090584","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090584","url":null,"abstract":"MT reliability of MANOS cell was examined from cell array. Lots of retention tail bits occurred even at RT. The fail cells were classified as the manner of q-loss. Defective cell lost abundant charge at early stage, while the q-loss rate of worse cell was faster and lasted in a certain period. Si-cluster in our nitride was supposed to make the worse cell, and this cell redeemed its retention capability by reducing shallow trap in Si-rich nitride.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114264625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090570
J. Yater, M. Suhail, S. Kang, J. Shen, C. Hong, T. Merchant, R. Rao, H. Gasquet, K. Loiko, B. Winstead, S. Williams, M. Rossow, W. Malloch, R. Syzdek, G. Chindalore
This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.
{"title":"16Mb Split Gate Flash Memory with Improved Process Window","authors":"J. Yater, M. Suhail, S. Kang, J. Shen, C. Hong, T. Merchant, R. Rao, H. Gasquet, K. Loiko, B. Winstead, S. Williams, M. Rossow, W. Malloch, R. Syzdek, G. Chindalore","doi":"10.1109/IMW.2009.5090570","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090570","url":null,"abstract":"This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"422 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090596
G. Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. van Houdt
TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.
{"title":"Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory","authors":"G. Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. van Houdt","doi":"10.1109/IMW.2009.5090596","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090596","url":null,"abstract":"TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123099985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090586
L. Liu, X. Sun, B. Sun, J. Kang, Y. Wang, X. Liu, R. Han, G. Xiong
The RS behaviors of stoichiometric and nonstoichiometric CeOx films were studied. Current compliance-free resistive switching was achieved in the nonstoichiometric CeOx film, which are helpful to remove the limitation of current compliance to simplify RRAM circuits design.
{"title":"Current Compliance-Free Resistive Switching in Nonstoichiometric CeOx Films for Nonvolatile Memory Application","authors":"L. Liu, X. Sun, B. Sun, J. Kang, Y. Wang, X. Liu, R. Han, G. Xiong","doi":"10.1109/IMW.2009.5090586","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090586","url":null,"abstract":"The RS behaviors of stoichiometric and nonstoichiometric CeOx films were studied. Current compliance-free resistive switching was achieved in the nonstoichiometric CeOx film, which are helpful to remove the limitation of current compliance to simplify RRAM circuits design.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122621198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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