Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090577
P. Zhou, H. Wan, Y. L. Song, M. Yin, H. Lv, Yinyin Lin, S. Song, R. Huang, J. Wu, M. Chi
The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-Cu x O-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive random access memory (RRAM) resistor connected in series with a select transistor. Results show that the structure of TiN-Cu x O-Cu with its compatibility to CMOS technology appears a promising memory device for embedded application.
TiN- cu x O-Cu(以TiN帽层为顶电极)在85℃下保持时间长达10年以上，具有优异的热可靠性记忆。TiN帽层使得在正脉冲下从低阻状态(LRS)复位到高阻状态(HRS)和在负脉冲下的SET复位更加稳定，这有利于在与选择晶体管串联的电阻式随机存取存储器(RRAM)电阻上提供大的编程电流或电压。结果表明，TiN-Cu x O-Cu结构与CMOS技术兼容，是一种很有前途的嵌入式存储器件。
{"title":"A Systematic Investigation of TiN/CuxO/Cu RRAM with Long Retention and Excellent Thermal Stability","authors":"P. Zhou, H. Wan, Y. L. Song, M. Yin, H. Lv, Yinyin Lin, S. Song, R. Huang, J. Wu, M. Chi","doi":"10.1109/IMW.2009.5090577","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090577","url":null,"abstract":"The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-Cu x O-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive random access memory (RRAM) resistor connected in series with a select transistor. Results show that the structure of TiN-Cu x O-Cu with its compatibility to CMOS technology appears a promising memory device for embedded application.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124873414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090574
Hsin-Heng Wang, Pei-Shan Shieh, Chiutsung Huang, K. Tokami, R. Kuo, Shin-Hsien Chen, Houng-Chi Wei, S. Pittikoun, S. Aritome
In this paper, we have reported a new failure phenomenon of read-disturb in MLC NAND flash memory caused by boosting hot-carrier injection effect. (1) The read-disturb failure occurred on unselected WL (WLn+1) after the adjacent selected WL (WLn) was performed with more than 1K read cycles. (2) The read-disturb failure of WLn+1 depends on WLn cell's Vth and its applied voltage. (3) The mechanism of this kind of failure can be explained by hot carrier injection that is generated by discharging from boosting voltage in unselected cell area (Drain of WLn) to ground (Source of WLn).
{"title":"A New Read-Disturb Failure Mechanism Caused by Boosting Hot-Carrier Injection Effect in MLC NAND Flash Memory","authors":"Hsin-Heng Wang, Pei-Shan Shieh, Chiutsung Huang, K. Tokami, R. Kuo, Shin-Hsien Chen, Houng-Chi Wei, S. Pittikoun, S. Aritome","doi":"10.1109/IMW.2009.5090574","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090574","url":null,"abstract":"In this paper, we have reported a new failure phenomenon of read-disturb in MLC NAND flash memory caused by boosting hot-carrier injection effect. (1) The read-disturb failure occurred on unselected WL (WLn+1) after the adjacent selected WL (WLn) was performed with more than 1K read cycles. (2) The read-disturb failure of WLn+1 depends on WLn cell's Vth and its applied voltage. (3) The mechanism of this kind of failure can be explained by hot carrier injection that is generated by discharging from boosting voltage in unselected cell area (Drain of WLn) to ground (Source of WLn).","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127854382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090593
Y. Roizin, E. Pikhay, V. Dayan, A. Heiman
We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.
{"title":"High Density MTP Logic NVM for Power Management Applications","authors":"Y. Roizin, E. Pikhay, V. Dayan, A. Heiman","doi":"10.1109/IMW.2009.5090593","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090593","url":null,"abstract":"We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131961507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090606
A. Demolliens, C. Muller, D. Deleruyelle, S. Spiga, E. Cianci, M. Fanciulli, F. Nardi, C. Cagli, D. Ielmini
As Flash memories are approaching their ultimate scaling limit, reversible resistance switching attracts considerable interest because of its potential for high density non volatile memory devices. Resistive switching phenomena have been reported in many transition metal oxide films such as TiO 2 or MO. This work investigates the feasibility of emerging resistive- switching devices with NiO active dielectric layer on top of a pillar W bottom electrode. Reversible and repetitive switching is demonstrated for ReRAM cells with diameters ranging from 0.18 to 1 mum. Scaling and cycling capabilities are discussed and preliminary TEM results enable apprehending reliability issues and failure mechanisms.
{"title":"Reliability of NiO-Based Resistive Switching Memory (ReRAM) Elements with Pillar W Bottom Electrode","authors":"A. Demolliens, C. Muller, D. Deleruyelle, S. Spiga, E. Cianci, M. Fanciulli, F. Nardi, C. Cagli, D. Ielmini","doi":"10.1109/IMW.2009.5090606","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090606","url":null,"abstract":"As Flash memories are approaching their ultimate scaling limit, reversible resistance switching attracts considerable interest because of its potential for high density non volatile memory devices. Resistive switching phenomena have been reported in many transition metal oxide films such as TiO 2 or MO. This work investigates the feasibility of emerging resistive- switching devices with NiO active dielectric layer on top of a pillar W bottom electrode. Reversible and repetitive switching is demonstrated for ReRAM cells with diameters ranging from 0.18 to 1 mum. Scaling and cycling capabilities are discussed and preliminary TEM results enable apprehending reliability issues and failure mechanisms.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131635161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090608
E. Souchier, L. Cario, B. Corraze, C. Estournès, V. Fernandez, T. Skotnicki, P. Mazoyer, E. Janod, M. Besland
In that work, we show that RF magnetron sputtering can be used to obtain pure and crystallized thin layers of GaV 4 S 8 films with a well controlled composition, depending mainly on RF power and deposition pressure. The obtained layers exhibit similar structural and physical properties as GaV 4 S 8 polycrystal or crystal. In addition, we have successfully demonstrated that a reversible resistive switching can also be obtained on thin layers. Electrical measurements will be further investigated on thinner layers and for shorter pulse time. Nevertheless, these preliminary results obtained on Au/Si substrates are very promising for further RRAM applications.
{"title":"Thin Layers Obtained by Plasma Process for Emerging Non-Volatile Memory (RRAM) Applications","authors":"E. Souchier, L. Cario, B. Corraze, C. Estournès, V. Fernandez, T. Skotnicki, P. Mazoyer, E. Janod, M. Besland","doi":"10.1109/IMW.2009.5090608","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090608","url":null,"abstract":"In that work, we show that RF magnetron sputtering can be used to obtain pure and crystallized thin layers of GaV 4 S 8 films with a well controlled composition, depending mainly on RF power and deposition pressure. The obtained layers exhibit similar structural and physical properties as GaV 4 S 8 polycrystal or crystal. In addition, we have successfully demonstrated that a reversible resistive switching can also be obtained on thin layers. Electrical measurements will be further investigated on thinner layers and for shorter pulse time. Nevertheless, these preliminary results obtained on Au/Si substrates are very promising for further RRAM applications.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"37 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090589
Chieh-Fang Chen, A. Schrott, Ming-Hsiu Lee, Simone Raoux, Yen-Hao Shih, M. Breitwisch, F. Baumann, Erh-Kun Lai, Thomas M. Shaw, Philip L. Flaitz, R. Cheek, Eric A. Joseph, S. H. Chen, Bipin Rajendran, H. Lung, C. H. Lam
We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.
{"title":"Endurance Improvement of Ge2Sb2Te5-Based Phase Change Memory","authors":"Chieh-Fang Chen, A. Schrott, Ming-Hsiu Lee, Simone Raoux, Yen-Hao Shih, M. Breitwisch, F. Baumann, Erh-Kun Lai, Thomas M. Shaw, Philip L. Flaitz, R. Cheek, Eric A. Joseph, S. H. Chen, Bipin Rajendran, H. Lung, C. H. Lam","doi":"10.1109/IMW.2009.5090589","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090589","url":null,"abstract":"We describe a cycling failure mode in Ge\u0000 2\u0000Sb\u0000 2\u0000Te\u0000 5\u0000-based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10\u0000 9\u0000 cycles.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121333591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090607
P. Blomme, J. van Houdt
We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.
{"title":"Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm","authors":"P. Blomme, J. van Houdt","doi":"10.1109/IMW.2009.5090607","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090607","url":null,"abstract":"We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090599
W. Chien, Y. C. Chen, K. P. Chang, E. Lai, Y. Yao, P. Lin, J. Gong, S. Tsai, S. Hsieh, C. F. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu
The multi-level operation of WO x based RRAM has been investigated. Improvement of our WO x process has produced an extended linear R-V region for our devices. By adding an electrical forming process and a program-verify algorithm we have demonstrated stable 2-bit/cell operation, with potential for 3-bit/cell. The reliability of the MLC operation has been examined and very stable high temperature retention, robust read disturb immunity and initial cycling endurance of >1,000 times have been demonstrated.
{"title":"Multi-Level Operation of Fully CMOS Compatible WOX Resistive Random Access Memory (RRAM)","authors":"W. Chien, Y. C. Chen, K. P. Chang, E. Lai, Y. Yao, P. Lin, J. Gong, S. Tsai, S. Hsieh, C. F. Chen, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/IMW.2009.5090599","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090599","url":null,"abstract":"The multi-level operation of WO\u0000 x\u0000 based RRAM has been investigated. Improvement of our WO\u0000 x\u0000 process has produced an extended linear R-V region for our devices. By adding an electrical forming process and a program-verify algorithm we have demonstrated stable 2-bit/cell operation, with potential for 3-bit/cell. The reliability of the MLC operation has been examined and very stable high temperature retention, robust read disturb immunity and initial cycling endurance of >1,000 times have been demonstrated.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128157522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090573
T. Ogura, M. Mihara, Y. Kawajiri, K. Kobayashi, S. Shimizu, S. Shukuri, N. Ajika, M. Nakashima
A 90 nm floating gate NOR B4-Flash memory with IF (F: minimum feature size) gate length cell has been investigated by using 64 Mbit test chip to evaluate the scalability of B4-Flash memory. 90 nm (=1F) gate length of memory cell is shortest in many NOR flash memories reported previously. Basic program and erase characteristics and robust program disturb immunity of B4-Flash memory utilizing NMOS select transistor in memory cell array have been demonstrated. Furthermore, to simplify the peripheral circuits and reduce a die size, a new charge pump circuit which can generate both positive and negative high voltage at a supply voltage of 1.8 V has been introduced.
{"title":"A 90nm Floating Gate \"B4-Flash\" Memory Technology- Breakthrough of the Gate Length Limitation on NOR Flash Memory","authors":"T. Ogura, M. Mihara, Y. Kawajiri, K. Kobayashi, S. Shimizu, S. Shukuri, N. Ajika, M. Nakashima","doi":"10.1109/IMW.2009.5090573","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090573","url":null,"abstract":"A 90 nm floating gate NOR B4-Flash memory with IF (F: minimum feature size) gate length cell has been investigated by using 64 Mbit test chip to evaluate the scalability of B4-Flash memory. 90 nm (=1F) gate length of memory cell is shortest in many NOR flash memories reported previously. Basic program and erase characteristics and robust program disturb immunity of B4-Flash memory utilizing NMOS select transistor in memory cell array have been demonstrated. Furthermore, to simplify the peripheral circuits and reduce a die size, a new charge pump circuit which can generate both positive and negative high voltage at a supply voltage of 1.8 V has been introduced.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090595
M. F. Beug, T. Melde, J. Paul, U. Bewersdorff-Sarlette, M. Czernohorsky, V. Beyer, R. Hoffmann, K. Seidel, D. Lohr, L. Bach, R. Knoefler, A. Tilke
This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.
{"title":"Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner","authors":"M. F. Beug, T. Melde, J. Paul, U. Bewersdorff-Sarlette, M. Czernohorsky, V. Beyer, R. Hoffmann, K. Seidel, D. Lohr, L. Bach, R. Knoefler, A. Tilke","doi":"10.1109/IMW.2009.5090595","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090595","url":null,"abstract":"This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121026623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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