Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341224
B. Baddipadiga, S. Strathman, M. Ferdowsi, J. Kimball
This paper introduces a high-voltage-gain dc-dc converter designed to act as a power processing unit for a multi-mode monopropellant-electrospray propulsion system used in satellites. The high-voltage-gain converter is capable of offering a voltage gain ranging from 200 to 350. This converter is made up of two stages: 1). A two-phase interleaved boost stage on the input side and 2). A Cockcroft-Walton voltage multiplier on the output side. This converter is employed to boost a 15 V battery voltage to 3400 V required for operating the thruster in electrical mode. The theoretical analysis and design procedure of the converter is discussed in detail. Hardware test results supporting the converter operation and analysis are also provided.
{"title":"A high-voltage-gain DC-DC converter for powering a multi-mode monopropellant-electrospray propulsion system in satellites","authors":"B. Baddipadiga, S. Strathman, M. Ferdowsi, J. Kimball","doi":"10.1109/APEC.2018.8341224","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341224","url":null,"abstract":"This paper introduces a high-voltage-gain dc-dc converter designed to act as a power processing unit for a multi-mode monopropellant-electrospray propulsion system used in satellites. The high-voltage-gain converter is capable of offering a voltage gain ranging from 200 to 350. This converter is made up of two stages: 1). A two-phase interleaved boost stage on the input side and 2). A Cockcroft-Walton voltage multiplier on the output side. This converter is employed to boost a 15 V battery voltage to 3400 V required for operating the thruster in electrical mode. The theoretical analysis and design procedure of the converter is discussed in detail. Hardware test results supporting the converter operation and analysis are also provided.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133126840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341402
Mehrdad Biglarbegian, Namwon Kim, Tiefu Zhao, B. Parkhideh
This paper presents the design of the Isolated SenseGaN (Iso-SenseGaN) current sensing technique using Gallium Nitride (GaN) transistors. The isolation technique for the SenseGaN brings an opportunity for integration of sensing element with the power modules, and enables many control schemes in power converters. This could effectively open broader area for smart device monitoring, implementation of current controlling techniques at high frequency, and proper feedback for diagnostics/prognostics developments. In this work, the focus is on the practical challenges for the SenseGaN technique and presenting the inductor-based galvanic isolation. Using the current mirroring method, the authors defined a cursor for detection of the power converter operation mode, i.e., Continuous Conduction Mode (CCM) vs. Boundary Conduction Mode (BCM) in a DC-DC boost and a DC-AC converter a real-time setup.
{"title":"Development of Isolated SenseGaN current monitoring for boundary conduction mode control of power converters","authors":"Mehrdad Biglarbegian, Namwon Kim, Tiefu Zhao, B. Parkhideh","doi":"10.1109/APEC.2018.8341402","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341402","url":null,"abstract":"This paper presents the design of the Isolated SenseGaN (Iso-SenseGaN) current sensing technique using Gallium Nitride (GaN) transistors. The isolation technique for the SenseGaN brings an opportunity for integration of sensing element with the power modules, and enables many control schemes in power converters. This could effectively open broader area for smart device monitoring, implementation of current controlling techniques at high frequency, and proper feedback for diagnostics/prognostics developments. In this work, the focus is on the practical challenges for the SenseGaN technique and presenting the inductor-based galvanic isolation. Using the current mirroring method, the authors defined a cursor for detection of the power converter operation mode, i.e., Continuous Conduction Mode (CCM) vs. Boundary Conduction Mode (BCM) in a DC-DC boost and a DC-AC converter a real-time setup.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341171
O. Kilic, A. Elrayyah, Y. Sozer
In this paper, a switched reluctance motor (SRM) with a new winding configuration and a novel power converter topology is presented. The new winding topology along with the power converter are developed to improve the machine efficiency by exciting only the portion of the phase windings at high speeds. The new configuration helps overcoming the effect of the high back EMF (Electromotive Force) and hence improving the torque speed characteristics of the SRM. The proposed configuration is investigated using coupled Finite Element Analysis (FEA) and circuit simulations on a case study motor. The new SRM drive and its associated control have been experimentally tested.
{"title":"Torque ripple minimization in SRMs at medium and high speeds using a multi-stator windings with a novel power converter","authors":"O. Kilic, A. Elrayyah, Y. Sozer","doi":"10.1109/APEC.2018.8341171","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341171","url":null,"abstract":"In this paper, a switched reluctance motor (SRM) with a new winding configuration and a novel power converter topology is presented. The new winding topology along with the power converter are developed to improve the machine efficiency by exciting only the portion of the phase windings at high speeds. The new configuration helps overcoming the effect of the high back EMF (Electromotive Force) and hence improving the torque speed characteristics of the SRM. The proposed configuration is investigated using coupled Finite Element Analysis (FEA) and circuit simulations on a case study motor. The new SRM drive and its associated control have been experimentally tested.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131702314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341567
Namwon Kim, Mehrdad Biglarbegian, B. Parkhideh
Integration of energy storage with a grid-tied photovoltaic (PV) generation system in conventional residential and commercial applications uses legacy PV power electronics topologies. This paper presents a novel solar PV power electronics system which allows a seamless integration of energy storage with partial power processing technique. In the proposed topology, a dual active bridge DC-DC converter is applied to configure partially-rated power electronics system with bi-directional power flow, galvanic isolation, a high voltage boosting gain, and results in high conversion efficiency. The proposed topology is explained in detail and analyzed with the quantitative approach to verify the improvement of system efficiency and power density in the DC-DC power conversion unit: 99.5% efficiency and 3.3kW rated power for 7.5kW PV and 2.5kW battery system. Also, the steady-state operation of the proposed universal optimizer is verified through the controller hardware-in-the-loop test.
{"title":"Flexible high efficiency battery-ready PV inverter for rooftop systems","authors":"Namwon Kim, Mehrdad Biglarbegian, B. Parkhideh","doi":"10.1109/APEC.2018.8341567","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341567","url":null,"abstract":"Integration of energy storage with a grid-tied photovoltaic (PV) generation system in conventional residential and commercial applications uses legacy PV power electronics topologies. This paper presents a novel solar PV power electronics system which allows a seamless integration of energy storage with partial power processing technique. In the proposed topology, a dual active bridge DC-DC converter is applied to configure partially-rated power electronics system with bi-directional power flow, galvanic isolation, a high voltage boosting gain, and results in high conversion efficiency. The proposed topology is explained in detail and analyzed with the quantitative approach to verify the improvement of system efficiency and power density in the DC-DC power conversion unit: 99.5% efficiency and 3.3kW rated power for 7.5kW PV and 2.5kW battery system. Also, the steady-state operation of the proposed universal optimizer is verified through the controller hardware-in-the-loop test.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122343516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341372
G. Knabben, D. Neumayr, J. Kolar
Despite the increasing performance of power semi-conductors and passives components, limited timing resolution in off-the-shelf available digital control hardware often prevents the switching frequency in kW-scale dc/ac power conversion to be increased above several MHz for the sake of extreme power densities. In this paper an alternative approach to generate a sinusoidal output voltage, based on constant duty cycle frequency shift control of a high frequency resonant inverter stage and a subsequent synchronous cycloconverter, is analyzed. The design of the presented converter is facilitated by means of a derived mathematical model. A novel closed-loop control system is proposed which achieves tight regulation of the output voltage by means of controlling the switching frequencies of the involved bridge legs operated in resonant mode. Characteristic waveforms of the dc/ac converter during steady-state and load transients are presented. Two distinct implementations of the resonant inverter stage, constituting an intermediate voltage or intermediate current link, are analysed and compared.
{"title":"Constant duty cycle sinusoidal output inverter with sine amplitude modulated high frequency link","authors":"G. Knabben, D. Neumayr, J. Kolar","doi":"10.1109/APEC.2018.8341372","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341372","url":null,"abstract":"Despite the increasing performance of power semi-conductors and passives components, limited timing resolution in off-the-shelf available digital control hardware often prevents the switching frequency in kW-scale dc/ac power conversion to be increased above several MHz for the sake of extreme power densities. In this paper an alternative approach to generate a sinusoidal output voltage, based on constant duty cycle frequency shift control of a high frequency resonant inverter stage and a subsequent synchronous cycloconverter, is analyzed. The design of the presented converter is facilitated by means of a derived mathematical model. A novel closed-loop control system is proposed which achieves tight regulation of the output voltage by means of controlling the switching frequencies of the involved bridge legs operated in resonant mode. Characteristic waveforms of the dc/ac converter during steady-state and load transients are presented. Two distinct implementations of the resonant inverter stage, constituting an intermediate voltage or intermediate current link, are analysed and compared.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341117
Juncheng Lu, Ruoyu Hou, Di Chen
Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) exhibit superior performance versus Si devices in both hard-switching and soft-switching converters. Due to the relatively higher switching-on loss compared with switching-off loss, zero voltage switching (ZVS) turn-on is still preferred to the application scope which efficiency is the primary design target. In this paper, the characteristics of GaN HEMTs under ZVS conditions is modeled. The packaging considerations on circuit parasitics and thermal management for soft switching applications is also discussed. An insulated metal substrate (IMS) based half-bridge power module consisting of two high-side and two low-side 650 V/60 A GaN HEMTs in parallel is designed and experimentally evaluated. A strong correlation is shown between simulations and experiments, verifying the power module design and GaN HEMTs' loss model.
氮化镓增强型高电子迁移率晶体管(GaN e - hemt)在硬开关和软开关变换器中都表现出优于Si器件的性能。由于零电压开关(zero voltage switching, ZVS)的导通损耗相对于关断损耗相对较高，因此在以效率为主要设计目标的应用范围中，仍优先考虑零电压开关导通。本文建立了ZVS条件下GaN hemt的特性模型。讨论了软开关应用中电路寄生和热管理方面的封装考虑。设计了一种基于绝缘金属基板(IMS)的半桥功率模块，该模块由两个高侧和两个低侧650v / 60a GaN hemt并联组成。仿真结果与实验结果具有较强的相关性，验证了功率模块设计和GaN hemt的损耗模型。
{"title":"Opportunities and design considerations of GaN HEMTs in ZVS applications","authors":"Juncheng Lu, Ruoyu Hou, Di Chen","doi":"10.1109/APEC.2018.8341117","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341117","url":null,"abstract":"Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) exhibit superior performance versus Si devices in both hard-switching and soft-switching converters. Due to the relatively higher switching-on loss compared with switching-off loss, zero voltage switching (ZVS) turn-on is still preferred to the application scope which efficiency is the primary design target. In this paper, the characteristics of GaN HEMTs under ZVS conditions is modeled. The packaging considerations on circuit parasitics and thermal management for soft switching applications is also discussed. An insulated metal substrate (IMS) based half-bridge power module consisting of two high-side and two low-side 650 V/60 A GaN HEMTs in parallel is designed and experimentally evaluated. A strong correlation is shown between simulations and experiments, verifying the power module design and GaN HEMTs' loss model.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341214
M. Antivachis, D. Bortis, L. Schrittwieser, J. Kolar
Driven by the needs of the continuously growing fuel-cell industry, a promising three-phase inverter topology, the Y-inverter, is proposed, which comprises three identical buck-boost DC/DC converter modules connected to a common star point. Each module constitutes a phase-leg and can be operated in similar fashion to conventional DC/DC converters, independent of the remaining two phases. Therefore, a straightforward and simple operation is possible. In addition, the Y-inverter allows for continuous output AC voltage waveforms, eliminating the need of additional AC-side filtering. Due to the buck-boost nature of each phase leg, the AC voltages can be higher or lower than the DC input voltage. This is an essential feature for fuel-cell applications, which suffer from a wide DC input voltage range. This paper details the operating principle of the Y-inverter, outlines the control system design and verifies its functionality by means of simulation results. The Y-inverter performance in terms of efficiency η and power density ρ is briefly analyzed by means of a multi-objective optimization and a converter design is selected which is compared to a benchmark system realized with a conventional inverter solution.
{"title":"Three-phase buck-boost Y-inverter with wide DC input voltage range","authors":"M. Antivachis, D. Bortis, L. Schrittwieser, J. Kolar","doi":"10.1109/APEC.2018.8341214","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341214","url":null,"abstract":"Driven by the needs of the continuously growing fuel-cell industry, a promising three-phase inverter topology, the Y-inverter, is proposed, which comprises three identical buck-boost DC/DC converter modules connected to a common star point. Each module constitutes a phase-leg and can be operated in similar fashion to conventional DC/DC converters, independent of the remaining two phases. Therefore, a straightforward and simple operation is possible. In addition, the Y-inverter allows for continuous output AC voltage waveforms, eliminating the need of additional AC-side filtering. Due to the buck-boost nature of each phase leg, the AC voltages can be higher or lower than the DC input voltage. This is an essential feature for fuel-cell applications, which suffer from a wide DC input voltage range. This paper details the operating principle of the Y-inverter, outlines the control system design and verifies its functionality by means of simulation results. The Y-inverter performance in terms of efficiency η and power density ρ is briefly analyzed by means of a multi-objective optimization and a converter design is selected which is compared to a benchmark system realized with a conventional inverter solution.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341284
Arvind H Kadam, Rishi Menon, S. Williamson
In the industrial production stage of a drive, its control algorithm must be tested for its validity with real machine. Testing with real machine could pose some serious challenges. During the testing, if the control algorithm starts behaving unexpectedly, it may cause serious damage to the real machine or drive. Such hazardous operating conditions can be avoided by replacing a real machine with a power electronic converter based ‘Virtual Machine’ (VM) test-bench. The VM can be designed to allow the device under test (DUT) to be tested at actual power with the help of a power electronic converter test setup and the motor model. The VM controls the current drawn from the DUT to match with that of estimated by the motor model. The existing VM system comprises of AC-DC followed by DC-AC converter, increasing the number of converter stages in the system. In addition, both the converters require independent control which increases the control complexity. This multistage conversion stage can be eliminated by replacing AC-DC-AC emulator with AC-DC converter supplied by common DC bus to DUT and VM both. Taking into account, this paper proposes a novel single-stage, three-phase bi-directional AC-DC converter topology suitable for VM system.
{"title":"A novel bidirectional three-phase AC-DC/DC-AC converter for PMSM virtual machine system with common DC bus","authors":"Arvind H Kadam, Rishi Menon, S. Williamson","doi":"10.1109/APEC.2018.8341284","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341284","url":null,"abstract":"In the industrial production stage of a drive, its control algorithm must be tested for its validity with real machine. Testing with real machine could pose some serious challenges. During the testing, if the control algorithm starts behaving unexpectedly, it may cause serious damage to the real machine or drive. Such hazardous operating conditions can be avoided by replacing a real machine with a power electronic converter based ‘Virtual Machine’ (VM) test-bench. The VM can be designed to allow the device under test (DUT) to be tested at actual power with the help of a power electronic converter test setup and the motor model. The VM controls the current drawn from the DUT to match with that of estimated by the motor model. The existing VM system comprises of AC-DC followed by DC-AC converter, increasing the number of converter stages in the system. In addition, both the converters require independent control which increases the control complexity. This multistage conversion stage can be eliminated by replacing AC-DC-AC emulator with AC-DC converter supplied by common DC bus to DUT and VM both. Taking into account, this paper proposes a novel single-stage, three-phase bi-directional AC-DC converter topology suitable for VM system.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341124
Ruoyu Hou, Juncheng Lu, Di Chen
Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) can achieve relatively high-efficiency and high-frequency in hard-switching mode. One particular reason is that GaN E-HEMTs obtain zero reverse-recovery loss and also a zero reverse-recovery period. For silicon (Si) MOSFETs, it has been a well-known issue that their Qrr is too big to switch the transistor in hard-switching mode. Researchers have made extensive efforts to calculate the reverse-recovery loss. However, few of them pay attention to the Qoss, as the Qrr dominates in the turn-on switching loss for Si MOSFETs. For GaN HEMTs, the absence of the Qrr makes the Qoss noticeable, although the value of the Qoss for GaN HEMTs is still the smallest among both Si and Silicon Carbide (SiC) MOSFETs. This paper focus on the Eqoss loss in GaN HEMTs. The Eqoss loss mechanism, detailed calculation and detailed measurement method for GaN HEMTs are provided. In addition, the theoretical results are verified by the double-pulse test at different junction temperatures and gate resistances.
{"title":"Parasitic capacitance Eqoss loss mechanism, calculation, and measurement in hard-switching for GaN HEMTs","authors":"Ruoyu Hou, Juncheng Lu, Di Chen","doi":"10.1109/APEC.2018.8341124","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341124","url":null,"abstract":"Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) can achieve relatively high-efficiency and high-frequency in hard-switching mode. One particular reason is that GaN E-HEMTs obtain zero reverse-recovery loss and also a zero reverse-recovery period. For silicon (Si) MOSFETs, it has been a well-known issue that their Qrr is too big to switch the transistor in hard-switching mode. Researchers have made extensive efforts to calculate the reverse-recovery loss. However, few of them pay attention to the Qoss, as the Qrr dominates in the turn-on switching loss for Si MOSFETs. For GaN HEMTs, the absence of the Qrr makes the Qoss noticeable, although the value of the Qoss for GaN HEMTs is still the smallest among both Si and Silicon Carbide (SiC) MOSFETs. This paper focus on the Eqoss loss in GaN HEMTs. The Eqoss loss mechanism, detailed calculation and detailed measurement method for GaN HEMTs are provided. In addition, the theoretical results are verified by the double-pulse test at different junction temperatures and gate resistances.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124738738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-04DOI: 10.1109/APEC.2018.8341023
J. Müting, Nick Schneider, T. Ziemann, R. Stark, U. Grossner
In order to investigate the performance of SiC power MOSFETs and especially their applicability for parallelization, ten samples of Cree's C2M0080120D MOSFET are investigated in terms of their electrical and thermal behavior. A significant spread of on-state resistance and threshold voltage is observed, where the maximum differences are ΔI ≈ 10 mΩ, i.e. 12.5 % at a current of 20 A, and ΔVth ≈ 1 V, respectively. The parallelization of these devices is analyzed by developing a numerically efficient and semi-physical Spice model for the given MOSFET. Circuit simulations of ten paralleled devices show a maximum imbalance in current of 13 % and a maximum imbalance in junction to case temperature of around 11 % between the devices. The turn-on losses increase by 2 % while the turn-off losses remain unchanged compared to ten parallel devices with similar, averaged on-resistance. Applying these ten parallel MOSFETs with different characteristics to a 50 kW bi-directional DC/DC converter in boost mode increases the losses by 46 W in comparison to ten identical MOSFETs with averaged characteristics.
{"title":"Exploring the behavior of parallel connected SiC power MOSFETs influenced by performance spread in circuit simulations","authors":"J. Müting, Nick Schneider, T. Ziemann, R. Stark, U. Grossner","doi":"10.1109/APEC.2018.8341023","DOIUrl":"https://doi.org/10.1109/APEC.2018.8341023","url":null,"abstract":"In order to investigate the performance of SiC power MOSFETs and especially their applicability for parallelization, ten samples of Cree's C2M0080120D MOSFET are investigated in terms of their electrical and thermal behavior. A significant spread of on-state resistance and threshold voltage is observed, where the maximum differences are ΔI ≈ 10 mΩ, i.e. 12.5 % at a current of 20 A, and ΔVth ≈ 1 V, respectively. The parallelization of these devices is analyzed by developing a numerically efficient and semi-physical Spice model for the given MOSFET. Circuit simulations of ten paralleled devices show a maximum imbalance in current of 13 % and a maximum imbalance in junction to case temperature of around 11 % between the devices. The turn-on losses increase by 2 % while the turn-off losses remain unchanged compared to ten parallel devices with similar, averaged on-resistance. Applying these ten parallel MOSFETs with different characteristics to a 50 kW bi-directional DC/DC converter in boost mode increases the losses by 46 W in comparison to ten identical MOSFETs with averaged characteristics.","PeriodicalId":113756,"journal":{"name":"2018 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"360 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126695546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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