Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027683
Jaeduk Han, Eric Y. Chang, E. Alon
This paper introduces key techniques to implement high-speed wireline transceivers presented in [1]–[3]. The frontend equalizers operate at high frequencies by employing energy-efficient current integration and resonant clocking techniques. The baud-rate clock-and-data-recovery (CDR) is implemented to reduce the number of samplers and clock phases for the CDR operation. In addition to the design techniques, the generator-based design methodology [4] [5] is utilized to extremely optimize the sizing parameters of critical circuits by automatically generating their layouts and capturing the layout dependent effects. Two representative design examples that used the proposed techniques achieved 60 Gb/s and 15 Gb/s respectively, which demonstrate their effectiveness to achieve such high data-rates with excellent energy efficiencies.
{"title":"Design and Automatic Generation of High-Speed Circuits for Wireline Communications","authors":"Jaeduk Han, Eric Y. Chang, E. Alon","doi":"10.1109/ISOCC47750.2019.9027683","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027683","url":null,"abstract":"This paper introduces key techniques to implement high-speed wireline transceivers presented in [1]–[3]. The frontend equalizers operate at high frequencies by employing energy-efficient current integration and resonant clocking techniques. The baud-rate clock-and-data-recovery (CDR) is implemented to reduce the number of samplers and clock phases for the CDR operation. In addition to the design techniques, the generator-based design methodology [4] [5] is utilized to extremely optimize the sizing parameters of critical circuits by automatically generating their layouts and capturing the layout dependent effects. Two representative design examples that used the proposed techniques achieved 60 Gb/s and 15 Gb/s respectively, which demonstrate their effectiveness to achieve such high data-rates with excellent energy efficiencies.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"98 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128350879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027630
Hyunsung Kim, J. Lim, W. Hong, Joonho Park, Young-Seok Kim, Mijung Kim, Youngjoo Lee
This paper presents a prototype wearable device that tracks movements of football players during the match time. To analyze the performance of each player, the proposed device uses the global navigation satellite system (GNSS) assisted by the inertial measurement unit (IMU). Several algorithms are realized on the embedded processor to estimate the amount of speed, total distance covered, and inertia. In addition, the Bluetooth Low Energy (BLE) protocol is used to transfer acquired data from the pitch while reducing the overall power consumption. Experimental results show that the BLE-based wearable device successfully demonstrates the real-time tracking operation, achieving the low-power solution compared to the existing devices.
{"title":"Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players","authors":"Hyunsung Kim, J. Lim, W. Hong, Joonho Park, Young-Seok Kim, Mijung Kim, Youngjoo Lee","doi":"10.1109/ISOCC47750.2019.9027630","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027630","url":null,"abstract":"This paper presents a prototype wearable device that tracks movements of football players during the match time. To analyze the performance of each player, the proposed device uses the global navigation satellite system (GNSS) assisted by the inertial measurement unit (IMU). Several algorithms are realized on the embedded processor to estimate the amount of speed, total distance covered, and inertia. In addition, the Bluetooth Low Energy (BLE) protocol is used to transfer acquired data from the pitch while reducing the overall power consumption. Experimental results show that the BLE-based wearable device successfully demonstrates the real-time tracking operation, achieving the low-power solution compared to the existing devices.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130684140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027681
Eunseok Lee, Sujin Park, Nahmil Koo, Seonghwan Cho
In this paper, we propose a low-power piezoelectric speaker driver for acoustic communication based on on-off keying modulation. To reduce the dynamic power consumed to drive the capacitive speaker, the proposed driver is implemented using an LC oscillator. A proof-of-concept prototype is implemented using off-chip components, and experimental results show that the proposed LC oscillator based on-off keying reduces the power consumption by nearly 50 % compared to a conventional driver.
{"title":"A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication","authors":"Eunseok Lee, Sujin Park, Nahmil Koo, Seonghwan Cho","doi":"10.1109/ISOCC47750.2019.9027681","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027681","url":null,"abstract":"In this paper, we propose a low-power piezoelectric speaker driver for acoustic communication based on on-off keying modulation. To reduce the dynamic power consumed to drive the capacitive speaker, the proposed driver is implemented using an LC oscillator. A proof-of-concept prototype is implemented using off-chip components, and experimental results show that the proposed LC oscillator based on-off keying reduces the power consumption by nearly 50 % compared to a conventional driver.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125418295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027698
Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim
The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (cd) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance gd (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, Cvar(V) (voltage-controlled capacitance), is added to minimize cd(equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and cdbecause the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.
{"title":"Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation","authors":"Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC47750.2019.9027698","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027698","url":null,"abstract":"The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (cd) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance gd (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, Cvar(V) (voltage-controlled capacitance), is added to minimize cd(equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and cdbecause the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027650
Sanghyuk Lee, Jaehoon Cha, Kyeong Soo Kim
Building energy optimization has much related with energy saving and building maintenance viewpoint as well. First we face with building modelling problem. Then it is naturally followed the issue by how exact or how efficient it is. Generally, analytical approach meets rather complex and complicate to express with exactly. Hence, we normally design the system model with possible and accessible input/output data with IoT sensor. That is Neural Network (NN), and it has been focused nowadays. In this paper, we will focus on the building modelling with NN based on input and output data such as temperature, working days, humidity, weather characteristics and electrical consumption for IoT applications. Modelling verification will be followed with test data, and performance also evaluated.
{"title":"Data Gathering and Application to Building Energy Optimization with Sensitivity Analysis for IoT Applications","authors":"Sanghyuk Lee, Jaehoon Cha, Kyeong Soo Kim","doi":"10.1109/ISOCC47750.2019.9027650","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027650","url":null,"abstract":"Building energy optimization has much related with energy saving and building maintenance viewpoint as well. First we face with building modelling problem. Then it is naturally followed the issue by how exact or how efficient it is. Generally, analytical approach meets rather complex and complicate to express with exactly. Hence, we normally design the system model with possible and accessible input/output data with IoT sensor. That is Neural Network (NN), and it has been focused nowadays. In this paper, we will focus on the building modelling with NN based on input and output data such as temperature, working days, humidity, weather characteristics and electrical consumption for IoT applications. Modelling verification will be followed with test data, and performance also evaluated.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114284068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027696
Zelin Meng, Xiangbo Kong, Lin Meng, Hiroyuki Tomiyama
This paper presents an alternative of our previously proposed lightweight camera motion estimation method based on descriptor matching. First, based on the FAST feature and Lucas-Kanade Optical flow approach, we obtain tracked feature point pairs of two frames of input image. Secondly, according to the obtained pixel coordinates of the tracking point pairs, the motion of the camera can be estimated by the epipolar geometry method. The experiment results indicate that our proposed work can provide a 25% improvement in time-efficiency relative to our previous work. So that it can have higher suitability and possibility of implementation in low-power computing platforms.
{"title":"Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach","authors":"Zelin Meng, Xiangbo Kong, Lin Meng, Hiroyuki Tomiyama","doi":"10.1109/ISOCC47750.2019.9027696","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027696","url":null,"abstract":"This paper presents an alternative of our previously proposed lightweight camera motion estimation method based on descriptor matching. First, based on the FAST feature and Lucas-Kanade Optical flow approach, we obtain tracked feature point pairs of two frames of input image. Secondly, according to the obtained pixel coordinates of the tracking point pairs, the motion of the camera can be estimated by the epipolar geometry method. The experiment results indicate that our proposed work can provide a 25% improvement in time-efficiency relative to our previous work. So that it can have higher suitability and possibility of implementation in low-power computing platforms.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124310726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027711
Tatsuya Maekawa, Y. Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura
The proposed architecture estimates the pre-emphasis weighting of the transmitter from the waveform monitor in the receiver. This weighting data is stored on the memory, and it makes a quick response to packet data. We evaluated the proposed circuit with a field programmable gate array (FPGA), and it achieved good eye openings with high-speed response for wide degradation conditions.
{"title":"Tunable pre-emphasis architecture for downstream data in long-haul PON systems","authors":"Tatsuya Maekawa, Y. Miwa, Akihito Uno, Daisuke Ito, Makoto Nakamura","doi":"10.1109/ISOCC47750.2019.9027711","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027711","url":null,"abstract":"The proposed architecture estimates the pre-emphasis weighting of the transmitter from the waveform monitor in the receiver. This weighting data is stored on the memory, and it makes a quick response to packet data. We evaluated the proposed circuit with a field programmable gate array (FPGA), and it achieved good eye openings with high-speed response for wide degradation conditions.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027762
Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.
{"title":"Area Efficient Multi-Threshold Null Convenction Logic","authors":"Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC47750.2019.9027762","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027762","url":null,"abstract":"Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129570940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027710
Y. Uwate, Y. Nishio
It is well known that burst patterns within neurons may have some important role for operating information processing in a brain. However, the analysis of judgement of synchronization and correlation between burst patterns is not so easy. Therefore, we have proposed a visualization method of bursting patterns of whole neural network using nonlinear time series analysis. Additionally, we consider that it is required to construct a model using mathematical neuron model producing burst patterns, because it is difficult to obtain real biological neuron data. In this study, we propose a visualization method of network characteristics of FitzHu-Nagumo (FHN) neuron model using nonlinear time-series analysis.
{"title":"Nonlinear Time Series Analysis of Coupled Bursting Neuron Model Depending on Coupling Strength","authors":"Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC47750.2019.9027710","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027710","url":null,"abstract":"It is well known that burst patterns within neurons may have some important role for operating information processing in a brain. However, the analysis of judgement of synchronization and correlation between burst patterns is not so easy. Therefore, we have proposed a visualization method of bursting patterns of whole neural network using nonlinear time series analysis. Additionally, we consider that it is required to construct a model using mathematical neuron model producing burst patterns, because it is difficult to obtain real biological neuron data. In this study, we propose a visualization method of network characteristics of FitzHu-Nagumo (FHN) neuron model using nonlinear time-series analysis.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129856009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027721
Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Hi-Seok Kim
Most of the marker-based watershed methods require manual selecting the markers which need human interaction. We propose a new automatic markers generation method for the marker-based watershed algorithm. This algorithm uses Otsu's threshold information for generating markers. The proposed method is tested on the infrared images and we have obtained satisfactory results.
{"title":"Marker-based watershed algorithm for segmentation of the infrared images","authors":"Manikanta Prahlad Manda, Chan Su Park, ByeongCheol Oh, Hi-Seok Kim","doi":"10.1109/ISOCC47750.2019.9027721","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027721","url":null,"abstract":"Most of the marker-based watershed methods require manual selecting the markers which need human interaction. We propose a new automatic markers generation method for the marker-based watershed algorithm. This algorithm uses Otsu's threshold information for generating markers. The proposed method is tested on the infrared images and we have obtained satisfactory results.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128786544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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