Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078463
W. Ki, Lin Cheng, Xinyuan Ge, C. Tsui
By modeling the LC tank of a wireless receiver as an AC current source that serves as the input, the H-bridge built with four power transistors can be switched to work in 1X, ½X and 0X modes to realize rectification and constant-current and constant-voltage charging, thus resulting in a single-stage wireless charger; and for low charging current, a ½X - 0X single-stage charger only needs three power switches.
{"title":"Single-Stage Rectifying Constant-Current Constant-Voltage Charger for Wireless Charging","authors":"W. Ki, Lin Cheng, Xinyuan Ge, C. Tsui","doi":"10.1109/ISOCC47750.2019.9078463","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078463","url":null,"abstract":"By modeling the LC tank of a wireless receiver as an AC current source that serves as the input, the H-bridge built with four power transistors can be switched to work in 1X, ½X and 0X modes to realize rectification and constant-current and constant-voltage charging, thus resulting in a single-stage wireless charger; and for low charging current, a ½X - 0X single-stage charger only needs three power switches.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078493
Seung Chan Lee, T. Han
With the rapid growth of modern applications based on machine learning, neural network (NN) algorithm has been widely used in various fields. Accordingly, machine learning accelerators with high performance based on FPGA and ASIC design have become necessary. Machine learning accelerators generally include a matrix multiply unit that performs arithmetic. However, despite the development of dedicated hardware, some NN algorithms still suffer from performance degradation due to computation bounds in the matrix multiply units. Resolving the computation bound is crucial for high throughput machine learning accelerator. In this paper, we propose a 4-way matrix unit to resolve the computation bound by minimizing idle state operation logic and improving overall utilization. A 4-way matrix multiply unit resulted in an average throughput improvement of 29 percent and a 24 percent increase in the total area, comparing to the conventional systolic array-based matrix multiply unit.
{"title":"A 4-way Matrix Multiply Unit for High Throughput Machine Learning Accelerator","authors":"Seung Chan Lee, T. Han","doi":"10.1109/ISOCC47750.2019.9078493","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078493","url":null,"abstract":"With the rapid growth of modern applications based on machine learning, neural network (NN) algorithm has been widely used in various fields. Accordingly, machine learning accelerators with high performance based on FPGA and ASIC design have become necessary. Machine learning accelerators generally include a matrix multiply unit that performs arithmetic. However, despite the development of dedicated hardware, some NN algorithms still suffer from performance degradation due to computation bounds in the matrix multiply units. Resolving the computation bound is crucial for high throughput machine learning accelerator. In this paper, we propose a 4-way matrix unit to resolve the computation bound by minimizing idle state operation logic and improving overall utilization. A 4-way matrix multiply unit resulted in an average throughput improvement of 29 percent and a 24 percent increase in the total area, comparing to the conventional systolic array-based matrix multiply unit.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130296296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078523
Chia-Chun Tsai
In this paper, we proposed an algorithm to improve the bus performance by reconstructing a stacked-layer data bus. The algorithm always tries to insert repeaters into the current critical path of a data access for isolating their extra capacitive loadings and sizes their repeaters for minimizing the critical access time on a complete timing period. The above process is repeated until no any improvement in the critical access time. Finally, each access time and the average access time can be dramatically decreased and the bus performance thus be upgraded. Experimental results show that our performance improvement for a stacked-layer data bus on a complete timing period has up to 49.15% in average access time on average and has 17.95% better than other approaches.
{"title":"Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period","authors":"Chia-Chun Tsai","doi":"10.1109/ISOCC47750.2019.9078523","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078523","url":null,"abstract":"In this paper, we proposed an algorithm to improve the bus performance by reconstructing a stacked-layer data bus. The algorithm always tries to insert repeaters into the current critical path of a data access for isolating their extra capacitive loadings and sizes their repeaters for minimizing the critical access time on a complete timing period. The above process is repeated until no any improvement in the critical access time. Finally, each access time and the average access time can be dramatically decreased and the bus performance thus be upgraded. Experimental results show that our performance improvement for a stacked-layer data bus on a complete timing period has up to 49.15% in average access time on average and has 17.95% better than other approaches.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078511
Sodam Han, Yonghee Yun, Young Hwan Kim
In this research, we demonstrate the fundamental inefficiency of the asymmetric multicore architecture in modern mobile CPUs, and propose two principles for the effective utilization of the asymmetric characteristics of modern mobile CPUs; power-efficient cluster with sufficient performance and high-speed cluster with reasonable performance. In the experimental study, the proposed principles reduced the energy consumption up to 37% while not harming system performance. The experimental results demonstrate that the proposed principles can be used to improve the power efficiency while not harming QoS.
{"title":"Effective Uilitzation of Modern Mobile CPU's Asymmetric Characteristics","authors":"Sodam Han, Yonghee Yun, Young Hwan Kim","doi":"10.1109/ISOCC47750.2019.9078511","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078511","url":null,"abstract":"In this research, we demonstrate the fundamental inefficiency of the asymmetric multicore architecture in modern mobile CPUs, and propose two principles for the effective utilization of the asymmetric characteristics of modern mobile CPUs; power-efficient cluster with sufficient performance and high-speed cluster with reasonable performance. In the experimental study, the proposed principles reduced the energy consumption up to 37% while not harming system performance. The experimental results demonstrate that the proposed principles can be used to improve the power efficiency while not harming QoS.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078517
Hyeonchan Lim, Seokjun Jang, Seunghwan Kim, Sungho Kang
Scan-based test and diagnosis are important for improving yield of nanometer-scale chips. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method is proposed for not only stuck-at fault but also transition fault. The proposed method is implemented simply and provides maximum diagnosis resolution for stuck-at and transition faults.
{"title":"An Efficient Scan Chain Diagnosis for Stuck-at and Transition Faults","authors":"Hyeonchan Lim, Seokjun Jang, Seunghwan Kim, Sungho Kang","doi":"10.1109/ISOCC47750.2019.9078517","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078517","url":null,"abstract":"Scan-based test and diagnosis are important for improving yield of nanometer-scale chips. However, the scan chain can be subject to defects due to large hardware incurred by itself, which accounts for considerable portion of total chip area. Hence, scan chain test and diagnosis has played a critical role in recent years. In this paper, an efficient scan chain diagnosis method is proposed for not only stuck-at fault but also transition fault. The proposed method is implemented simply and provides maximum diagnosis resolution for stuck-at and transition faults.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124833579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/isocc47750.2019.9027737
Farid Feyzi, Saeed Parsa
In this paper, a novel approach, Inforence, is proposed to isolate the suspicious codes that likely contain faults. Inforence employs a feature selection method, based on mutual information, to identify those bug-related statements that may cause the program to fail. Because the majority of a program faults may be revealed as undesired joint effect of the program statements on each other and on program termination state, unlike the state-of-the-art methods, Inforence tries to identify and select groups of interdependent statements which altogether may affect the program failure. The interdependence amongst the statements is measured according to their mutual effect on each other and on the program termination state. To provide the context of failure, the selected bug-related statements are chained to each other, considering the program static structure. Eventually, the resultant cause-effect chains are ranked according to their combined causal effect on program failure. To validate Inforence, the results of our experiments with seven sets of programs include Siemens suite, gzip, grep, sed, space, make and bash are presented. The experimental results are then compared with those provided by different fault localization techniques for the both single-fault and multi-fault programs. The experimental results prove the outperformance of the proposed method compared to the state-of-the-art techniques.
{"title":"Front","authors":"Farid Feyzi, Saeed Parsa","doi":"10.1109/isocc47750.2019.9027737","DOIUrl":"https://doi.org/10.1109/isocc47750.2019.9027737","url":null,"abstract":"In this paper, a novel approach, Inforence, is proposed to isolate the suspicious codes that likely contain faults. Inforence employs a feature selection method, based on mutual information, to identify those bug-related statements that may cause the program to fail. Because the majority of a program faults may be revealed as undesired joint effect of the program statements on each other and on program termination state, unlike the state-of-the-art methods, Inforence tries to identify and select groups of interdependent statements which altogether may affect the program failure. The interdependence amongst the statements is measured according to their mutual effect on each other and on the program termination state. To provide the context of failure, the selected bug-related statements are chained to each other, considering the program static structure. Eventually, the resultant cause-effect chains are ranked according to their combined causal effect on program failure. To validate Inforence, the results of our experiments with seven sets of programs include Siemens suite, gzip, grep, sed, space, make and bash are presented. The experimental results are then compared with those provided by different fault localization techniques for the both single-fault and multi-fault programs. The experimental results prove the outperformance of the proposed method compared to the state-of-the-art techniques.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128422050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078501
Muhammad Asif, Imran Ali, Y. Qaragoez, Muhammad Basim, Kangyoon Lee
In this paper, a configurable linear ramp controller (CLRC) for power amplifier (PA) is proposed. It changes PA core size linearly for amplitude shift keying (ASK) modulation and improves PA power controllability. The configurable ramping reduces harmonics and spurious in PA output power spectrum and improves PA performance. The proposed controller uses standard cells for the unit delay and it is fully synthesizable. The ramping step size is configurable between 0.2 ns to 0.7 ns. It needs 51.73 K gate counts for its implementation. The design consumes 863 μW power and draws 719 μA current from 1.2 V supply. The proposed controller is integrated into DSRC transceiver and is implemented in 130 nm CMOS technology. It occupies 314 μm × 314 μm of chip area.
{"title":"A Configurable Linear PA Ramp Controller for DSRC Applications in 130 nm CMOS Technology","authors":"Muhammad Asif, Imran Ali, Y. Qaragoez, Muhammad Basim, Kangyoon Lee","doi":"10.1109/ISOCC47750.2019.9078501","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078501","url":null,"abstract":"In this paper, a configurable linear ramp controller (CLRC) for power amplifier (PA) is proposed. It changes PA core size linearly for amplitude shift keying (ASK) modulation and improves PA power controllability. The configurable ramping reduces harmonics and spurious in PA output power spectrum and improves PA performance. The proposed controller uses standard cells for the unit delay and it is fully synthesizable. The ramping step size is configurable between 0.2 ns to 0.7 ns. It needs 51.73 K gate counts for its implementation. The design consumes 863 μW power and draws 719 μA current from 1.2 V supply. The proposed controller is integrated into DSRC transceiver and is implemented in 130 nm CMOS technology. It occupies 314 μm × 314 μm of chip area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131133989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078525
Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee
Virtual SoC platforms can shorten development time of embedded systems by enabling to develop embedded software before FPGA prototypes or SoCs are given. However, virtual platforms have a limitation in the development of sensor applications because they cannot emulate external hardware modules. Thus in this paper, we propose a virtual SoC platform that supports serial interfaces where actual sensors can be used for emulating applications. The proposed platform is implemented by integrating USBtoSerial modules with QEMU. We verify the functional correctness by comparing the results of a sensor application on the proposed virtual platform, FPGA prototype, and actual SoC.
{"title":"Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications","authors":"Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee","doi":"10.1109/ISOCC47750.2019.9078525","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078525","url":null,"abstract":"Virtual SoC platforms can shorten development time of embedded systems by enabling to develop embedded software before FPGA prototypes or SoCs are given. However, virtual platforms have a limitation in the development of sensor applications because they cannot emulate external hardware modules. Thus in this paper, we propose a virtual SoC platform that supports serial interfaces where actual sensors can be used for emulating applications. The proposed platform is implemented by integrating USBtoSerial modules with QEMU. We verify the functional correctness by comparing the results of a sensor application on the proposed virtual platform, FPGA prototype, and actual SoC.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131286674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078492
Sunghye Park, Sunmean Kim, Seokhyeong Kang
Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5- trit ternary adder-subtractor and ternary multiplier, respectively.
{"title":"Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU","authors":"Sunghye Park, Sunmean Kim, Seokhyeong Kang","doi":"10.1109/ISOCC47750.2019.9078492","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078492","url":null,"abstract":"Ternary logic circuits can provide simpler circuit structure and a significant reduction in power consumption via reduced interconnects. We propose a signed ternary arithmetic logic unit (ALU) which is designed with multi-threshold voltages graphene barristors. We simulated the ternary logic circuits using SPICE model of an experimentally proven multi-threshold voltages graphene barristor. Our proposed ternary ALU demonstrates improved energy-efficiency compared to the binary design; 87% and 93% reduction of power-delay product in the 5- trit ternary adder-subtractor and ternary multiplier, respectively.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130094077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078505
Seonyoung Lee, Haengson Son, Yunjeong Kim, Kyoungwon Min
Applications such as automobiles, robots and games require a real-time operation in embedded systems. However, since the accurate hand gesture recognition requires a large amount of computation, it is difficult a real-time operation. In this paper, we propose a hand skeleton extraction accelerator for real-time hand gesture recognition. We analyze the hand gesture recognition algorithm to find the parts with high computational complexity and determine which routines that are difficult a real-time operation. And the hardware accelerator is implemented using HLS method for embedded system. Implemented hand skeleton extraction accelerator circuit was tested its operation using Xilinx’s Zynq-7000 FPGA (XC7Z020) device. Our circuit operates in real-time in an embedded system and recognition success rates is 86.8%.
{"title":"Design of hand skeleton extraction accelerator for a real-time hand gesture recognition","authors":"Seonyoung Lee, Haengson Son, Yunjeong Kim, Kyoungwon Min","doi":"10.1109/ISOCC47750.2019.9078505","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078505","url":null,"abstract":"Applications such as automobiles, robots and games require a real-time operation in embedded systems. However, since the accurate hand gesture recognition requires a large amount of computation, it is difficult a real-time operation. In this paper, we propose a hand skeleton extraction accelerator for real-time hand gesture recognition. We analyze the hand gesture recognition algorithm to find the parts with high computational complexity and determine which routines that are difficult a real-time operation. And the hardware accelerator is implemented using HLS method for embedded system. Implemented hand skeleton extraction accelerator circuit was tested its operation using Xilinx’s Zynq-7000 FPGA (XC7Z020) device. Our circuit operates in real-time in an embedded system and recognition success rates is 86.8%.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127154478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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