Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078526
Jaeseong Park, Y. Lee, Junho Heo, Suk-ju Kang
In this paper, we propose a novel system to generate jaywalking images. To synthesize a pedestrian on the road and label the binary case such as jaywalk or normal-walk, the pre-trained Convolutional Neural Network (CNN) is used to segment the drivable area from the large-scale dataset. The proposed system automatically generates a jaywalker based on existing pedestrian objects in the image. The proposed system performs three main steps. First, we train the existing network with both black box image dataset and object dataset to segment road areas and pedestrians. Second, the generator synthesizes jaywalkers randomly within the road segmentation masks. Third, a CNN classifier is trained using the generated synthetic dataset and performs the inference from natural jaywalking images. The experiment results show that the jaywalking classifier trained with both generated synthetic dataset and the untouched natural dataset has a high accuracy of 0.96, which is 0.08 higher than the accuracy using only the untouched natural dataset on the same model.
{"title":"Convolutional Neural Network-based Jaywalking Data Generation and Classification","authors":"Jaeseong Park, Y. Lee, Junho Heo, Suk-ju Kang","doi":"10.1109/ISOCC47750.2019.9078526","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078526","url":null,"abstract":"In this paper, we propose a novel system to generate jaywalking images. To synthesize a pedestrian on the road and label the binary case such as jaywalk or normal-walk, the pre-trained Convolutional Neural Network (CNN) is used to segment the drivable area from the large-scale dataset. The proposed system automatically generates a jaywalker based on existing pedestrian objects in the image. The proposed system performs three main steps. First, we train the existing network with both black box image dataset and object dataset to segment road areas and pedestrians. Second, the generator synthesizes jaywalkers randomly within the road segmentation masks. Third, a CNN classifier is trained using the generated synthetic dataset and performs the inference from natural jaywalking images. The experiment results show that the jaywalking classifier trained with both generated synthetic dataset and the untouched natural dataset has a high accuracy of 0.96, which is 0.08 higher than the accuracy using only the untouched natural dataset on the same model.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129902602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078524
Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang
Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.
{"title":"Transition-delay Test Methodology for Designs with Self-gating","authors":"Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang","doi":"10.1109/ISOCC47750.2019.9078524","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078524","url":null,"abstract":"Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078503
Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang
With the development of memory density and capacity, a redundancy analysis (RA) is widely used to improve memory yield. However, as the probability of fault occurrence on memory increases, repair rates of conventional RAs with a simple spare structure have been not enough to achieve a high memory yield. In this paper, redundancy analysis based on fault distribution (RAFD) for memory with complex spares is proposed to address the problem. It can obtain much higher repair rate than using conventional RAs with a simple spare structure by using complex spares. Also, although use of complex spares can cause analysis time increase but, RAFD solves the problem with the sequential spare allocations through consideration of fault distribution.
{"title":"Redundancy Analysis based on Fault Distribution for Memory with Complex Spares","authors":"Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang","doi":"10.1109/ISOCC47750.2019.9078503","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078503","url":null,"abstract":"With the development of memory density and capacity, a redundancy analysis (RA) is widely used to improve memory yield. However, as the probability of fault occurrence on memory increases, repair rates of conventional RAs with a simple spare structure have been not enough to achieve a high memory yield. In this paper, redundancy analysis based on fault distribution (RAFD) for memory with complex spares is proposed to address the problem. It can obtain much higher repair rate than using conventional RAs with a simple spare structure by using complex spares. Also, although use of complex spares can cause analysis time increase but, RAFD solves the problem with the sequential spare allocations through consideration of fault distribution.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124112314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078497
Sangwoo Jung, J. Kung
In this paper, we perform the noise analysis on an energy-scalable deep learning model with two extreme bit-precisions, named MixNet. In real-world applications, there might be a great deal of noisy inputs that are collected from mobile sensors, and the training is performed on those noisy datasets. According to our initial set of experiments, MixNet has lower sensitivity to the noise in the training dataset, when compared to the original CNN model with high-precision. As a result, it is expected that the MixNet can be trained better even in a noisy environment than the original high-precision deep learning models.
{"title":"Noise Tolerance of an Energy-Scalable Deep Learning Model with Two Extreme Bit-Precisions","authors":"Sangwoo Jung, J. Kung","doi":"10.1109/ISOCC47750.2019.9078497","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078497","url":null,"abstract":"In this paper, we perform the noise analysis on an energy-scalable deep learning model with two extreme bit-precisions, named MixNet. In real-world applications, there might be a great deal of noisy inputs that are collected from mobile sensors, and the training is performed on those noisy datasets. According to our initial set of experiments, MixNet has lower sensitivity to the noise in the training dataset, when compared to the original CNN model with high-precision. As a result, it is expected that the MixNet can be trained better even in a noisy environment than the original high-precision deep learning models.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117035592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027634
Ghil-geun Oh, Jong-Ho Eun, Shin-Young Chung, Brandon Lee
This paper introduces an effective design debugging and verification method using optical fault isolation (OFI) techniques. Although OFI is mainly used for failure analysis of semiconductor, key concepts of OFI techniques can be enlarged for circuit analysis of a real chip. Circuit analysis results on device skew of digital logic and pulse rejection filter of MIPI D-PHY core show that it is a very effective method to apply OFI to design verification at the early phase of production.
{"title":"Advanded Design Verification and Debugging Techniques Based on Optical Fault Isolation Method","authors":"Ghil-geun Oh, Jong-Ho Eun, Shin-Young Chung, Brandon Lee","doi":"10.1109/ISOCC47750.2019.9027634","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027634","url":null,"abstract":"This paper introduces an effective design debugging and verification method using optical fault isolation (OFI) techniques. Although OFI is mainly used for failure analysis of semiconductor, key concepts of OFI techniques can be enlarged for circuit analysis of a real chip. Circuit analysis results on device skew of digital logic and pulse rejection filter of MIPI D-PHY core show that it is a very effective method to apply OFI to design verification at the early phase of production.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122403050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027708
T. Tsai, Ping-Cheng Hao
In this paper, a customized wake-up word system combined with key word spotting using neural network was proposed. This system is divided into three phases: training wake-up word phase, detecting wake-up word phase and key word spotting phase. In training phase, user can say any word in any language and system will automatically count how many syllable of this word. If several syllables are in the range, system will accept this customized wake-up word. Next, the word will be extracted the features by Mel-Frequency Cepstral Coefficients (MFCC) method. It can be used for speaker model, speech model and state sequence for next phase. In detecting phase, system detects an unknown voice segment and compares it with models. After these steps, system will determine to wake up or not. If user says the right wake-up word, system goes to next phase. In key word spotting phase, the command words are fixed. The system is designed using convolutional neural network for key word spotting model. Moreover, all processes are executed without Internet to protect user privacy. This system can give a good result with a very small amount of wake-up word training data, and run in real-time.
{"title":"Customized Wake-Up Word with Key Word Spotting using Convolutional Neural Network","authors":"T. Tsai, Ping-Cheng Hao","doi":"10.1109/ISOCC47750.2019.9027708","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027708","url":null,"abstract":"In this paper, a customized wake-up word system combined with key word spotting using neural network was proposed. This system is divided into three phases: training wake-up word phase, detecting wake-up word phase and key word spotting phase. In training phase, user can say any word in any language and system will automatically count how many syllable of this word. If several syllables are in the range, system will accept this customized wake-up word. Next, the word will be extracted the features by Mel-Frequency Cepstral Coefficients (MFCC) method. It can be used for speaker model, speech model and state sequence for next phase. In detecting phase, system detects an unknown voice segment and compares it with models. After these steps, system will determine to wake up or not. If user says the right wake-up word, system goes to next phase. In key word spotting phase, the command words are fixed. The system is designed using convolutional neural network for key word spotting model. Moreover, all processes are executed without Internet to protect user privacy. This system can give a good result with a very small amount of wake-up word training data, and run in real-time.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123886742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027761
Tso-Bing Juang, C. Lin, Guan-Zhong Lin
In this work, high-speed and area-efficient rectangle to polar coordinate converters are proposed. By adopting logarithmic number system (LNS)-based implementations, tremendous and time-consuming operations for obtaining the values of radius and angles from given values of Cartesian coordinates can be easily simplified and implemented. Simulation results show that our proposed design can achieve area-delay efficient than conventional designs with tolerable errors. The proposed converters can be applied in real-time signal processing applications.
{"title":"Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems","authors":"Tso-Bing Juang, C. Lin, Guan-Zhong Lin","doi":"10.1109/ISOCC47750.2019.9027761","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027761","url":null,"abstract":"In this work, high-speed and area-efficient rectangle to polar coordinate converters are proposed. By adopting logarithmic number system (LNS)-based implementations, tremendous and time-consuming operations for obtaining the values of radius and angles from given values of Cartesian coordinates can be easily simplified and implemented. Simulation results show that our proposed design can achieve area-delay efficient than conventional designs with tolerable errors. The proposed converters can be applied in real-time signal processing applications.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124246379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027758
Wan-Ling Wu, Yong-Zheng Wang, Ching-Yuan Yang
Piezoelectric is a vibration source which can generate energy out of ambient vibrations. Four approaches of energy harvesting circuits in 0.35-µm CMOS process are discussed in the paper, including 1) the full bridge rectifier (FBR), 2) the switch only rectifier (SOR), 3) the parallel-synchronized-switch harvesting-on-inductor (P-SSHI), and 4) the flipping-capacitor rectifier (FCR). Compared to the transferred-power ability of the conventional FBR, the improved factors of SOR, P-SSHI and FCR can reach up to 1.58x, 1.93x and 1.96x at an excitation frequency of 100 Hz, respectively.
{"title":"Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting","authors":"Wan-Ling Wu, Yong-Zheng Wang, Ching-Yuan Yang","doi":"10.1109/ISOCC47750.2019.9027758","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027758","url":null,"abstract":"Piezoelectric is a vibration source which can generate energy out of ambient vibrations. Four approaches of energy harvesting circuits in 0.35-µm CMOS process are discussed in the paper, including 1) the full bridge rectifier (FBR), 2) the switch only rectifier (SOR), 3) the parallel-synchronized-switch harvesting-on-inductor (P-SSHI), and 4) the flipping-capacitor rectifier (FCR). Compared to the transferred-power ability of the conventional FBR, the improved factors of SOR, P-SSHI and FCR can reach up to 1.58x, 1.93x and 1.96x at an excitation frequency of 100 Hz, respectively.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126444782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027673
Maha S. Diab, S. Mahmoud
A field programmable analogue array (FPAA) for biomedical applications is introduced in this paper. The proposed FPAA is based on operational transconductance amplifier (OTA). The FPAA consists of configurable analogue blocks (CABs) arranged in three sections. Each section implements an OTA-C filter of reconfigurable order with variable gain, and bandwidth. Direct connections between CABs within a section, and between sections are present. The proposed reconfigurable FPAA permits different connections between its sections, providing a wide range of possible applications. Allowing the implementation of full biomedical systems, such as the analogue front-end (AFE) for biopotential signal acquisition. Reconfigurability and functionality of the proposed FPAA architecture is demonstrated through mapping of low power filters and AFE on FPAA. Simulations results for a 90 nm CMOS technology are given. The simulation results of filter and AFE on FPAA are compared to off- FPAA simulations.
{"title":"Ultra-Low Power Rectangular Field Programmable Analogue Arrays For Biomedical Applications","authors":"Maha S. Diab, S. Mahmoud","doi":"10.1109/ISOCC47750.2019.9027673","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027673","url":null,"abstract":"A field programmable analogue array (FPAA) for biomedical applications is introduced in this paper. The proposed FPAA is based on operational transconductance amplifier (OTA). The FPAA consists of configurable analogue blocks (CABs) arranged in three sections. Each section implements an OTA-C filter of reconfigurable order with variable gain, and bandwidth. Direct connections between CABs within a section, and between sections are present. The proposed reconfigurable FPAA permits different connections between its sections, providing a wide range of possible applications. Allowing the implementation of full biomedical systems, such as the analogue front-end (AFE) for biopotential signal acquisition. Reconfigurability and functionality of the proposed FPAA architecture is demonstrated through mapping of low power filters and AFE on FPAA. Simulations results for a 90 nm CMOS technology are given. The simulation results of filter and AFE on FPAA are compared to off- FPAA simulations.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115825520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISOCC47750.2019.9027704
Malik Summair Asghar, Saad Arslan, Hyungwon Kim, Jaehun Jun, Hyun-kyu Park
Large interactive touch screen displays are witnessing widespread acceptance among users, while approaching hundreds of Tx/Rx channels and reducing useable bandwidth. This presents several challenges and renders conventional touch detection methods ineffective. For smaller displays, employing concurrent Tx driving methods like Frequency Division Concurrent Driving (FDCD) or Coded Division Concurrent Driving (CDCD) improves SNR and substantially enhances report rate. In larger Touch Screen Panels (TSPs), however, it becomes difficult to drive the entire panel concurrently with either orthogonal frequencies or codes. In this work, a hybrid concurrent driving technique, which combines both FDCD and CDCD, is proposed and evaluated. The proposed driving technique aims to achieve better efficiency in terms of utilizing limited frequency bandwidth and improving the SNR. This work realizes the proposed driving technique by a MATLAB implementation. This paper includes SNR analysis for various scenarios, to evaluate the effectiveness of the proposed technique. The analysis reveals that the proposed method performs reliably under significant amount of noise for all corner cases.
{"title":"Hybrid Concurrent Driving Technique for Large Touch Screen Panels","authors":"Malik Summair Asghar, Saad Arslan, Hyungwon Kim, Jaehun Jun, Hyun-kyu Park","doi":"10.1109/ISOCC47750.2019.9027704","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9027704","url":null,"abstract":"Large interactive touch screen displays are witnessing widespread acceptance among users, while approaching hundreds of Tx/Rx channels and reducing useable bandwidth. This presents several challenges and renders conventional touch detection methods ineffective. For smaller displays, employing concurrent Tx driving methods like Frequency Division Concurrent Driving (FDCD) or Coded Division Concurrent Driving (CDCD) improves SNR and substantially enhances report rate. In larger Touch Screen Panels (TSPs), however, it becomes difficult to drive the entire panel concurrently with either orthogonal frequencies or codes. In this work, a hybrid concurrent driving technique, which combines both FDCD and CDCD, is proposed and evaluated. The proposed driving technique aims to achieve better efficiency in terms of utilizing limited frequency bandwidth and improving the SNR. This work realizes the proposed driving technique by a MATLAB implementation. This paper includes SNR analysis for various scenarios, to evaluate the effectiveness of the proposed technique. The analysis reveals that the proposed method performs reliably under significant amount of noise for all corner cases.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"490 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132365696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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