Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078491
Hyounghun Joe, Cheolsoo Park, Hyungtak Kim, Youngmin Kim
Stochastic computing is one of approximate computing, which provides lower power consumption through simpler designs with a tolerable error. However, stochastic computing has a fundamental limitation in bit width. The larger the bit size, the longer the computation time. Besides, the error rate also increases as the bit size increases. In this paper, we propose a new stochastic adder, in which stochastic computing is only applied in the lower bits to reduce overall errors in large bit addition. Simulation shows that the proposed design can achieve up to 17x average error reduction compared with the conventional design when a half of the bit is computed stochastically.
{"title":"Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy","authors":"Hyounghun Joe, Cheolsoo Park, Hyungtak Kim, Youngmin Kim","doi":"10.1109/ISOCC47750.2019.9078491","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078491","url":null,"abstract":"Stochastic computing is one of approximate computing, which provides lower power consumption through simpler designs with a tolerable error. However, stochastic computing has a fundamental limitation in bit width. The larger the bit size, the longer the computation time. Besides, the error rate also increases as the bit size increases. In this paper, we propose a new stochastic adder, in which stochastic computing is only applied in the lower bits to reduce overall errors in large bit addition. Simulation shows that the proposed design can achieve up to 17x average error reduction compared with the conventional design when a half of the bit is computed stochastically.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128681798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078504
Hoyoung Yu, Hyung-Min Lee, Youngjoo Shin, Youngmin Kim
As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.
{"title":"FPGA reverse engineering in Vivado design suite based on X-ray project","authors":"Hoyoung Yu, Hyung-Min Lee, Youngjoo Shin, Youngmin Kim","doi":"10.1109/ISOCC47750.2019.9078504","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078504","url":null,"abstract":"As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130668468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078462
Wei-Jun Liao, T. Tsai
Ultrasonic power transmission provides an attractive solution to minimize the size of the implants while achieving high power levels (100 μW to several mW) required for most implant applications. Also, ultrasonic power transmission is affected by the distance and the alignment, and results in a wide input voltage range. A wide-input-range ultrasonic power regulator with an adaptive voltage generator for implantable applications is presented in this paper. A highfrequency voltage doubler circuit is used in the receiver to regulate the output voltage. On-chip capacitance is used to minimize the volume of the implant. The proposed regulator is designed in TSMC 0.18um CMOS process with 1.8 V supply voltage, and achieves a peak efficiency of 56.2%. The input voltage ranges from ±0.5 V to ±1.8 V.
超声功率传输提供了一个有吸引力的解决方案，以最大限度地减少植入物的尺寸，同时实现大多数植入物应用所需的高功率水平(100 μW到几mW)。此外，超声波功率传输受距离和对准的影响，导致输入电压范围很宽。提出了一种具有自适应电压发生器的可植入型宽输入范围超声功率调节器。接收机采用高频倍压电路来调节输出电压。片上电容用于最小化植入体的体积。该稳压器采用TSMC 0.18um CMOS工艺设计，电源电压为1.8 V，峰值效率为56.2%。输入电压范围:±0.5 V ~±1.8 V。
{"title":"A Wide-Input-Range Ultrasonic Power Regulator with an Adaptive Voltage Generator for Implantable Applications","authors":"Wei-Jun Liao, T. Tsai","doi":"10.1109/ISOCC47750.2019.9078462","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078462","url":null,"abstract":"Ultrasonic power transmission provides an attractive solution to minimize the size of the implants while achieving high power levels (100 μW to several mW) required for most implant applications. Also, ultrasonic power transmission is affected by the distance and the alignment, and results in a wide input voltage range. A wide-input-range ultrasonic power regulator with an adaptive voltage generator for implantable applications is presented in this paper. A highfrequency voltage doubler circuit is used in the receiver to regulate the output voltage. On-chip capacitance is used to minimize the volume of the implant. The proposed regulator is designed in TSMC 0.18um CMOS process with 1.8 V supply voltage, and achieves a peak efficiency of 56.2%. The input voltage ranges from ±0.5 V to ±1.8 V.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125948813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078530
Shota Uchino, T. Yamamoto, F. Mohamad, K. Shinohara, T. Iida, T. Kousaka, H. Ohtagaki, H. Asahara
Thermoelectric power generation modules for industrial applications often require an output of several tens of watts, and DC-DC converters used for power matching are required to have high conversion efficiency at low voltage input. In this study, we realize high conversion efficiency at low voltage and we investigate basic circuit performance in the laboratory experiment. In addition, since some of the thermoelectric generation modules have low voltage output characteristics, it is necessary to design high step-up ratio DC-DC converter. In view of the above, we report on the design and trial evaluation of the generated power conditioning system with the high step-up ratio DC-DC converter.
{"title":"Basic circuit design of high step-up ratio DC-DC converter","authors":"Shota Uchino, T. Yamamoto, F. Mohamad, K. Shinohara, T. Iida, T. Kousaka, H. Ohtagaki, H. Asahara","doi":"10.1109/ISOCC47750.2019.9078530","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078530","url":null,"abstract":"Thermoelectric power generation modules for industrial applications often require an output of several tens of watts, and DC-DC converters used for power matching are required to have high conversion efficiency at low voltage input. In this study, we realize high conversion efficiency at low voltage and we investigate basic circuit performance in the laboratory experiment. In addition, since some of the thermoelectric generation modules have low voltage output characteristics, it is necessary to design high step-up ratio DC-DC converter. In view of the above, we report on the design and trial evaluation of the generated power conditioning system with the high step-up ratio DC-DC converter.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122204383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We take advantage of the relative gradient method and the bound component analysis algorithm to propose the relativegradient bound component analysis algorithm in this paper. This algorithm does not need to compute the inverse matrix and the covariance matrix. It can succesfully separate the mixed pictures without whitening. The time complexity and the space complexity of this algorithm are both lower than those of the original bound component analysis algorithm.
{"title":"Application of Blind-Signal-Processing Algorithm in Image Separation - Blind-Signal-Processing in Image Separation","authors":"Chuen-Yau Chen, Cheng-Yuan Lin, Wei-Ching Liu, Yen-Ting Chen","doi":"10.1109/ISOCC47750.2019.9078531","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078531","url":null,"abstract":"We take advantage of the relative gradient method and the bound component analysis algorithm to propose the relativegradient bound component analysis algorithm in this paper. This algorithm does not need to compute the inverse matrix and the covariance matrix. It can succesfully separate the mixed pictures without whitening. The time complexity and the space complexity of this algorithm are both lower than those of the original bound component analysis algorithm.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123167466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078513
Joshua Adiel Wijaya, T. Adiono
In this paper we proposed a configurable CNN architecture design for use in a SoC co-processor. The co-processor is configured and generated by the proposed design tools utilizing folding architecture and multiple processing elements working in parallel. The proposed system utilized a configurable system designer that can automatically generate the verilog source file that defines a CNN processor that can process various image and kernel sizes. The system designer also able to generate the program code to be run on the SoC platform. The system design has been verified using a ZYNQTM 7000 SoC platform and shows the processing result is similar to the simulation results. The system can reach the processing speed of 72.727 MHz.
{"title":"Configurable CNN SoC Co-Processor Architecture","authors":"Joshua Adiel Wijaya, T. Adiono","doi":"10.1109/ISOCC47750.2019.9078513","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078513","url":null,"abstract":"In this paper we proposed a configurable CNN architecture design for use in a SoC co-processor. The co-processor is configured and generated by the proposed design tools utilizing folding architecture and multiple processing elements working in parallel. The proposed system utilized a configurable system designer that can automatically generate the verilog source file that defines a CNN processor that can process various image and kernel sizes. The system designer also able to generate the program code to be run on the SoC platform. The system design has been verified using a ZYNQTM 7000 SoC platform and shows the processing result is similar to the simulation results. The system can reach the processing speed of 72.727 MHz.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078520
Huo Yingge, Imran Ali, Kangyoon Lee
In this paper, a wideband differential low noise amplifier (LNA) is presented for TV white space (TVWS) applications. For wideband input matching and high gain over 470~698 MHz TVWS bandwidth, a common-source (CS) complementary resistive shunt feedback amplifier is used in the proposed LNA. This LNA structure also reduces noise. The design achieves 26.4 dB gain and 1.75 dB noise figure. It consumes 22.56 mW power and draws 18.8 mA current from 1.2 V supply. It is integrated into TVWS transceiver with 130 nm CMOS technology and it occupies 531 × 279 μm² chip area.
{"title":"A Wideband Differential Low Noise Amplifier for TVWS Applications in 130 nm CMOS Technology","authors":"Huo Yingge, Imran Ali, Kangyoon Lee","doi":"10.1109/ISOCC47750.2019.9078520","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078520","url":null,"abstract":"In this paper, a wideband differential low noise amplifier (LNA) is presented for TV white space (TVWS) applications. For wideband input matching and high gain over 470~698 MHz TVWS bandwidth, a common-source (CS) complementary resistive shunt feedback amplifier is used in the proposed LNA. This LNA structure also reduces noise. The design achieves 26.4 dB gain and 1.75 dB noise figure. It consumes 22.56 mW power and draws 18.8 mA current from 1.2 V supply. It is integrated into TVWS transceiver with 130 nm CMOS technology and it occupies 531 × 279 μm² chip area.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127572727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078516
Chaeun Lee, Jaehyun Kim, Jihun Kim, Jaehyun Kim, Cheol Seong Hwang, Kiyoung Choi
We propose a simulation method for analog deep binarized neural networks which enables fast and accurate simulation. This method is based on look-up tables and can accelerate simulation on a GPU. It extracts the look-up tables using a circuit simulator such as SPICE under various types of environments. To prove the validity of this method, we show the experimental results for analog deep binarized neural networks. In the experiment, we could accelerate the simulation by 612K times compared to FineSim simulation on an example of multilayer perceptron.
{"title":"Fast Simulation Method for Analog Deep Binarized Neural Networks","authors":"Chaeun Lee, Jaehyun Kim, Jihun Kim, Jaehyun Kim, Cheol Seong Hwang, Kiyoung Choi","doi":"10.1109/ISOCC47750.2019.9078516","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078516","url":null,"abstract":"We propose a simulation method for analog deep binarized neural networks which enables fast and accurate simulation. This method is based on look-up tables and can accelerate simulation on a GPU. It extracts the look-up tables using a circuit simulator such as SPICE under various types of environments. To prove the validity of this method, we show the experimental results for analog deep binarized neural networks. In the experiment, we could accelerate the simulation by 612K times compared to FineSim simulation on an example of multilayer perceptron.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131156672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-06DOI: 10.1109/ISOCC47750.2019.9078534
J. Ruseckas, Gediminas Molis, A. Mackute-Varoneckiene, T. Krilavičius
For efficient spectrum sharing between noncooperating networks a fast spectrum scan must be implemented. Frequency, power, bandwidth and modulation have to be quickly estimated to adapt to the environment and cause minimal interference for other users even when protocol is not known. Here we propose to apply convolutional neural network for multicarrier signal detection and classification as it can measure all these parameters from one short data sample. For the classification and detection tasks, six multi-carrier signal modulations were generated. We have measured detection probability and classification accuracy over wide range of signal-to-noise ratios and have estimated the hardware resources needed for the task. In addition, we have studied impact of signal augmentation during training phase on classification accuracy when only portion of the signal is available. We show that signal four times shorter than 5G radio subframe can be sufficient for the task.
{"title":"Multi-carrier Signal Detection using Convolutional Neural Networks","authors":"J. Ruseckas, Gediminas Molis, A. Mackute-Varoneckiene, T. Krilavičius","doi":"10.1109/ISOCC47750.2019.9078534","DOIUrl":"https://doi.org/10.1109/ISOCC47750.2019.9078534","url":null,"abstract":"For efficient spectrum sharing between noncooperating networks a fast spectrum scan must be implemented. Frequency, power, bandwidth and modulation have to be quickly estimated to adapt to the environment and cause minimal interference for other users even when protocol is not known. Here we propose to apply convolutional neural network for multicarrier signal detection and classification as it can measure all these parameters from one short data sample. For the classification and detection tasks, six multi-carrier signal modulations were generated. We have measured detection probability and classification accuracy over wide range of signal-to-noise ratios and have estimated the hardware resources needed for the task. In addition, we have studied impact of signal augmentation during training phase on classification accuracy when only portion of the signal is available. We show that signal four times shorter than 5G radio subframe can be sufficient for the task.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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