This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 /spl mu/m standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013 mm/sup 2/ area. The proposed A/D converter is suitable for System-on-Chip (SoC) applications in wireless products and other ultra high speed applications.
{"title":"A 1-GSPS CMOS flash A/D converter for system-on-chip applications","authors":"Jincheol Yoo, Kyusun Choi, A. Tangel","doi":"10.1109/IWV.2001.923152","DOIUrl":"https://doi.org/10.1109/IWV.2001.923152","url":null,"abstract":"This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 /spl mu/m standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013 mm/sup 2/ area. The proposed A/D converter is suitable for System-on-Chip (SoC) applications in wireless products and other ultra high speed applications.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technique is presented for accurately computing the power of digital circuits described by behavioral- and gate-level designs. Accurate power estimation for high-level designs provides early warning of potential power problems, supporting design flexibility and a reduction of time and cost. The technique uses a behavioral VHDL specification or gate-level netlist as input. For a variety of combinational benchmark circuits, assuming the zero-delay model and uncorrelated primary inputs, the approach has been tested and compared with the Berkeley SIS power estimator. The proposed technique has been implemented in a program called the Behavioral Level Activity and Power Estimator (BLAPE). Experimental results demonstrate a savings in time with an average error less than 1.00%.
{"title":"Improved power estimation for behavioral and gate level designs","authors":"R. L. Wright, M. Shanblatt","doi":"10.1109/IWV.2001.923147","DOIUrl":"https://doi.org/10.1109/IWV.2001.923147","url":null,"abstract":"A technique is presented for accurately computing the power of digital circuits described by behavioral- and gate-level designs. Accurate power estimation for high-level designs provides early warning of potential power problems, supporting design flexibility and a reduction of time and cost. The technique uses a behavioral VHDL specification or gate-level netlist as input. For a variety of combinational benchmark circuits, assuming the zero-delay model and uncorrelated primary inputs, the approach has been tested and compared with the Berkeley SIS power estimator. The proposed technique has been implemented in a program called the Behavioral Level Activity and Power Estimator (BLAPE). Experimental results demonstrate a savings in time with an average error less than 1.00%.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128758017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.
{"title":"A low-energy adaptive bus coding scheme","authors":"B. Bishop, A. Bahuman","doi":"10.1109/IWV.2001.923149","DOIUrl":"https://doi.org/10.1109/IWV.2001.923149","url":null,"abstract":"We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123896536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Becker, Thilo Pionteck, C. Habermann, M. Glesner
This paper presents the hardware structure and application of a coarse-grained dynamically reconfigurable hardware architecture dedicated to wireless communication systems. The application tailored architecture, called DReAM (D_ynamically R_econfigurable Hardware A_rchitecture for M_obile Communication Systems), is a research project at the Darmstadt University of Technology. It covers the complete design process from analyzing the requirements for the dedicated application field, the specification and VHDL implementation of the architecture, up to the physical layout for the final chip. In the following we provide an overview of the major design stages, starting with a motivation for choosing the concept of distributed arithmetic in reconfigurable computing.
{"title":"Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture","authors":"J. Becker, Thilo Pionteck, C. Habermann, M. Glesner","doi":"10.1109/IWV.2001.923138","DOIUrl":"https://doi.org/10.1109/IWV.2001.923138","url":null,"abstract":"This paper presents the hardware structure and application of a coarse-grained dynamically reconfigurable hardware architecture dedicated to wireless communication systems. The application tailored architecture, called DReAM (D_ynamically R_econfigurable Hardware A_rchitecture for M_obile Communication Systems), is a research project at the Darmstadt University of Technology. It covers the complete design process from analyzing the requirements for the dedicated application field, the specification and VHDL implementation of the architecture, up to the physical layout for the final chip. In the following we provide an overview of the major design stages, starting with a motivation for choosing the concept of distributed arithmetic in reconfigurable computing.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122942416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show that some structures benefit substantially from the addition of appropriate output buffering.
{"title":"Load-sensitive flip-flop characterizations","authors":"Seongmoo Heo, K. Asanović","doi":"10.1109/IWV.2001.923144","DOIUrl":"https://doi.org/10.1109/IWV.2001.923144","url":null,"abstract":"Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show that some structures benefit substantially from the addition of appropriate output buffering.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Shih, B. Calhoun, Seong-Hwan Cho, A. Chandrakasan
Wireless microsensors are being used to form large, dense networks for the purposes of long-term environmental sensing and data collection. Unfortunately these networks are typically deployed in remote environments where energy sources are limited. Thus, designing fault-tolerant wireless microsensor networks with long system lifetimes can be challenging. By applying energy-efficient techniques at all levels of the system hierarchy, system lifetime can be extended. In this paper, energy-efficient techniques that adapt underlying communication parameters will be presented in the context of wireless microsensor networks. In particular, the effect of adapting link and physical layer parameters, such as output transmit power and error control coding, on system energy consumption will be examined.
{"title":"Energy-efficient link layer for wireless microsensor networks","authors":"E. Shih, B. Calhoun, Seong-Hwan Cho, A. Chandrakasan","doi":"10.1109/IWV.2001.923134","DOIUrl":"https://doi.org/10.1109/IWV.2001.923134","url":null,"abstract":"Wireless microsensors are being used to form large, dense networks for the purposes of long-term environmental sensing and data collection. Unfortunately these networks are typically deployed in remote environments where energy sources are limited. Thus, designing fault-tolerant wireless microsensor networks with long system lifetimes can be challenging. By applying energy-efficient techniques at all levels of the system hierarchy, system lifetime can be extended. In this paper, energy-efficient techniques that adapt underlying communication parameters will be presented in the context of wireless microsensor networks. In particular, the effect of adapting link and physical layer parameters, such as output transmit power and error control coding, on system energy consumption will be examined.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a new semi-distributed architecture for clock distribution that is suitable for gigascale integration. First, the limitations associated with conventional clock distribution networks are discussed. Next, some of the alternative solutions to the clock distribution problem are reviewed and compared in terms of architecture, power dissipation, clock inaccuracy, and ease of implementation. The compatibility of the alternatives with established design-for-testability and design-for-debuggability techniques is also evaluated. Then, the proposed architecture is introduced. It employs an array of phase-locked loops (PLLs) synchronized using digital feedback. The new architecture addresses the limitations associated with conventional clocking networks, but does not suffer from the practical shortcomings affecting the alternatives proposed so far.
{"title":"A multi-PLL clock distribution architecture for gigascale integration","authors":"M. Saint-Laurent, M. Swaminathan","doi":"10.1109/IWV.2001.923136","DOIUrl":"https://doi.org/10.1109/IWV.2001.923136","url":null,"abstract":"This paper proposes a new semi-distributed architecture for clock distribution that is suitable for gigascale integration. First, the limitations associated with conventional clock distribution networks are discussed. Next, some of the alternative solutions to the clock distribution problem are reviewed and compared in terms of architecture, power dissipation, clock inaccuracy, and ease of implementation. The compatibility of the alternatives with established design-for-testability and design-for-debuggability techniques is also evaluated. Then, the proposed architecture is introduced. It employs an array of phase-locked loops (PLLs) synchronized using digital feedback. The new architecture addresses the limitations associated with conventional clocking networks, but does not suffer from the practical shortcomings affecting the alternatives proposed so far.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124656478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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