Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993594
B. Devlin, M. Ikeda, K. Asada
A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6× total energy reduction and 6.4× performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8× improvement in power-delay product (PDP) and 2× performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6× PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz.
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Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993600
M. Kochte, K. Miyase, X. Wen, S. Kajihara, Yuta Yamato, K. Enokimoto, H. Wunderlich
Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.
{"title":"SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures","authors":"M. Kochte, K. Miyase, X. Wen, S. Kajihara, Yuta Yamato, K. Enokimoto, H. Wunderlich","doi":"10.1109/ISLPED.2011.5993600","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993600","url":null,"abstract":"Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122838587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993604
T. Sakurai
In this talk, key design considerations in deep-volt are summarized with emphasis on the difference between normal voltage design and ultra-low voltage design.
在这次演讲中，总结了深电压设计的关键考虑因素，重点介绍了正常电压设计和超低电压设计的区别。
{"title":"Designing ultra-low voltage logic","authors":"T. Sakurai","doi":"10.1109/ISLPED.2011.5993604","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993604","url":null,"abstract":"In this talk, key design considerations in deep-volt are summarized with emphasis on the difference between normal voltage design and ultra-low voltage design.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122861460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993674
Pingqiang Zhou, Jieming Yin, Antonia Zhai, S. Sapatnekar
Voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. We propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network frequency and save network energy, without significant performance degradation. Furthermore, we demonstrate the use of simple performance metrics to determine the optimal operation frequency, considering the energy/performance impact on all aspects of the system — the cores, the caches and the interconnection network.
{"title":"NoC frequency scaling with flexible-pipeline routers","authors":"Pingqiang Zhou, Jieming Yin, Antonia Zhai, S. Sapatnekar","doi":"10.1109/ISLPED.2011.5993674","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993674","url":null,"abstract":"Voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. We propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network frequency and save network energy, without significant performance degradation. Furthermore, we demonstrate the use of simple performance metrics to determine the optimal operation frequency, considering the energy/performance impact on all aspects of the system — the cores, the caches and the interconnection network.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123613563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993599
W. Shum, J. Anderson
This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don't-cares in the circuit by setting their values based on the circuit's simulated glitch behavior. Glitch power is reduced by up to 49.0%, with an average of 13.7%, while total dynamic power is reduced by up to 12.5%, with an average of 4.0%. The algorithm is applied after placement and routing, and has zero area and performance overhead.
{"title":"FPGA glitch power analysis and reduction","authors":"W. Shum, J. Anderson","doi":"10.1109/ISLPED.2011.5993599","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993599","url":null,"abstract":"This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don't-cares in the circuit by setting their values based on the circuit's simulated glitch behavior. Glitch power is reduced by up to 49.0%, with an average of 13.7%, while total dynamic power is reduced by up to 12.5%, with an average of 4.0%. The algorithm is applied after placement and routing, and has zero area and performance overhead.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"40 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993606
M. Koyanagi
A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.
{"title":"3D Super chip technology to achieve low-power and high-performance system-on-a chip","authors":"M. Koyanagi","doi":"10.1109/ISLPED.2011.5993606","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993606","url":null,"abstract":"A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126278503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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