Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993628
A. Vincenzi, A. Sridhar, M. Ruggiero, David Atienza Alonso
Heat removal is one of the major challenges faced in developing the new generation of high density integrated circuits. Future design technologies strongly depend on the availability of efficient means for thermal modeling and analysis. These thermal models must be also accurate and provide the most efficient level of abstraction enabling fast execution. We propose an innovative thermal simulation method based on Neural Networks that is able to solve the scalability problem of transient heat flow simulation in large 2D/3D multi-processor ICs by exploiting the computational power of massively parallel graphics processing units (GPUs).
{"title":"Fast thermal simulation of 2D/3D integrated circuits exploiting neural networks and GPUs","authors":"A. Vincenzi, A. Sridhar, M. Ruggiero, David Atienza Alonso","doi":"10.1109/ISLPED.2011.5993628","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993628","url":null,"abstract":"Heat removal is one of the major challenges faced in developing the new generation of high density integrated circuits. Future design technologies strongly depend on the availability of efficient means for thermal modeling and analysis. These thermal models must be also accurate and provide the most efficient level of abstraction enabling fast execution. We propose an innovative thermal simulation method based on Neural Networks that is able to solve the scalability problem of transient heat flow simulation in large 2D/3D multi-processor ICs by exploiting the computational power of massively parallel graphics processing units (GPUs).","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993652
Ming-Hung Chang, Y. Chiu, Shu-Lin Lai, W. Hwang
Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.
{"title":"A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS","authors":"Ming-Hung Chang, Y. Chiu, Shu-Lin Lai, W. Hwang","doi":"10.1109/ISLPED.2011.5993652","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993652","url":null,"abstract":"Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133830142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993665
G. Szarka, P. Proynov, B. Stark, S. Burrow, N. McNeill
This paper demonstrates single-stage boost rectification for electromagnetic energy harvesters down to approximately 100 μW using practical low-power techniques. The circuits exploit the inductance of the generator, and operate without a discrete inductor, which facilitates integration. Experimental results demonstrate the importance of switching device selection, and the compound effect of the duty ratio on energy harvester output power and converter efficiency, as a function of load current. The circuits demonstrate up to 84.1% harvester utilization at the maximum extractable harvester power of 141 μW, and conversion efficiencies of 73.3% and 59.4% for half- and full-wave operation respectively, neglecting gate drive losses.
{"title":"Experimental investigation of inductorless, single-stage boost rectification for sub-mW electromagnetic energy harvesters","authors":"G. Szarka, P. Proynov, B. Stark, S. Burrow, N. McNeill","doi":"10.1109/ISLPED.2011.5993665","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993665","url":null,"abstract":"This paper demonstrates single-stage boost rectification for electromagnetic energy harvesters down to approximately 100 μW using practical low-power techniques. The circuits exploit the inductance of the generator, and operate without a discrete inductor, which facilitates integration. Experimental results demonstrate the importance of switching device selection, and the compound effect of the duty ratio on energy harvester output power and converter efficiency, as a function of load current. The circuits demonstrate up to 84.1% harvester utilization at the maximum extractable harvester power of 141 μW, and conversion efficiencies of 73.3% and 59.4% for half- and full-wave operation respectively, neglecting gate drive losses.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"90 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133558713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993671
Piotr Patronik, Krzysztof S. Berezowski, S. Piestrak, J. Biernat, Aviral Shrivastava
In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques of sharing of subexpressions in the multiplier block (MB), to its optimized usage in the MB and accumulation pipeline hardware design. As a result, we propose a common subexpression elimination (CSE) based synthesis technique for RNS-based MBs, along with a high-performance RNS-based FIR filter architecture that employs RNS arithmetic principles but implements them mainly using more efficient 2's complement hardware. Several filters with numbers of taps ranging from 25 to 326 and dynamic ranges from 24 to 50 bits have been synthesized using TSMC 90 nm LP kit and Cadence RTL Compiler. Comparison of power, delay, and area of the new filters implemented using the 4- and 5-moduli RNSs against various equivalent 2's complement counterparts show uniform improvement in performance and power efficiency, often accompanied by significant reduction in area/power consumption as compared to 2's complement implementations. We observed up to 22% improvement in peformance (19% reduction in area) within bounded power envelope, or up to 14% reduction in power consumption (12% reduction in area) at same frequency.
{"title":"Fast and energy-efficient constant-coefficient FIR filters using residue number system","authors":"Piotr Patronik, Krzysztof S. Berezowski, S. Piestrak, J. Biernat, Aviral Shrivastava","doi":"10.1109/ISLPED.2011.5993671","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993671","url":null,"abstract":"In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques of sharing of subexpressions in the multiplier block (MB), to its optimized usage in the MB and accumulation pipeline hardware design. As a result, we propose a common subexpression elimination (CSE) based synthesis technique for RNS-based MBs, along with a high-performance RNS-based FIR filter architecture that employs RNS arithmetic principles but implements them mainly using more efficient 2's complement hardware. Several filters with numbers of taps ranging from 25 to 326 and dynamic ranges from 24 to 50 bits have been synthesized using TSMC 90 nm LP kit and Cadence RTL Compiler. Comparison of power, delay, and area of the new filters implemented using the 4- and 5-moduli RNSs against various equivalent 2's complement counterparts show uniform improvement in performance and power efficiency, often accompanied by significant reduction in area/power consumption as compared to 2's complement implementations. We observed up to 22% improvement in peformance (19% reduction in area) within bounded power envelope, or up to 14% reduction in power consumption (12% reduction in area) at same frequency.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130252361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyunjoong Lee, Hyongmin Lee, J. Woo, Sunkwon Kim, Young June Park, Suhwan Kim
We present a sensor readout integrated circuit for the CNT bio-sensor array, the heart of which is our low-power current-input continuous-time ΔΣ modulator that is capable of dynamic range extension. Experimental results show that the prototype chip, designed and fabricated in 0.18μm CMOS process, achieves a dynamic range of 87.746dB and has a readout rate of 160kHz, which guarantees 1k sample/s per each sensor. It consumes 8.94μW/cell considering the 16×10 sensors and its core area is 0.085mm2.
{"title":"A CMOS readout integrated circuit with wide dynamic range for a CNT bio-sensor array system","authors":"Hyunjoong Lee, Hyongmin Lee, J. Woo, Sunkwon Kim, Young June Park, Suhwan Kim","doi":"10.5555/2016802.2016884","DOIUrl":"https://doi.org/10.5555/2016802.2016884","url":null,"abstract":"We present a sensor readout integrated circuit for the CNT bio-sensor array, the heart of which is our low-power current-input continuous-time ΔΣ modulator that is capable of dynamic range extension. Experimental results show that the prototype chip, designed and fabricated in 0.18μm CMOS process, achieves a dynamic range of 87.746dB and has a readout rate of 160kHz, which guarantees 1k sample/s per each sensor. It consumes 8.94μW/cell considering the 16×10 sensors and its core area is 0.085mm2.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131806271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993668
M. Yokokawa, F. Shoji, Atsuya Uno, M. Kurokawa, Tadashi Watanabe
The K computer is a distributed memory supercomputer system consisting of more than 80,000 compute nodes which is being developed by RIKEN as a Japanese national project. Its performance is aimed at achieving 10 peta-flops sustained in the LINPACK benchmark. The system is under installation and adjustment. The whole system will be operational in 2012.
{"title":"The K computer: Japanese next-generation supercomputer development project","authors":"M. Yokokawa, F. Shoji, Atsuya Uno, M. Kurokawa, Tadashi Watanabe","doi":"10.1109/ISLPED.2011.5993668","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993668","url":null,"abstract":"The K computer is a distributed memory supercomputer system consisting of more than 80,000 compute nodes which is being developed by RIKEN as a Japanese national project. Its performance is aimed at achieving 10 peta-flops sustained in the LINPACK benchmark. The system is under installation and adjustment. The whole system will be operational in 2012.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133150448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993661
Y. Miyahara
Mobile communication technology has been improving the connection speed every year. In addition, the wireless communication LSI improves not only speed but also the reliability and functionality due to market requirements. As a result, the power of consumption of the wireless RF chip LSI has been much bloated. Currently, Panasonic is interested in two categories of technology in the new market area. One is the ultra-low power radio technology with several kbps which requires more than decade operation by a single coin battery. Another is the ultra-high-speed radio technology for data transfer. Both common wireless technologies can extremely reduce power consumption in terms of the parameter of energy expense over 1-bit (pJ/bit technology). In this talk, we introduce the technology of the low power radio system ever developed for a cellular phone. The digital RF architecture with polar transmitter system can improve the power amplifier efficiency. Then we introduce the ultra-low power wireless core technologies for RF, including the standardizations. Simple OOK signal modulation in wireless system can extremely reduce the total power consumption in RF. The low power system and circuit technique are introduced. These ultra-low-power radios are used for the smart grid home network based on the IEEE802.15.4g or body area network based on IEEE802.15.6 for future products. Finally, we explain Giga-bit wireless data communication where 60 GHz-band is one of the most attractive frequency resources, since 60 GHz band has already been allocated as unlicensed band with more than 7 GHz bandwidth in most of countries,. IEEE802.15.3c specification has been developed as the wireless personal area network (WPAN) standard above 1-Gbps in 2009. Other standardization bodies, such as the Wireless Gigabit Alliance and the IEEE802.11ad are also being developed for the wireless local area network (WLAN) toward 2012. All standards are targeting short range wireless connectivity among personal computers, audio-video equipments and mobile devices (e.g. smart phone or digital still camera) for uncompressed high-definition (HD) video stream and/or “sync and go” file transfer applications. In order to realize gigabit wireless connectivity for mobile, low power consumption less than 1 W with more than1 Gbps (less than 1pJ/bit) is required. Achieving such a low power radio at 60 GHz including the high-speed baseband is challenging. Using a CMOS technology is a promising approach to realize single chip solution with less than 1pJ/bit.
{"title":"Next-generation wireless technologies trends for ultra low energy","authors":"Y. Miyahara","doi":"10.1109/ISLPED.2011.5993661","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993661","url":null,"abstract":"Mobile communication technology has been improving the connection speed every year. In addition, the wireless communication LSI improves not only speed but also the reliability and functionality due to market requirements. As a result, the power of consumption of the wireless RF chip LSI has been much bloated. Currently, Panasonic is interested in two categories of technology in the new market area. One is the ultra-low power radio technology with several kbps which requires more than decade operation by a single coin battery. Another is the ultra-high-speed radio technology for data transfer. Both common wireless technologies can extremely reduce power consumption in terms of the parameter of energy expense over 1-bit (pJ/bit technology). In this talk, we introduce the technology of the low power radio system ever developed for a cellular phone. The digital RF architecture with polar transmitter system can improve the power amplifier efficiency. Then we introduce the ultra-low power wireless core technologies for RF, including the standardizations. Simple OOK signal modulation in wireless system can extremely reduce the total power consumption in RF. The low power system and circuit technique are introduced. These ultra-low-power radios are used for the smart grid home network based on the IEEE802.15.4g or body area network based on IEEE802.15.6 for future products. Finally, we explain Giga-bit wireless data communication where 60 GHz-band is one of the most attractive frequency resources, since 60 GHz band has already been allocated as unlicensed band with more than 7 GHz bandwidth in most of countries,. IEEE802.15.3c specification has been developed as the wireless personal area network (WPAN) standard above 1-Gbps in 2009. Other standardization bodies, such as the Wireless Gigabit Alliance and the IEEE802.11ad are also being developed for the wireless local area network (WLAN) toward 2012. All standards are targeting short range wireless connectivity among personal computers, audio-video equipments and mobile devices (e.g. smart phone or digital still camera) for uncompressed high-definition (HD) video stream and/or “sync and go” file transfer applications. In order to realize gigabit wireless connectivity for mobile, low power consumption less than 1 W with more than1 Gbps (less than 1pJ/bit) is required. Achieving such a low power radio at 60 GHz including the high-speed baseband is challenging. Using a CMOS technology is a promising approach to realize single chip solution with less than 1pJ/bit.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993649
Karthik Kumar, K. Doshi, Martin Dimitrov, Yung-Hsiang Lu
Energy efficiency is an important factor in designing and configuring enterprise servers. In these servers, memory may consume 40% of the total system power. Different memory configurations (sizes, numbers of ranks, speeds, etc.) can have significant impacts on the performance and energy consumption of enterprise workloads. Many of these workloads, such as decision support systems (DSS), require large amounts of memory. This paper investigates the potential to save energy by making the memory configuration adaptive to workload behavior. We present a case study on how memory configurations affect energy consumption and performance for running DSS. We measure the energy consumption and performance of a commercial enterprise server, and develop a model to describe the conditions when energy can be saved with acceptable performance degradation. Using this model, we identify opportunities to save energy in future enterprise servers.
{"title":"Memory energy management for an enterprise decision support system","authors":"Karthik Kumar, K. Doshi, Martin Dimitrov, Yung-Hsiang Lu","doi":"10.1109/ISLPED.2011.5993649","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993649","url":null,"abstract":"Energy efficiency is an important factor in designing and configuring enterprise servers. In these servers, memory may consume 40% of the total system power. Different memory configurations (sizes, numbers of ranks, speeds, etc.) can have significant impacts on the performance and energy consumption of enterprise workloads. Many of these workloads, such as decision support systems (DSS), require large amounts of memory. This paper investigates the potential to save energy by making the memory configuration adaptive to workload behavior. We present a case study on how memory configurations affect energy consumption and performance for running DSS. We measure the energy consumption and performance of a commercial enterprise server, and develop a model to describe the conditions when energy can be saved with acceptable performance degradation. Using this model, we identify opportunities to save energy in future enterprise servers.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121078605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993629
David Li, P. Chuang, D. Nairn, M. Sachdev
Flip-flop metastability is becoming an important consideration for designing reliable synchronous and asynchronous systems, especially in the sub-threshold region where it degrades exponentially with the reduction in supply voltage. In this paper, detailed analysis is given on the design of metastable-hardened flip-flops in the sub-threshold region. Proper transistor sizing using either transconductance or load variation along with implementing the inverter pair in the flip-flop master-stage with low-Vth can result in significant reduction in the time-resolving constant τ. Extensive simulation results have shown that the optimum metastability-power-delay-product (MPDP) design allows the flip-flops to improve its metastability with a more balanced design tradeoff between performance and power consumption.
{"title":"Design and analysis of metastable-hardened flip-flops in sub-threshold region","authors":"David Li, P. Chuang, D. Nairn, M. Sachdev","doi":"10.1109/ISLPED.2011.5993629","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993629","url":null,"abstract":"Flip-flop metastability is becoming an important consideration for designing reliable synchronous and asynchronous systems, especially in the sub-threshold region where it degrades exponentially with the reduction in supply voltage. In this paper, detailed analysis is given on the design of metastable-hardened flip-flops in the sub-threshold region. Proper transistor sizing using either transconductance or load variation along with implementing the inverter pair in the flip-flop master-stage with low-Vth can result in significant reduction in the time-resolving constant τ. Extensive simulation results have shown that the optimum metastability-power-delay-product (MPDP) design allows the flip-flops to improve its metastability with a more balanced design tradeoff between performance and power consumption.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115001719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993607
Manuj R. Sabharwal
Software is increasingly becoming a central issue in low power consumer based system. The amount of energy consumed by software has severe battery impact on the system. Minimizing power consumption is one of the primary challenges that today's developers faces due to lack of instrumentation functionality in the system. This tutorial will cover different prospect of energy usage and energy aware software design in system ranging from notebooks to smartphones/tablets. This tutorial will give special importance on the role of idle software in attain overall system energy efficiency. In Summary, this tutorial will give overview of software impact on hardware, quantify the impact and fix the issues in applications to extend the battery life.
{"title":"Software power optimization: Analysis and optimization for energy-efficient software","authors":"Manuj R. Sabharwal","doi":"10.1109/ISLPED.2011.5993607","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993607","url":null,"abstract":"Software is increasingly becoming a central issue in low power consumer based system. The amount of energy consumed by software has severe battery impact on the system. Minimizing power consumption is one of the primary challenges that today's developers faces due to lack of instrumentation functionality in the system. This tutorial will cover different prospect of energy usage and energy aware software design in system ranging from notebooks to smartphones/tablets. This tutorial will give special importance on the role of idle software in attain overall system energy efficiency. In Summary, this tutorial will give overview of software impact on hardware, quantify the impact and fix the issues in applications to extend the battery life.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117094408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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