Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993605
T. Hiramoto
The challenges for ultra-low-voltage operation are reviewed from the device side. The degradations of transistor variability and subthreshold swing are the main obstacles for the ultra-low-voltage operation. A new transistor structure with fully-depleted channel is discussed as a possible solution.
{"title":"Ultra-low-voltage operation: Device perspective","authors":"T. Hiramoto","doi":"10.1109/ISLPED.2011.5993605","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993605","url":null,"abstract":"The challenges for ultra-low-voltage operation are reviewed from the device side. The degradations of transistor variability and subthreshold swing are the main obstacles for the ultra-low-voltage operation. A new transistor structure with fully-depleted channel is discussed as a possible solution.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993598
T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya, T. Sakurai
Determinant factors of the minimum operating voltage (VDDmin) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. VDDmin consists of a systematic component (VDDmin(SYS)) and a random variation component (VDDmin(RAND)). VDDmin(SYS) is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (VDD). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. VDDmin(RAND) is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of VDDmin is measured for the first time. The temperature for the worst corner analysis for VDDmin should be changed depending on the number of gate counts of logic circuits.
{"title":"Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS","authors":"T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya, T. Sakurai","doi":"10.1109/ISLPED.2011.5993598","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993598","url":null,"abstract":"Determinant factors of the minimum operating voltage (V<inf>DDmin</inf>) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. V<inf>DDmin</inf> consists of a systematic component (V<inf>DDmin(SYS)</inf>) and a random variation component (V<inf>DDmin(RAND)</inf>). V<inf>DDmin(SYS)</inf> is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (V<inf>DD</inf>). The tuning of the logic threshold voltage of each logic gate is achieved by the sizing of the gate width of nMOS/pMOS. V<inf>DDmin(RAND)</inf> is minimized by reducing the random threshold variation achieved by increasing the gate width or the forward body biasing. In addition, the temperature dependence of V<inf>DDmin</inf> is measured for the first time. The temperature for the worst corner analysis for V<inf>DDmin</inf> should be changed depending on the number of gate counts of logic circuits.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993663
Liyuan Liu, Dongmei Li, Y. Ye, Zhihua Wang
This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference voltage. As a result the size of sampling capacitor which determines the thermal noise level is reduced. The feed-forward path is introduced to the modulator loop which bypasses input signal component and let the integrator only process quantization error signal. The integrator's swing is hence suppressed, and the design requirement of amplifier inside the integrator is relaxed. On the circuits' level, single stage amplifier with only 40dB gain is adopted to construct the first integrator. Large sampling integrator can be driven with low current consumption. In the quantizer design, traditional flash quantizer is replaced by successive approximation (SAR) quantizer. The overwhelming advantage is that the number of comparators is reduced to only one which saves power and area cost. The control of SAR employs asynchronous logic which prevents high frequency clock generation. Implemented in 0.18μm standard CMOS technology the prototype modulator achieves 92.4dB peak SNDR with only 352μW power dissipation. The total chip area is 1.66mm2 including bonding pad.
{"title":"A 92.4dB SNDR 24kHz ΔΣ modulator consuming 352μW","authors":"Liyuan Liu, Dongmei Li, Y. Ye, Zhihua Wang","doi":"10.1109/ISLPED.2011.5993663","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993663","url":null,"abstract":"This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference voltage. As a result the size of sampling capacitor which determines the thermal noise level is reduced. The feed-forward path is introduced to the modulator loop which bypasses input signal component and let the integrator only process quantization error signal. The integrator's swing is hence suppressed, and the design requirement of amplifier inside the integrator is relaxed. On the circuits' level, single stage amplifier with only 40dB gain is adopted to construct the first integrator. Large sampling integrator can be driven with low current consumption. In the quantizer design, traditional flash quantizer is replaced by successive approximation (SAR) quantizer. The overwhelming advantage is that the number of comparators is reduced to only one which saves power and area cost. The control of SAR employs asynchronous logic which prevents high frequency clock generation. Implemented in 0.18μm standard CMOS technology the prototype modulator achieves 92.4dB peak SNDR with only 352μW power dissipation. The total chip area is 1.66mm2 including bonding pad.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993650
S. Sapatnekar
As the computational capabilities of integrated systems grow, they become increasingly power-hungry. This dissipated power is converted to heat that must be removed from the system, and a failure to do so can result in excessive temperatures. The trends for thermal problems are severe enough along the Moore's law curve, but become even worse with the advent of 3D ICs, where the power density per unit footprint increases. Therefore, in future systems, it is a virtual certainty that thermal bottlenecks will gain centerstage, and the problem of thermal management must be tackled aggressively at all levels of design. At the chip level, the focus of thermally-aware design has moved from merely package-level considerations to include on-chip thermal management. Thermal variations during the operation of a circuit can result in changes or unpredictability in its performance and reliability. It is essential to solve the problem of thermally-aware design at all levels, developing techniques that range from presilicon analysis and optimization to postsilicon mitigation, taking into account all of the effects associated with elevated temperatures. This talk will provide an overview of challenges and opportunities in this domain.
{"title":"The whys and hows of thermal management","authors":"S. Sapatnekar","doi":"10.1109/ISLPED.2011.5993650","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993650","url":null,"abstract":"As the computational capabilities of integrated systems grow, they become increasingly power-hungry. This dissipated power is converted to heat that must be removed from the system, and a failure to do so can result in excessive temperatures. The trends for thermal problems are severe enough along the Moore's law curve, but become even worse with the advent of 3D ICs, where the power density per unit footprint increases. Therefore, in future systems, it is a virtual certainty that thermal bottlenecks will gain centerstage, and the problem of thermal management must be tackled aggressively at all levels of design. At the chip level, the focus of thermally-aware design has moved from merely package-level considerations to include on-chip thermal management. Thermal variations during the operation of a circuit can result in changes or unpredictability in its performance and reliability. It is essential to solve the problem of thermally-aware design at all levels, developing techniques that range from presilicon analysis and optimization to postsilicon mitigation, taking into account all of the effects associated with elevated temperatures. This talk will provide an overview of challenges and opportunities in this domain.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115407937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993659
C. Brandolese, S. Corbetta, W. Fornaciari
Early estimation of embedded software power consumption is a critical issue that can determine the quality and, sometimes, the feasibility of a system. Architecture-specific, cycle-accurate simulators are valuable tools for fine-tuning performance of critical sections of the application but are often too slow for the simulation of entire systems. This paper proposes a fast and statistically accurate methodology to evaluate the energy performance of embedded software and describes the associated toolchain. The methodology is based on a static characterization of the target instruction set to allow estimation on an equivalent, target-independent intermediate code representation.
{"title":"Software energy estimation based on statistical characterization of intermediate compilation code","authors":"C. Brandolese, S. Corbetta, W. Fornaciari","doi":"10.1109/ISLPED.2011.5993659","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993659","url":null,"abstract":"Early estimation of embedded software power consumption is a critical issue that can determine the quality and, sometimes, the feasibility of a system. Architecture-specific, cycle-accurate simulators are valuable tools for fine-tuning performance of critical sections of the application but are often too slow for the simulation of entire systems. This paper proposes a fast and statistically accurate methodology to evaluate the energy performance of embedded software and describes the associated toolchain. The methodology is based on a static characterization of the target instruction set to allow estimation on an equivalent, target-independent intermediate code representation.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130255758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993614
R. Abdallah, P. Shenoy, Naresh R Shanbhag, P. Krein
This paper addresses the problem of designing energy-efficient embedded systems by jointly optimizing the power consumption of both the DC-DC converter and the computational core. Past work has shown that there exists a minimum energy operating point (MEOP) in the subthreshold region for computational cores (C-MEOP), at which the dynamic and leakage powers are balanced. The MEOP is defined by the 3-tuple consisting of the optimum energy consumption E∗, optimum voltage V∗ and optimum frequency f∗. First, we show that the DC-DC converter losses in dynamic voltage scaling (DVS) cause the overall system MEOP (S-MEOP) to differ significantly from C-MEOP. Simulations in a 130-nm, 1.2V commercial CMOS process show that operation at S-MEOP results in a 45.5% energy savings over operating at a core voltage V∗C suggested by C-MEOP. The DC-DC converter efficiency is also improved by 2.2X. Second, we show that architectural techniques such as parallelization cause the S-MEOP to approach C-MEOP. Thus, it is sufficient to track C-MEOP — a much easier task on-chip — in order to account for process variations. We show that DC-DC converter losses reduces in subthreshold region but increases in superthreshold region when parallelization is employed. This observation leads us to propose a reconfigurable core architecture that improves the converter efficiency by 2.3X at C-MEOP, and makes energy consumption at S-MEOP and C-MEOP to be within 4% of each other, while improving throughput in the subthreshold region by at least 8X. Finally, we show that pipelining, which has been proposed to decrease core energy at C-MEOP while improving throughput [1], adversely affects the S-MEOP. The pipelined-core system energy at S-MEOP is 85% lower than the pipelined-core system energy when operating at the C-MEOP voltage V∗C.
{"title":"System energy minimization via joint optimization of the DC-DC converter and the core","authors":"R. Abdallah, P. Shenoy, Naresh R Shanbhag, P. Krein","doi":"10.1109/ISLPED.2011.5993614","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993614","url":null,"abstract":"This paper addresses the problem of designing energy-efficient embedded systems by jointly optimizing the power consumption of both the DC-DC converter and the computational core. Past work has shown that there exists a minimum energy operating point (MEOP) in the subthreshold region for computational cores (C-MEOP), at which the dynamic and leakage powers are balanced. The MEOP is defined by the 3-tuple consisting of the optimum energy consumption E∗, optimum voltage V∗ and optimum frequency f∗. First, we show that the DC-DC converter losses in dynamic voltage scaling (DVS) cause the overall system MEOP (S-MEOP) to differ significantly from C-MEOP. Simulations in a 130-nm, 1.2V commercial CMOS process show that operation at S-MEOP results in a 45.5% energy savings over operating at a core voltage V∗C suggested by C-MEOP. The DC-DC converter efficiency is also improved by 2.2X. Second, we show that architectural techniques such as parallelization cause the S-MEOP to approach C-MEOP. Thus, it is sufficient to track C-MEOP — a much easier task on-chip — in order to account for process variations. We show that DC-DC converter losses reduces in subthreshold region but increases in superthreshold region when parallelization is employed. This observation leads us to propose a reconfigurable core architecture that improves the converter efficiency by 2.3X at C-MEOP, and makes energy consumption at S-MEOP and C-MEOP to be within 4% of each other, while improving throughput in the subthreshold region by at least 8X. Finally, we show that pipelining, which has been proposed to decrease core energy at C-MEOP while improving throughput [1], adversely affects the S-MEOP. The pipelined-core system energy at S-MEOP is 85% lower than the pipelined-core system energy when operating at the C-MEOP voltage V∗C.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The operability of a portable embedded system is severely constrained by its supply's duration. We propose a novel energy management strategy for a combined (hybrid) supply consisting of a battery and a set of supercapacitors to extend the system's lifetime. Batteries are not sufficient for handling high load fluctuations and demands in modern complex systems. Supercapacitors hold promise for complementing battery supplies because they possess higher power density, a larger number of charge/recharge cycles, and less sensitivity to operational conditions. However, supercapacitors are not efficient as a standalone supply because of their comparatively higher leakage and lower energy density. Due to the nonlinearity of the hybrid supply elements, multiplicity of the possible supply states, and the stochastic nature of the workloads, deriving an optimal management policy is a challenge. We pose this problem as a stochastic Markov Decision Process (MDP) and develop a reinforcement learning method, called Q-learning, to derive an efficient approximation for the optimal management strategy. This method studies a diverse set of workload profiles for a mobile platform and learns the best policy in form of an adaptive approximation approach. Evaluations on measurements collected from mobile phone users show the effectiveness of our proposed method in maximizing the combined energy system's lifetime.
{"title":"Learning to manage combined energy supply systems","authors":"Azalia Mirhoseini, F. Koushanfar","doi":"10.5555/2016802.2016856","DOIUrl":"https://doi.org/10.5555/2016802.2016856","url":null,"abstract":"The operability of a portable embedded system is severely constrained by its supply's duration. We propose a novel energy management strategy for a combined (hybrid) supply consisting of a battery and a set of supercapacitors to extend the system's lifetime. Batteries are not sufficient for handling high load fluctuations and demands in modern complex systems. Supercapacitors hold promise for complementing battery supplies because they possess higher power density, a larger number of charge/recharge cycles, and less sensitivity to operational conditions. However, supercapacitors are not efficient as a standalone supply because of their comparatively higher leakage and lower energy density. Due to the nonlinearity of the hybrid supply elements, multiplicity of the possible supply states, and the stochastic nature of the workloads, deriving an optimal management policy is a challenge. We pose this problem as a stochastic Markov Decision Process (MDP) and develop a reinforcement learning method, called Q-learning, to derive an efficient approximation for the optimal management strategy. This method studies a diverse set of workload profiles for a mobile platform and learns the best policy in form of an adaptive approximation approach. Evaluations on measurements collected from mobile phone users show the effectiveness of our proposed method in maximizing the combined energy system's lifetime.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993643
K. Usami, Yuya Goto, Kensaku Matsunaga, S. Koyama, D. Ikebuchi, H. Amano, Hiroshi Nakamura
In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%–17% difference from that of the conventional simulation-based off-line technique.
{"title":"On-chip detection methodology for break-even time of power gated function units","authors":"K. Usami, Yuya Goto, Kensaku Matsunaga, S. Koyama, D. Ikebuchi, H. Amano, Hiroshi Nakamura","doi":"10.1109/ISLPED.2011.5993643","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993643","url":null,"abstract":"In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%–17% difference from that of the conventional simulation-based off-line technique.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128273737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993653
J. Ryan, Sudhanshu Khanna, B. Calhoun
This paper presents a model for the exact distribution of performance yield in an SRAM using order statistics for strobed and non-strobed sense amplifier (SA) implementations. Monte-Carlo simulation results validate the model, which offers a speedup in runtime of 3 to 4 orders of magnitude. Using the model, we quantify the potential benefits of using a non-strobed SA in different types of system architectures.
{"title":"An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal","authors":"J. Ryan, Sudhanshu Khanna, B. Calhoun","doi":"10.1109/ISLPED.2011.5993653","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993653","url":null,"abstract":"This paper presents a model for the exact distribution of performance yield in an SRAM using order statistics for strobed and non-strobed sense amplifier (SA) implementations. Monte-Carlo simulation results validate the model, which offers a speedup in runtime of 3 to 4 orders of magnitude. Using the model, we quantify the potential benefits of using a non-strobed SA in different types of system architectures.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133599213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993673
Yibo Chen, E. Kursun, D. Motschman, C. Johnson, Yuan Xie
The three-dimensional integrated circuits (3D ICs) offer performance advantages thanks to the increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers). TSV farms can cause different thermal effects on different layers due to the unequal x, y, z thermal conductivities. This can exhibit itself as thermal improvement in the vertical heat flow, at the same time lateral heat blockage effects in thinned pass-through layers. In this paper, we propose a thermal-aware via farm placement technique for 3D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.
三维集成电路(3D ic)提供了性能优势，这要归功于通过硅孔结构(tsv)增加的带宽和缩短的线长。传统上认为热导膜在垂直方向上可以改善导热性。然而，横向热阻塞效应对于TSV通孔场(用于层间信号总线连接的TSV通孔簇)变得越来越重要。由于x, y, z热传导率不等，TSV电场在不同层上产生不同的热效应。这可以在垂直热流中表现为热改善，同时在薄透层中表现为侧向热阻塞效应。在本文中，我们提出了一种热感知的通过农场放置技术，用于3D集成电路，以减少由密集的信号总线TSV结构引起的侧向热阻塞。通过在设计流程中结合导通区块的导热曲线，并实现布局/宽高比优化，可以在导线长度和面积限制下将相应的热点最小化。
{"title":"Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs","authors":"Yibo Chen, E. Kursun, D. Motschman, C. Johnson, Yuan Xie","doi":"10.1109/ISLPED.2011.5993673","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993673","url":null,"abstract":"The three-dimensional integrated circuits (3D ICs) offer performance advantages thanks to the increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers). TSV farms can cause different thermal effects on different layers due to the unequal x, y, z thermal conductivities. This can exhibit itself as thermal improvement in the vertical heat flow, at the same time lateral heat blockage effects in thinned pass-through layers. In this paper, we propose a thermal-aware via farm placement technique for 3D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. By incorporating thermal conductivity profile of via farm blocks in the design flow and enabling placement/aspect ratio optimization, the corresponding hotspots can be minimized within the wire-length and area constraints.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：