Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993655
P. Hsiu, Chun-Han Lin, C. Hsieh
With the increasing variety of mobile applications, reducing the energy consumption of mobile devices is a major challenge in sustaining multimedia streaming applications. This paper explores backlight scaling, which is deemed a promising technical solution. First, we model the problem as a dynamic backlight scaling optimization problem. The objective is to minimize the energy consumption of the backlight when displaying a video stream without adversely impacting the user's visual perception. Then, we propose a dynamic-programming algorithm to solve the fundamental problem and prove its optimality in terms of energy savings. Finally, based on the algorithm, we consider implementation issues. We have also developed a prototype implementation integrated with existing video streaming services to validate the practicability of the approach. The results of experiments conducted to demonstrate the efficacy of the proposed algorithm are very encouraging.
{"title":"Dynamic backlight scaling optimization for mobile streaming applications","authors":"P. Hsiu, Chun-Han Lin, C. Hsieh","doi":"10.1109/ISLPED.2011.5993655","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993655","url":null,"abstract":"With the increasing variety of mobile applications, reducing the energy consumption of mobile devices is a major challenge in sustaining multimedia streaming applications. This paper explores backlight scaling, which is deemed a promising technical solution. First, we model the problem as a dynamic backlight scaling optimization problem. The objective is to minimize the energy consumption of the backlight when displaying a video stream without adversely impacting the user's visual perception. Then, we propose a dynamic-programming algorithm to solve the fundamental problem and prove its optimality in terms of energy savings. Finally, based on the algorithm, we consider implementation issues. We have also developed a prototype implementation integrated with existing video streaming services to validate the practicability of the approach. The results of experiments conducted to demonstrate the efficacy of the proposed algorithm are very encouraging.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993608
Kee-sup Kim
Low power technology, especially for SoC's has been developed first to extend battery life, to manage heat and then to reduce overall consumption of electricity. To achieve best result, chip-centric and low power centric solutions can be very limiting. More holistic approach would span product planning, application, architecture, physical design, library and process technology. Furthermore, co-optimizing low power solutions with the solutions for other axis such as reliability, speed and process variability can lead to surprisingly rewarding results. This talk will also explore where else low power technology developed for the semiconductor industry can be applied.
{"title":"Holistic low power solutions for the new world","authors":"Kee-sup Kim","doi":"10.1109/ISLPED.2011.5993608","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993608","url":null,"abstract":"Low power technology, especially for SoC's has been developed first to extend battery life, to manage heat and then to reduce overall consumption of electricity. To achieve best result, chip-centric and low power centric solutions can be very limiting. More holistic approach would span product planning, application, architecture, physical design, library and process technology. Furthermore, co-optimizing low power solutions with the solutions for other axis such as reliability, speed and process variability can lead to surprisingly rewarding results. This talk will also explore where else low power technology developed for the semiconductor industry can be applied.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125269243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993644
Karthik Swaminathan, Emre Kultursay, V. Saripalli, N. Vijaykrishnan, M. Kandemir, S. Datta
Energy-Delay-Product-aware DVFS is a widely-used technique that improves energy efficiency by dynamically adjusting the frequencies of cores. Further, for multithreaded applications, barrier-aware DVFS is a method that can dynamically tune the frequencies of cores to reduce barrier stall times and achieve higher energy efficiency. In both forms of DVFS, frequencies of cores are reduced from the maximum value to achieve better energy efficiency. TFET devices operate at energy efficiencies that cannot be achieved by CMOS devices. This advantage of TFET devices can be exploited in the context of multicore processors by replacing some of the CMOS cores with energy efficient TFET alternatives. However, the energy benefits of TFET devices are observed at relatively lower voltages, which results in a degradation in performance due to executing at lower frequencies. Although applications cannot be limited to run always at such lower frequencies, it can be significantly beneficial from an energy efficiency perspective to make use of energy efficient TFET cores during the times applications spend at these frequencies. In this paper, we show that due to EDP-aware DVFS and barrier-aware DVFS, multithreaded applications run for a significant portion of their execution time at frequencies at which TFET cores are more energy efficient. We further show that, at those frequencies, dynamically migrating threads to TFET cores can achieve average leakage and dynamic energy savings of 30% and 17%, respectively, with a performance degradation of less than 1%.
{"title":"Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores","authors":"Karthik Swaminathan, Emre Kultursay, V. Saripalli, N. Vijaykrishnan, M. Kandemir, S. Datta","doi":"10.1109/ISLPED.2011.5993644","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993644","url":null,"abstract":"Energy-Delay-Product-aware DVFS is a widely-used technique that improves energy efficiency by dynamically adjusting the frequencies of cores. Further, for multithreaded applications, barrier-aware DVFS is a method that can dynamically tune the frequencies of cores to reduce barrier stall times and achieve higher energy efficiency. In both forms of DVFS, frequencies of cores are reduced from the maximum value to achieve better energy efficiency. TFET devices operate at energy efficiencies that cannot be achieved by CMOS devices. This advantage of TFET devices can be exploited in the context of multicore processors by replacing some of the CMOS cores with energy efficient TFET alternatives. However, the energy benefits of TFET devices are observed at relatively lower voltages, which results in a degradation in performance due to executing at lower frequencies. Although applications cannot be limited to run always at such lower frequencies, it can be significantly beneficial from an energy efficiency perspective to make use of energy efficient TFET cores during the times applications spend at these frequencies. In this paper, we show that due to EDP-aware DVFS and barrier-aware DVFS, multithreaded applications run for a significant portion of their execution time at frequencies at which TFET cores are more energy efficient. We further show that, at those frequencies, dynamically migrating threads to TFET cores can achieve average leakage and dynamic energy savings of 30% and 17%, respectively, with a performance degradation of less than 1%.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993654
S. P. Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. P. Griffin, K. Roy
In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from 120MHZ@0.48V to 710MHz@1V) for the proposed SRAM array.
{"title":"Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors","authors":"S. P. Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. P. Griffin, K. Roy","doi":"10.1109/ISLPED.2011.5993654","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993654","url":null,"abstract":"In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from 120MHZ@0.48V to 710MHz@1V) for the proposed SRAM array.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127855408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993611
A. Jadidi, M. Arjomand, H. Sarbazi-Azad
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache architecture has large capacity and consumes near zero leakage energy using STT-RAM array; while dynamic write energy, acceptable write latency, and long lifetime is guaranteed via SRAM array. Results of full-system simulation for a quad-core CMP running PARSEC-2 benchmark suit confirm an average of 49 times improvement in cache lifetime and more than 50% reduction in cache power consumption when compared to baseline configurations.
{"title":"High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement","authors":"A. Jadidi, M. Arjomand, H. Sarbazi-Azad","doi":"10.1109/ISLPED.2011.5993611","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993611","url":null,"abstract":"In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache architecture has large capacity and consumes near zero leakage energy using STT-RAM array; while dynamic write energy, acceptable write latency, and long lifetime is guaranteed via SRAM array. Results of full-system simulation for a quad-core CMP running PARSEC-2 benchmark suit confirm an average of 49 times improvement in cache lifetime and more than 50% reduction in cache power consumption when compared to baseline configurations.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125941795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X.
{"title":"Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits","authors":"Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang","doi":"10.1109/ISLPED.2011.5993626","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993626","url":null,"abstract":"Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122353432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993658
Xin Fan, S. Kusakabe
This paper investigates the effectiveness of Time Aggregation Scheduler (TAS) for commodity platforms from the view point of energy saving. TAS can aggregate the execution of runnable sibling threads, and decrease the number of internal events that have negative impact on energy consumption in executing multithreaded applications. We compare energy consumption in running multithreaded applications of DaCapo Java benchmarks when using Linux default Completely Fair Scheduler, and TAS. The experimental results indicate that TAS can reduce the amount of system level energy consumption, as well as the quantity of internal events and the execution time.
{"title":"Energy efficient scheduling for multithreaded programs on general-purpose processors","authors":"Xin Fan, S. Kusakabe","doi":"10.1109/ISLPED.2011.5993658","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993658","url":null,"abstract":"This paper investigates the effectiveness of Time Aggregation Scheduler (TAS) for commodity platforms from the view point of energy saving. TAS can aggregate the execution of runnable sibling threads, and decrease the number of internal events that have negative impact on energy consumption in executing multithreaded applications. We compare energy consumption in running multithreaded applications of DaCapo Java benchmarks when using Linux default Completely Fair Scheduler, and TAS. The experimental results indicate that TAS can reduce the amount of system level energy consumption, as well as the quantity of internal events and the execution time.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134254621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993637
Po-Hsun Wu, Tsung-Yi Ho
As the number of buses in multi-core SoC designs increase, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, those proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots which result in high chip temperature on the chip. In this paper, a thermal-aware bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles which are the thermal distribution of each module is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplan-ner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — Placement and Routing General Terms: Algorithms, Design
{"title":"Thermal-aware bus-driven floorplanning","authors":"Po-Hsun Wu, Tsung-Yi Ho","doi":"10.1109/ISLPED.2011.5993637","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993637","url":null,"abstract":"As the number of buses in multi-core SoC designs increase, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, those proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots which result in high chip temperature on the chip. In this paper, a thermal-aware bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles which are the thermal distribution of each module is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplan-ner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids — Placement and Routing General Terms: Algorithms, Design","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129544274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993642
Sehwan Kim, P. Chou
EscaCap is an energy harvester that uses a boost-up charge pump to perform maximum power-transfer tracking (MPTT) while charging a reservoir supercapacitor array (RSA) with a reconfigurable topology. Unlike buck-down type harvesters, the voltage-doubling charge pump of EscaCap enables the sensor nodes to operate under low ambient power conditions. The supercapacitors in the RSA can be dynamically configured for series or parallel topologies by means of a switch array for not only minimizing leakage of the supercapacitors but also improving the charging speed. Furthermore, the RSA of EscaCap is modular and can be easily expanded. Experimental results show that EscaCap can harvest energy efficiently under low and high solar irradiation conditions, achieve shorter charging time, and demonstrate flexibility and robustness.
{"title":"Energy harvesting by sweeping voltage-escalated charging of a reconfigurable supercapacitor array","authors":"Sehwan Kim, P. Chou","doi":"10.1109/ISLPED.2011.5993642","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993642","url":null,"abstract":"EscaCap is an energy harvester that uses a boost-up charge pump to perform maximum power-transfer tracking (MPTT) while charging a reservoir supercapacitor array (RSA) with a reconfigurable topology. Unlike buck-down type harvesters, the voltage-doubling charge pump of EscaCap enables the sensor nodes to operate under low ambient power conditions. The supercapacitors in the RSA can be dynamically configured for series or parallel topologies by means of a switch array for not only minimizing leakage of the supercapacitors but also improving the charging speed. Furthermore, the RSA of EscaCap is modular and can be easily expanded. Experimental results show that EscaCap can harvest energy efficiently under low and high solar irradiation conditions, achieve shorter charging time, and demonstrate flexibility and robustness.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123498856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-08-01DOI: 10.1109/ISLPED.2011.5993662
Sunkwon Kim, J. Woo, Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Hyunjoong Lee, Suhwan Kim
This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.
{"title":"A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications","authors":"Sunkwon Kim, J. Woo, Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Hyunjoong Lee, Suhwan Kim","doi":"10.1109/ISLPED.2011.5993662","DOIUrl":"https://doi.org/10.1109/ISLPED.2011.5993662","url":null,"abstract":"This paper proposes a low-power referenceless clock and data recovery (CDR) circuit for biomedical devices or sensor applications. Its power consumption is reduced by adopting clock-edge modulation technique and using a voltage-controlled oscillator (VCO) based on a relaxation oscillator. Clock-edge modulation eliminates the need for an external reference clock without introducing the possibility of harmonic locking. Our CDR supports input data-rates between 200kbps and 10Mbps at 0.7V, and operate up to 24 MHz at 1.0V. The circuit is designed in a 0.18μm CMOS technology and consumes 8μW at an input data-rate of 10Mbps.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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