Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486382
R. Schlor
Surveys a self-contained part of the ESPRIT-project "FORMAT", which develops a prover for VHDL-based hardware design. Notable is the use of a graphical specification language called STD (Symbolic Timing Diagrams), which can be seen as a visual dialect of temporal logic. The heart of the prover is built by two powerful industrial verification tools: A (compositional) symbolic model checker (developed by SIEMENS), and the LAMBDA-theorem prover (developed by AHL). The aim of this paper is to describe (1) the various tools integrated in the prover, (2) the graphical specification language STD with its associated design methodology, and (3) to explain how proofs about generic (parameterized) designs are performed in the prover, using a combination of automatic and interactive reasoning.
{"title":"A prover for VHDL-based hardware design","authors":"R. Schlor","doi":"10.1109/ASPDAC.1995.486382","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486382","url":null,"abstract":"Surveys a self-contained part of the ESPRIT-project \"FORMAT\", which develops a prover for VHDL-based hardware design. Notable is the use of a graphical specification language called STD (Symbolic Timing Diagrams), which can be seen as a visual dialect of temporal logic. The heart of the prover is built by two powerful industrial verification tools: A (compositional) symbolic model checker (developed by SIEMENS), and the LAMBDA-theorem prover (developed by AHL). The aim of this paper is to describe (1) the various tools integrated in the prover, (2) the graphical specification language STD with its associated design methodology, and (3) to explain how proofs about generic (parameterized) designs are performed in the prover, using a combination of automatic and interactive reasoning.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115742350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486369
W. Wolf
This paper describes a new co-synthesis algorithm which synthesizes a distributed processing engine of arbitrary topology and the application software it executes from an object-oriented specification. Process partitioning is an especially important optimization for such systems because the specification will not in general take into account the process structure required for efficient execution on the distributed engine. Our algorithm takes advantage of the structure of the object-oriented specification to simultaneously partition, allocate, schedule, and map the required function to satisfy performance constraints and minimize costs. Experimental results show that our algorithm provides good results in reasonable CPU times.
{"title":"Object-oriented co-synthesis of distributed embedded systems","authors":"W. Wolf","doi":"10.1109/ASPDAC.1995.486369","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486369","url":null,"abstract":"This paper describes a new co-synthesis algorithm which synthesizes a distributed processing engine of arbitrary topology and the application software it executes from an object-oriented specification. Process partitioning is an especially important optimization for such systems because the specification will not in general take into account the process structure required for efficient execution on the distributed engine. Our algorithm takes advantage of the structure of the object-oriented specification to simultaneously partition, allocate, schedule, and map the required function to satisfy performance constraints and minimize costs. Experimental results show that our algorithm provides good results in reasonable CPU times.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127431835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486392
C. Bolchini, R. Montandon, F. Salice, D. Sciuto
The design of self-checking FSMs can be achieved by adopting an encoding for the state, for the output or for both. In this paper a state encoding in which the Hamming distance between each state and its possible next states is constant is proposed. The adoption of such an encoding and the application of specific techniques for achieving a complete fault detection property for faults occurring in the next-state logic are presented. Area overhead and fault coverage results on a set of MCNC benchmark FSMs are provided.
{"title":"A state encoding for self-checking finite state machines","authors":"C. Bolchini, R. Montandon, F. Salice, D. Sciuto","doi":"10.1109/ASPDAC.1995.486392","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486392","url":null,"abstract":"The design of self-checking FSMs can be achieved by adopting an encoding for the state, for the output or for both. In this paper a state encoding in which the Hamming distance between each state and its possible next states is constant is proposed. The adoption of such an encoding and the application of specific techniques for achieving a complete fault detection property for faults occurring in the next-state logic are presented. Area overhead and fault coverage results on a set of MCNC benchmark FSMs are provided.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125587595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486409
P. Tzionas, P. Tsalides, A. Thanailakis
This paper presents a new parallel algorithm for collision-free path planning of a diamond-shaped robot among arbitrarily-shaped obstacles and its implementation in VLSI. The proposed algorithm is based on the computational geometry concept known as the "Voronoi diagram", which is constructed through the time evolution of Cellular Automata, after an initial phase during which the boundaries of obstacles are identified and coded with respect to their orientation.
{"title":"Cellular automata-based collision-free robot path planning","authors":"P. Tzionas, P. Tsalides, A. Thanailakis","doi":"10.1109/ASPDAC.1995.486409","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486409","url":null,"abstract":"This paper presents a new parallel algorithm for collision-free path planning of a diamond-shaped robot among arbitrarily-shaped obstacles and its implementation in VLSI. The proposed algorithm is based on the computational geometry concept known as the \"Voronoi diagram\", which is constructed through the time evolution of Cellular Automata, after an initial phase during which the boundaries of obstacles are identified and coded with respect to their orientation.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486399
S. Katkoori, Nand Kumar, L. Rader, R. Vemuri
A profile driven approach to behavioral synthesis is presented. For a given design and a set of input vectors, the switching activity in the design yields a measure of the power consumption. Every module in a parameterized module library is characterized by its average switching activity per input vector. For a given behavioral specification, simulation using user specified inputs is carried out to collect the profile data of various operations and carriers in the specification. In the performance estimation phase, the profile data with the switching activity data in the precharacterized module library is used to estimate the average switching activity of all the module sets meeting other user specified constraints such as area and delay. The module set with the least estimated switching activity is further synthesized. Experimental results show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.
{"title":"A profile driven approach for low power synthesis","authors":"S. Katkoori, Nand Kumar, L. Rader, R. Vemuri","doi":"10.1109/ASPDAC.1995.486399","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486399","url":null,"abstract":"A profile driven approach to behavioral synthesis is presented. For a given design and a set of input vectors, the switching activity in the design yields a measure of the power consumption. Every module in a parameterized module library is characterized by its average switching activity per input vector. For a given behavioral specification, simulation using user specified inputs is carried out to collect the profile data of various operations and carriers in the specification. In the performance estimation phase, the profile data with the switching activity data in the precharacterized module library is used to estimate the average switching activity of all the module sets meeting other user specified constraints such as area and delay. The module set with the least estimated switching activity is further synthesized. Experimental results show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132243521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486398
Lars Skovby Nielsen
This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented.
{"title":"Design and verification of a self-timed RAM","authors":"Lars Skovby Nielsen","doi":"10.1109/ASPDAC.1995.486398","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486398","url":null,"abstract":"This paper describes a self-timed static RAM. A single bit RAM is described in the design language SYNCHRONIZED TRANSITIONS and using the verification tools supporting this language, it is shown that the design is speed-independent. Furthermore, a transistor level implementation of the design is presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486388
Yanbing Li, M. Leeser
HML (Hardware ML) is an innovative hardware description language based on the functional programming language SML. HML is a high-order language with polymorphic types. It uses advanced type checking and type inference techniques. We have implemented an HML type checker and a translator to VHDL. We generate a synthesizable subset of VHDL and automatically infer types and interfaces. This paper gives an overview of HML and discusses its typechecking techniques and the translation from HML to VHDL. We present a non-restoring integer square-root example to illustrate the HML system.
{"title":"HML: an innovative hardware description language and its translation to VHDL","authors":"Yanbing Li, M. Leeser","doi":"10.1109/ASPDAC.1995.486388","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486388","url":null,"abstract":"HML (Hardware ML) is an innovative hardware description language based on the functional programming language SML. HML is a high-order language with polymorphic types. It uses advanced type checking and type inference techniques. We have implemented an HML type checker and a translator to VHDL. We generate a synthesizable subset of VHDL and automatically infer types and interfaces. This paper gives an overview of HML and discusses its typechecking techniques and the translation from HML to VHDL. We present a non-restoring integer square-root example to illustrate the HML system.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123318384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486394
B. Falkowski, Chip-Hong Chang
Methods of generating forward and inverse transformation kernels for generalized arithmetic and adding transforms are presented. Different methods of generation of transformation matrices in arbitrary polarities from a transformation matrix in some polarity are developed. Mutual relations among transformation matrices and spectra for arbitrary polarities are also investigated. A unified approach to the fast arithmetic and adding algorithms based on the representation of transform matrices in the form of layered Kronecker matrices is developed.
{"title":"Fast generalized arithmetic and adding transforms","authors":"B. Falkowski, Chip-Hong Chang","doi":"10.1109/ASPDAC.1995.486394","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486394","url":null,"abstract":"Methods of generating forward and inverse transformation kernels for generalized arithmetic and adding transforms are presented. Different methods of generation of transformation matrices in arbitrary polarities from a transformation matrix in some polarity are developed. Mutual relations among transformation matrices and spectra for arbitrary polarities are also investigated. A unified approach to the fast arithmetic and adding algorithms based on the representation of transform matrices in the form of layered Kronecker matrices is developed.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121527239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486404
A. Tsutsui, T. Miyazaki
We introduce a CAD system for the original FPGA "PROTEUS", which has several features suitable for the efficient realization of practical digital transport processing systems. These features are considered in the design of the CAD system. Our CAD system supports both automatic and manual design environments. The automatic design environment offers complete top down design from high level hardware description to downloading the programming data into the FPGA. In the manual design environment, an interactive chip editor is provided that enables high performance circuits to be constructed skillfully. The paper introduces our design strategy and the algorithms that realize them.
{"title":"An efficient design environment and algorithms for transport processing FPGA","authors":"A. Tsutsui, T. Miyazaki","doi":"10.1109/ASPDAC.1995.486404","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486404","url":null,"abstract":"We introduce a CAD system for the original FPGA \"PROTEUS\", which has several features suitable for the efficient realization of practical digital transport processing systems. These features are considered in the design of the CAD system. Our CAD system supports both automatic and manual design environments. The automatic design environment offers complete top down design from high level hardware description to downloading the programming data into the FPGA. In the manual design environment, an interactive chip editor is provided that enables high performance circuits to be constructed skillfully. The paper introduces our design strategy and the algorithms that realize them.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486400
R. Fried, R. Holzer
The high frequency oscillator is one of the major causes of both high power consumption and high Electro Magnetic Interference (EMI) in embedded systems (ES). The paper presents a high frequency oscillator circuit that reduces substantially both power consumption and EMI, compared to high frequency oscillators currently in use. Using this oscillator spares the need for special isolation techniques used to reduce EMI in ES. It further saves the need for an additional low frequency oscillator that is used for reducing power consumption. The oscillator is designed for frequencies in the range of 10-60 MHz. It consumes typically 350 uA at 40.96 MHz with a 5 V power supply.
{"title":"Low power and very low EMI, high efficiency, high frequency crystal oscillator","authors":"R. Fried, R. Holzer","doi":"10.1109/ASPDAC.1995.486400","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486400","url":null,"abstract":"The high frequency oscillator is one of the major causes of both high power consumption and high Electro Magnetic Interference (EMI) in embedded systems (ES). The paper presents a high frequency oscillator circuit that reduces substantially both power consumption and EMI, compared to high frequency oscillators currently in use. Using this oscillator spares the need for special isolation techniques used to reduce EMI in ES. It further saves the need for an additional low frequency oscillator that is used for reducing power consumption. The oscillator is designed for frequencies in the range of 10-60 MHz. It consumes typically 350 uA at 40.96 MHz with a 5 V power supply.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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