Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486246
D. Deschacht, C. Dabrin
In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification.
{"title":"A new and accurate interconnection delay time evaluation in a general tree-type network","authors":"D. Deschacht, C. Dabrin","doi":"10.1109/ASPDAC.1995.486246","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486246","url":null,"abstract":"In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126979253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486203
M. Heijligers, L.J.M. Cluitmans, J.A.G. Jess
In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to cover other architectural issues and (for example) provides ways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods.
{"title":"High-level synthesis scheduling and allocation using genetic algorithms","authors":"M. Heijligers, L.J.M. Cluitmans, J.A.G. Jess","doi":"10.1109/ASPDAC.1995.486203","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486203","url":null,"abstract":"In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to cover other architectural issues and (for example) provides ways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124499730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486355
Noriya Kobayashi, S. Malik
In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. The proposed graphical data structure is of size proportional to (m+n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input/output pair has size proportional to m/spl times/n. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m+n).
{"title":"Delay abstraction in combinational logic circuits","authors":"Noriya Kobayashi, S. Malik","doi":"10.1109/ASPDAC.1995.486355","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486355","url":null,"abstract":"In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. The proposed graphical data structure is of size proportional to (m+n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input/output pair has size proportional to m/spl times/n. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m+n).","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486352
Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao
In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications.
{"title":"A hardware-oriented design for weighted median filters","authors":"Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao","doi":"10.1109/ASPDAC.1995.486352","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486352","url":null,"abstract":"In this paper, the design consideration and algorithm mapping for weighted median filters are presented. To achieve high throughput rate, a special coding technique and its dedicated architecture with block processing are constructed to handle multiple filtering inputs and outputs concurrently. The pipelined cycle in our design has the delay time of 1-bit carry-save-adder (CSA). Due to this design strategy, the proposed architecture can support not only weighted median filters but also rank order-based filters in high-speed applications.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486245
S. Yamashita, Y. Kambayashi, S. Muroga
In recent years Field Programmable Gate Arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes due to their low cost, reprogrammability and rapid turnaround times. Therefore, the need for design methods of FPGAs are getting larger and larger. In this paper, two methods to optimize networks which have been mapped for lookup-table-based FPGAs are discussed. These methods utilize the notion of compatible sets of permissible functions (CSPFs) of Transduction Method. Experimental results show the effectiveness of our methods.
{"title":"Optimization methods for lookup-table-based FPGAs using Transduction Method","authors":"S. Yamashita, Y. Kambayashi, S. Muroga","doi":"10.1109/ASPDAC.1995.486245","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486245","url":null,"abstract":"In recent years Field Programmable Gate Arrays (FPGAs) have emerged as an attractive means to implement low volume applications and prototypes due to their low cost, reprogrammability and rapid turnaround times. Therefore, the need for design methods of FPGAs are getting larger and larger. In this paper, two methods to optimize networks which have been mapped for lookup-table-based FPGAs are discussed. These methods utilize the notion of compatible sets of permissible functions (CSPFs) of Transduction Method. Experimental results show the effectiveness of our methods.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130886140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486228
H. Higuchi, Y. Matsunaga
This paper proposes a new implicit algorithm for excluding dominated compatibles. The algorithm utilizes a novel notion of signatures of compatibles to exclude dominated compatibles efficiently. Though this dominance check is weaker than the conventional one, experimental results show that in many cases the number of excluded compatibles is the same as that by class sets. The proposed method computes prime compatibles more efficiently than conventional methods for many tested large ISFSM's.
{"title":"Implicit prime compatible generation for minimizing incompletely specified finite state machines","authors":"H. Higuchi, Y. Matsunaga","doi":"10.1109/ASPDAC.1995.486228","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486228","url":null,"abstract":"This paper proposes a new implicit algorithm for excluding dominated compatibles. The algorithm utilizes a novel notion of signatures of compatibles to exclude dominated compatibles efficiently. Though this dominance check is weaker than the conventional one, experimental results show that in many cases the number of excluded compatibles is the same as that by class sets. The proposed method computes prime compatibles more efficiently than conventional methods for many tested large ISFSM's.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486194
How-Rern Lin, TingTing Hwang
This paper describes methods for reducing power consumption. We propose using gate sizing technique to reduce power for circuits that have already satisfied the timing constraint. Replacement of gates on noncritical paths with smaller templates is used in reducing the dissipated power of a circuit. We find that not only gates on noncritical paths can be down-sized, but also gates on critical paths can be down-sized. A power reduction algorithm by means of single gate resizing as well as multiple gates resizing will be proposed. In addition, to identify gates to be resized, a path-oriented method in calculating slack time with false path taken into consideration will be also proposed. During the slack time computation, in order to prevent long false path from becoming sensitizable and thus increasing the circuit delay, slack constraint will be set for gales. Results on a set of circuits from MCNC benchmark set demonstrate that our power reduction algorithm can reduce about 10% more power, on the average, than a previously proposed gate sizing algorithm.
{"title":"Power reduction by gate sizing with path-oriented slack calculation","authors":"How-Rern Lin, TingTing Hwang","doi":"10.1109/ASPDAC.1995.486194","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486194","url":null,"abstract":"This paper describes methods for reducing power consumption. We propose using gate sizing technique to reduce power for circuits that have already satisfied the timing constraint. Replacement of gates on noncritical paths with smaller templates is used in reducing the dissipated power of a circuit. We find that not only gates on noncritical paths can be down-sized, but also gates on critical paths can be down-sized. A power reduction algorithm by means of single gate resizing as well as multiple gates resizing will be proposed. In addition, to identify gates to be resized, a path-oriented method in calculating slack time with false path taken into consideration will be also proposed. During the slack time computation, in order to prevent long false path from becoming sensitizable and thus increasing the circuit delay, slack constraint will be set for gales. Results on a set of circuits from MCNC benchmark set demonstrate that our power reduction algorithm can reduce about 10% more power, on the average, than a previously proposed gate sizing algorithm.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"23 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486200
V. Moshnyaga, F. Ohbayashi, K. Tamaru
Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.
{"title":"A scheduling algorithm for synthesis of bus-partitioned architectures","authors":"V. Moshnyaga, F. Ohbayashi, K. Tamaru","doi":"10.1109/ASPDAC.1995.486200","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486200","url":null,"abstract":"Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486225
A. Motohara, S. Takeoka, Toshinori Hosokawa, M. Ohta, Yuji Takai, M. Matsumoto, M. Muraoka
An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.
{"title":"Design for testability using register-transfer level partial scan selection","authors":"A. Motohara, S. Takeoka, Toshinori Hosokawa, M. Ohta, Yuji Takai, M. Matsumoto, M. Muraoka","doi":"10.1109/ASPDAC.1995.486225","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486225","url":null,"abstract":"An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129852724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-01DOI: 10.1109/ASPDAC.1995.486219
Jong Tae Lee, Jaemin Kim, Jae-Cheol Son
This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC.
{"title":"Architectural simulation for a programmable DSP chip set","authors":"Jong Tae Lee, Jaemin Kim, Jae-Cheol Son","doi":"10.1109/ASPDAC.1995.486219","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486219","url":null,"abstract":"This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131969497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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