Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486413
Jin-Tai Yan
In this paper, a unified probabilistic-based estimation is firstly proposed for different kinds of channels. Furthermore, based on the estimation of channels, one safe routing space assignment is proposed to obtain a complete macro cell placement, and the time complexities of the safe routing space assignment is analyzed to be O(NlogN), where N is the number of macro cells in a macro cell placement. Finally, the experimental results show that the proposed approach has better accuracy for the assignment of routing space.
{"title":"Routing space estimation and safe assignment for macro cell placement","authors":"Jin-Tai Yan","doi":"10.1109/ASPDAC.1995.486413","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486413","url":null,"abstract":"In this paper, a unified probabilistic-based estimation is firstly proposed for different kinds of channels. Furthermore, based on the estimation of channels, one safe routing space assignment is proposed to obtain a complete macro cell placement, and the time complexities of the safe routing space assignment is analyzed to be O(NlogN), where N is the number of macro cells in a macro cell placement. Finally, the experimental results show that the proposed approach has better accuracy for the assignment of routing space.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115034060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486385
Kathi Fisler, Steven D. Johnson
Formal methods and verification tools are difficult for designers to use. Research has been concentrated on handling large proofs; meanwhile, insufficient attention has been paid to the reasoning process. We argue that a heterogeneous logic supporting hardware diagrams and sentential logic provides a natural framework for reasoning and for the formal integration of design and verification environments. We present such a logic and demonstrate its flexibility on fragments of a traffic light controller design and verification problem.
{"title":"Integrating design and verification environments through a logic supporting hardware diagrams","authors":"Kathi Fisler, Steven D. Johnson","doi":"10.1109/ASPDAC.1995.486385","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486385","url":null,"abstract":"Formal methods and verification tools are difficult for designers to use. Research has been concentrated on handling large proofs; meanwhile, insufficient attention has been paid to the reasoning process. We argue that a heterogeneous logic supporting hardware diagrams and sentential logic provides a natural framework for reasoning and for the formal integration of design and verification environments. We present such a logic and demonstrate its flexibility on fragments of a traffic light controller design and verification problem.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"6 Sect Hist Med 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116539922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486384
W. Grass, C. Grobe, S. Lenk, Wolf-Dieter Tiedemann, C. D. Kloos, A. Marin, T. Robles
Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits. In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench. By giving timing diagrams a formal semantics in terms of T-LOTOS, we can apply optimizing correctness-preserving transformation steps. In order to produce good VHDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given specification. The designer is rather asked to assist in introducing a structure by applying a bottom-up interactive synthesis procedure.
{"title":"Transformation of timing diagram specifications into VHDL code","authors":"W. Grass, C. Grobe, S. Lenk, Wolf-Dieter Tiedemann, C. D. Kloos, A. Marin, T. Robles","doi":"10.1109/ASPDAC.1995.486384","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486384","url":null,"abstract":"Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits. In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench. By giving timing diagrams a formal semantics in terms of T-LOTOS, we can apply optimizing correctness-preserving transformation steps. In order to produce good VHDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given specification. The designer is rather asked to assist in introducing a structure by applying a bottom-up interactive synthesis procedure.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486403
E. Domenis, E. Filippi, L. Licciardi, M. Paolini, M. Turolla, D. Rouquier
A flexible synthesis library for fast and safe prototyping of VLSI circuits for telecom applications is presented. Library modules are described in VHDL so as to be portable in different CAD frameworks and easily usable by IC and system designers. Module flexibility is achieved by using generic parameter programming; mapping can be done on FPGAs, semicustom and cell based CMOS libraries. Modules can reach several thousand gates in size and a target frequency of 40 MHz for a CMOS semicustom design. A VLSI MPEG1 audio decoder developed as a methodology test vehicle is finally detailed.
{"title":"Fast prototyping for telecom components using a synthesizeable VHDL flexible library","authors":"E. Domenis, E. Filippi, L. Licciardi, M. Paolini, M. Turolla, D. Rouquier","doi":"10.1109/ASPDAC.1995.486403","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486403","url":null,"abstract":"A flexible synthesis library for fast and safe prototyping of VLSI circuits for telecom applications is presented. Library modules are described in VHDL so as to be portable in different CAD frameworks and easily usable by IC and system designers. Module flexibility is achieved by using generic parameter programming; mapping can be done on FPGAs, semicustom and cell based CMOS libraries. Modules can reach several thousand gates in size and a target frequency of 40 MHz for a CMOS semicustom design. A VLSI MPEG1 audio decoder developed as a methodology test vehicle is finally detailed.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128071155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486383
W. Mueller, G. Lehrenfeld, C. Tahedl
This article discusses the application of Pictorial Janus (PJ) for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we first extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We finally give the example of the specification and animation of a non interlocked protocol.
{"title":"Complete visual specification and animation of protocols","authors":"W. Mueller, G. Lehrenfeld, C. Tahedl","doi":"10.1109/ASPDAC.1995.486383","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486383","url":null,"abstract":"This article discusses the application of Pictorial Janus (PJ) for the rapid development and analysis of protocols by animation and complete visualization. In order to make PJ applicable in the context of hardware description we first extend PJ by timing facilities (Timed PJ) and introduce an approach for integrating VHDL models into this visual framework preserving the simulation semantics of VHDL. We finally give the example of the specification and animation of a non interlocked protocol.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486364
M. Romdhani, R.P. Hautbois, A. Jeffroy, P. de Chazelles, A. Jerraya
This paper deals with experience with specification languages at AEROSPATIALE Aircraft, Systems and Avionics Division. We describe first the current avionics development environment. Then, we present our results and viewpoints on the use of the three specification languages: LOTOS, ESTEREL, and B. The evaluation studies we performed, showed that each of these languages does not cover in a complete way our needs in specification, validation, and development of avionics. Afterwards, we propose and illustrate an investigation approach that allows to structure and compose different formal specification languages in the same environment.
{"title":"Evaluation and composition of specification languages, an industrial point of view","authors":"M. Romdhani, R.P. Hautbois, A. Jeffroy, P. de Chazelles, A. Jerraya","doi":"10.1109/ASPDAC.1995.486364","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486364","url":null,"abstract":"This paper deals with experience with specification languages at AEROSPATIALE Aircraft, Systems and Avionics Division. We describe first the current avionics development environment. Then, we present our results and viewpoints on the use of the three specification languages: LOTOS, ESTEREL, and B. The evaluation studies we performed, showed that each of these languages does not cover in a complete way our needs in specification, validation, and development of avionics. Afterwards, we propose and illustrate an investigation approach that allows to structure and compose different formal specification languages in the same environment.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126465535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486380
H. Barringer, G. Gough, B. Monahan, A. Williams
We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are valid. The approach maintains a high degree of automation while offering the possibility of containing the usual growth in complexity of verification, and can be applied to certain systems which have infinite state-spaces.
{"title":"Symbolic verification of hardware systems","authors":"H. Barringer, G. Gough, B. Monahan, A. Williams","doi":"10.1109/ASPDAC.1995.486380","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486380","url":null,"abstract":"We describe a method for verifying the behavioural equivalence of hardware systems, modelled as deterministic machines, based on the symbolic simulation of the two systems. The state evolution method compares the behaviour of systems at an abstract level, and reduces the problem of checking the behavioural equivalence to one of needing to prove that a set of logical verification conditions are valid. The approach maintains a high degree of automation while offering the possibility of containing the usual growth in complexity of verification, and can be applied to certain systems which have infinite state-spaces.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128988128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486354
H. J. Kahn
Summary form only given. The design and implementation of the EDIF family of standards is based on the use of the specification technique called information modelling. The goal of information modelling is to provide the standards development process with a methodology that will ensure, as far as is possible, that the contents of the standard are correct, consistent and clearly defined. The first part of the paper addresses the high level concepts and goals of information modelling. It looks at the basic mechanisms EXPRESS provides for capturing the essential objects and attributes of a domain and how those objects are inter-related. Above all, it concentrates on how constraints are used to ensure that the information model is explicit and unambiguous. The second part of the presentation focuses on the content of EDIF Version 350 and EDIF Version 400. The general architecture of the new EDIF standard is introduced and used to show how extensions of EDIF into the new domains of PCB and MCM are supported. The solutions adopted in EDIF to ensure a representation with minimal context dependency and hence, it is hoped, minimal ambiguity are highlighted.
只提供摘要形式。EDIF系列标准的设计和实现基于称为信息建模的规范技术的使用。信息建模的目标是为标准开发过程提供一种方法，该方法将尽可能确保标准的内容是正确的、一致的和明确定义的。本文的第一部分讨论了信息建模的高级概念和目标。它研究了EXPRESS提供的用于捕获域的基本对象和属性的基本机制，以及这些对象如何相互关联。最重要的是，它集中于如何使用约束来确保信息模型是显式的和明确的。演讲的第二部分重点介绍了EDIF Version 350和EDIF Version 400的内容。介绍了新EDIF标准的一般体系结构，并使用它来说明如何将EDIF扩展到PCB和MCM的新领域。EDIF中采用的解决方案确保表示具有最小的上下文依赖性，因此，希望能够强调最小的模糊性。
{"title":"EDIF Version 350/400 and information modelling","authors":"H. J. Kahn","doi":"10.1109/ASPDAC.1995.486354","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486354","url":null,"abstract":"Summary form only given. The design and implementation of the EDIF family of standards is based on the use of the specification technique called information modelling. The goal of information modelling is to provide the standards development process with a methodology that will ensure, as far as is possible, that the contents of the standard are correct, consistent and clearly defined. The first part of the paper addresses the high level concepts and goals of information modelling. It looks at the basic mechanisms EXPRESS provides for capturing the essential objects and attributes of a domain and how those objects are inter-related. Above all, it concentrates on how constraints are used to ensure that the information model is explicit and unambiguous. The second part of the presentation focuses on the content of EDIF Version 350 and EDIF Version 400. The general architecture of the new EDIF standard is introduced and used to show how extensions of EDIF into the new domains of PCB and MCM are supported. The solutions adopted in EDIF to ensure a representation with minimal context dependency and hence, it is hoped, minimal ambiguity are highlighted.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124539580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486379
R. Hojati, R. Mueller-Thuns, P. Loewenstein, R. Brayton
In a shared memory multi-processor environment, one can achieve greater performance by out-of-order servicing of memory requests. Although this results in higher performance, such systems are complicated and their design and programming requires care. Recently, there have been efforts to develop concise formal specifications of such systems. We present a general strategy, based on the language containment paradigm, to automatically verify such memory systems against their formal specifications. The size of the state space explored during the verification is dependent on the number of data values, length of buffers, number of processors, and number of memory locations. Abstraction is used to reduce the number of data values to just two, and the number of memory locations to a small number without losing any accuracy in our verification. As an example, we concentrate on SPARC's V8 memory model, for which we have built a sample hardware description language model. Experimental results demonstrating the feasibility of our approach are presented.
{"title":"Automatic verification of memory systems which service their requests out of order","authors":"R. Hojati, R. Mueller-Thuns, P. Loewenstein, R. Brayton","doi":"10.1109/ASPDAC.1995.486379","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486379","url":null,"abstract":"In a shared memory multi-processor environment, one can achieve greater performance by out-of-order servicing of memory requests. Although this results in higher performance, such systems are complicated and their design and programming requires care. Recently, there have been efforts to develop concise formal specifications of such systems. We present a general strategy, based on the language containment paradigm, to automatically verify such memory systems against their formal specifications. The size of the state space explored during the verification is dependent on the number of data values, length of buffers, number of processors, and number of memory locations. Abstraction is used to reduce the number of data values to just two, and the number of memory locations to a small number without losing any accuracy in our verification. As an example, we concentrate on SPARC's V8 memory model, for which we have built a sample hardware description language model. Experimental results demonstrating the feasibility of our approach are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115737267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486363
T. Shonai, T. Shimizu
We describe a formal verification algorithm for pipelined and superscalar processors. This algorithm proves the equivalence between a processor's design and its specifications by rewriting recursive functions and using a new type of mathematical induction: extended recursive induction. Partial unfolding makes it possible to derive superscalar specifications from instruction-wise specifications. After the user indicates only selectors in the design, this algorithm can automatically prove correctness. The performance is independent of not only data width but also memory size. Experimental results are also presented.
{"title":"Formal verification of pipelined and superscalar processors","authors":"T. Shonai, T. Shimizu","doi":"10.1109/ASPDAC.1995.486363","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486363","url":null,"abstract":"We describe a formal verification algorithm for pipelined and superscalar processors. This algorithm proves the equivalence between a processor's design and its specifications by rewriting recursive functions and using a new type of mathematical induction: extended recursive induction. Partial unfolding makes it possible to derive superscalar specifications from instruction-wise specifications. After the user indicates only selectors in the design, this algorithm can automatically prove correctness. The performance is independent of not only data width but also memory size. Experimental results are also presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115337377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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