Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486397
V. Varshavsky, V. Marakhovsky, R. Lashevsky
To solve the problem of global synchronization in massively parallel VLSI systems, it is necessary to organize asynchronous interaction between system blocks. The possibility of applying current sensors for detection of the end of signal transitions to construct asynchronous blocks in CMOS-technology is discussed. For known current sensors, their design principles and characteristics are analysed. Two ways of organizing the interaction between circuits with current sensors are suggested. Stubborn problems of using the known current sensors that appear due to the imperfection of their characteristics are formulated. A current sensor is suggested that removes the major of these problems but is capable of working only with a particular circuit class. However, simulation results indicated that using even such sensors is not efficient enough.
{"title":"Critical view on the current sensor application for self-timing in VLSI systems","authors":"V. Varshavsky, V. Marakhovsky, R. Lashevsky","doi":"10.1109/ASPDAC.1995.486397","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486397","url":null,"abstract":"To solve the problem of global synchronization in massively parallel VLSI systems, it is necessary to organize asynchronous interaction between system blocks. The possibility of applying current sensors for detection of the end of signal transitions to construct asynchronous blocks in CMOS-technology is discussed. For known current sensors, their design principles and characteristics are analysed. Two ways of organizing the interaction between circuits with current sensors are suggested. Stubborn problems of using the known current sensors that appear due to the imperfection of their characteristics are formulated. A current sensor is suggested that removes the major of these problems but is capable of working only with a particular circuit class. However, simulation results indicated that using even such sensors is not efficient enough.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486199
L. Lindqvist
VHDL has successfully been introduced into the design methodology for VLSI ASICs. This paper describes a high-level data abstraction and supporting tool that enhances this methodology in the telecommunication application domain. A significant performance gain was obtained by introducing the data abstraction outside the VHDL simulator. The enhanced methodology has been used in current ASIC designs with good results.
{"title":"Enhancing a VHDL based design methodology with application specific data abstraction","authors":"L. Lindqvist","doi":"10.1109/ASPDAC.1995.486199","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486199","url":null,"abstract":"VHDL has successfully been introduced into the design methodology for VLSI ASICs. This paper describes a high-level data abstraction and supporting tool that enhances this methodology in the telecommunication application domain. A significant performance gain was obtained by introducing the data abstraction outside the VHDL simulator. The enhanced methodology has been used in current ASIC designs with good results.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130657511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486371
A. Semenov, A. Yakovlev
We propose an algorithm combining two approaches to PN verification: PN unfolding and BDD-based traversal. We introduce a new application of the PN unfolding method. The results of unfolding construction are used for obtaining the close-to-optimal ordering of BDD variables. The effect of this combination is demonstrated on a set of benchmarks. The overall framework has been used for the verification of circuits in an asynchronous microprocessor.
{"title":"Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits","authors":"A. Semenov, A. Yakovlev","doi":"10.1109/ASPDAC.1995.486371","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486371","url":null,"abstract":"We propose an algorithm combining two approaches to PN verification: PN unfolding and BDD-based traversal. We introduce a new application of the PN unfolding method. The results of unfolding construction are used for obtaining the close-to-optimal ordering of BDD variables. The effect of this combination is demonstrated on a set of benchmarks. The overall framework has been used for the verification of circuits in an asynchronous microprocessor.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"939 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121040255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486368
K. Takahashi, H. Fujita
We propose a new method for hardware verification using the Boyer-Moore Theorem Prover. In this method, each signal of a sequential circuit is represented not as a waveform, but as a time parameterized function. A user simply describes the logical connection of the components of a circuit, and the separated form is mechanically derived. We formalize the method and show that the method not only realizes an efficient proof but is also useful for debugging.
{"title":"Time parameterized function method: a new method for hardware verification with the Boyer-Moore Theorem Prover","authors":"K. Takahashi, H. Fujita","doi":"10.1109/ASPDAC.1995.486368","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486368","url":null,"abstract":"We propose a new method for hardware verification using the Boyer-Moore Theorem Prover. In this method, each signal of a sequential circuit is represented not as a waveform, but as a time parameterized function. A user simply describes the logical connection of the components of a circuit, and the separated form is mechanically derived. We formalize the method and show that the method not only realizes an efficient proof but is also useful for debugging.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486366
W. Bradley, Ranga Vemuri
The performance description language PDL provides a compact notation for the specification of non-functional attributes of VLSI systems. This paper presents evaluation mechanisms which allow the designer to assert performance goals on PDL models of VLSI systems and determine if the constrained models are satisfiable. This is done by developing a PDL performance model and constructing a constraint satisfaction problem from the system of dependencies. This allows the designer to verify that an implementation of a VLSI system can satisfy all performance goals.
{"title":"Performance verification using PDL and constraint satisfaction","authors":"W. Bradley, Ranga Vemuri","doi":"10.1109/ASPDAC.1995.486366","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486366","url":null,"abstract":"The performance description language PDL provides a compact notation for the specification of non-functional attributes of VLSI systems. This paper presents evaluation mechanisms which allow the designer to assert performance goals on PDL models of VLSI systems and determine if the constrained models are satisfiable. This is done by developing a PDL performance model and constructing a constraint satisfaction problem from the system of dependencies. This allows the designer to verify that an implementation of a VLSI system can satisfy all performance goals.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"518 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116335273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486387
H. Barringer, G. Gough, Brian Monahan, A. Williams, M. Arcus, A. Armstrong, M. Hill
We describe a fully integrated design environment for the Hardware Description Language ELLA, which provides formal verification support to the hardware engineer. The environment includes both conventional hardware design tools, and special purpose tools for ELLA-level design transformation, symbolic simulation and formal verification. All tools operate from an underlying formal semantic representation of ELLA. The operation of the various tools is described from the user viewpoint via a simple design example.
{"title":"A design and verification environment for ELLA","authors":"H. Barringer, G. Gough, Brian Monahan, A. Williams, M. Arcus, A. Armstrong, M. Hill","doi":"10.1109/ASPDAC.1995.486387","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486387","url":null,"abstract":"We describe a fully integrated design environment for the Hardware Description Language ELLA, which provides formal verification support to the hardware engineer. The environment includes both conventional hardware design tools, and special purpose tools for ELLA-level design transformation, symbolic simulation and formal verification. All tools operate from an underlying formal semantic representation of ELLA. The operation of the various tools is described from the user viewpoint via a simple design example.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486386
J. Helbig
Statecharts can complement VHDL, in particular for system level design. We present what would be needed to extend VHDL by state based specification, sharing its syntax and the fundamental notion of time. The resulting integration is very tight, allowing, by comparison to existing approaches, more precise control for synthesis, incorporation of library components, multiple statechart instantiations and smooth paradigm switches. The language is being developed and implemented in the ESPRIT project FORMAT, and has been successfully employed for formal verification against timing diagram specifications.
{"title":"Extending VHDL for state based specifications","authors":"J. Helbig","doi":"10.1109/ASPDAC.1995.486386","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486386","url":null,"abstract":"Statecharts can complement VHDL, in particular for system level design. We present what would be needed to extend VHDL by state based specification, sharing its syntax and the fundamental notion of time. The resulting integration is very tight, allowing, by comparison to existing approaches, more precise control for synthesis, incorporation of library components, multiple statechart instantiations and smooth paradigm switches. The language is being developed and implemented in the ESPRIT project FORMAT, and has been successfully employed for formal verification against timing diagram specifications.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123631113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486378
R. Nalumasu, G. Gopalakrishnan
We investigate new techniques for reducing the memory requirements of an on-the-fly model checking tool that employs explicit enumeration. Two techniques are studied in depth: exploiting symmetries in the model, and exploiting sequential regions in the model. These techniques can result in a significant reduction in memory requirements, and often find progress violations at much lower stack depths. Both techniques have been implemented as part of the SPIN verifier, a widely used on-the-fly model-checking tool.
{"title":"Explicit-enumeration based verification made memory-efficient","authors":"R. Nalumasu, G. Gopalakrishnan","doi":"10.1109/ASPDAC.1995.486378","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486378","url":null,"abstract":"We investigate new techniques for reducing the memory requirements of an on-the-fly model checking tool that employs explicit enumeration. Two techniques are studied in depth: exploiting symmetries in the model, and exploiting sequential regions in the model. These techniques can result in a significant reduction in memory requirements, and often find progress violations at much lower stack depths. Both techniques have been implemented as part of the SPIN verifier, a widely used on-the-fly model-checking tool.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121999933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486391
R. Rochet, R. Leveugle, G. Saucier
This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented.
{"title":"Efficiency comparison of signature monitoring schemes for FSMs","authors":"R. Rochet, R. Leveugle, G. Saucier","doi":"10.1109/ASPDAC.1995.486391","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486391","url":null,"abstract":"This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"106 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122643636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486411
M. Nagamatu, S. Ismail, R. Shinji, T. Yanaru
Routing problems have been formulated as discrete optimization problems. The maze router has been widely used because of its ability to find a shortest path. The weakness of the maze router is that the routing quality is dependent on the ordering of the nets to be routed. We propose a new algorithm which solves the routing problem as a continuous valued constrained optimization problem. In this method, all of the continuous valued wires change their values simultaneously according to the dynamic equations of the Lagrangian method. We show that this method can solve the small switchbox routing problems with a higher completion rate as compared to the rip-up reroute maze router.
{"title":"Wire routing by Lagrangian method","authors":"M. Nagamatu, S. Ismail, R. Shinji, T. Yanaru","doi":"10.1109/ASPDAC.1995.486411","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486411","url":null,"abstract":"Routing problems have been formulated as discrete optimization problems. The maze router has been widely used because of its ability to find a shortest path. The weakness of the maze router is that the routing quality is dependent on the ordering of the nets to be routed. We propose a new algorithm which solves the routing problem as a continuous valued constrained optimization problem. In this method, all of the continuous valued wires change their values simultaneously according to the dynamic equations of the Lagrangian method. We show that this method can solve the small switchbox routing problems with a higher completion rate as compared to the rip-up reroute maze router.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125669383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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