Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486408
C. Morganti, T. Chen
A design for implementing graceful capacity degradation in large capacity hierarchical memories is presented. Previous research provided a means for testing and repairing blocks of memory. In the presence of an excessive number of faults, blocks may not be fully repairable. When coupled with the test and repair structure, this scheme will allow the memory capacity to degrade gracefully, i.e., the memory will still operate with a lower total capacity. The scheme was implemented and simulated using a 0.8 /spl mu/m CMOS process technology. Initial results show relatively small area overhead with a repair time of 2.5 ns best case.
{"title":"Graceful capacity degradation for ultra-large hierarchical memory structures","authors":"C. Morganti, T. Chen","doi":"10.1109/ASPDAC.1995.486408","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486408","url":null,"abstract":"A design for implementing graceful capacity degradation in large capacity hierarchical memories is presented. Previous research provided a means for testing and repairing blocks of memory. In the presence of an excessive number of faults, blocks may not be fully repairable. When coupled with the test and repair structure, this scheme will allow the memory capacity to degrade gracefully, i.e., the memory will still operate with a lower total capacity. The scheme was implemented and simulated using a 0.8 /spl mu/m CMOS process technology. Initial results show relatively small area overhead with a repair time of 2.5 ns best case.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133312577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486376
P. Kudva, G. Gopalakrishnan, V. Akella
We introduce a high-level synthesis tool that generates efficient asynchronous circuits from a language based on extended Petri-nets. A salient feature of our synthesis technique is its ability to automatically generate ensembles of interacting burst-mode FSM-based controllers and macromodule-based controllers (using macromodule synthesis capabilities developed in our earlier efforts). This is achieved by first decomposing the input description into a set of sequential threads with choices, allocating resources for the threads, and refining the threads towards burst-mode machines. Major contributions of the work reported in this paper are the generation of interacting burst-mode controllers from high-level descriptions. Details of the synthesis system and results on examples including parts of a DCT processor are presented.
{"title":"High level synthesis of asynchronous circuit targeting state machine controllers","authors":"P. Kudva, G. Gopalakrishnan, V. Akella","doi":"10.1109/ASPDAC.1995.486376","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486376","url":null,"abstract":"We introduce a high-level synthesis tool that generates efficient asynchronous circuits from a language based on extended Petri-nets. A salient feature of our synthesis technique is its ability to automatically generate ensembles of interacting burst-mode FSM-based controllers and macromodule-based controllers (using macromodule synthesis capabilities developed in our earlier efforts). This is achieved by first decomposing the input description into a set of sequential threads with choices, allocating resources for the threads, and refining the threads towards burst-mode machines. Major contributions of the work reported in this paper are the generation of interacting burst-mode controllers from high-level descriptions. Details of the synthesis system and results on examples including parts of a DCT processor are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127824744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486390
F. Fummi, D. Sciuto, M. Serra
The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks.
{"title":"Test pattern embedding in sequential circuits through cellular automata","authors":"F. Fummi, D. Sciuto, M. Serra","doi":"10.1109/ASPDAC.1995.486390","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486390","url":null,"abstract":"The embedding of test patterns into a sequential circuit is the main topic of this paper. Deterministic test patterns for the sequential circuit under test are chosen to be embedded into hybrid cellular automata (CA). Test identification and CA synthesis are performed in parallel thus overcoming results achieved by embedding pre-computed vectors. The theory of sequential test generation under such a constraint is provided and the feasibility of the proposed testing methodology is shown on benchmarks.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115509340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486361
Mandayam, Srivas, Steven P. Miller
Formal verification using interactive proof-checkers has been used successfully to verify a wide variety of moderate-sized hardware designs. The industry is beginning to look at formal verification as an alternative to simulation for obtaining higher assurance than is currently possible. However, many questions remain regarding its use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This paper describes a project recently undertaken by SRI International and Collins Commercial Avionics, a division of Rockwell International to explore some of these questions. The project formally specified in SRI's PVS language a Rockwell proprietary pipelined microprocessor (the AAMP5, built using almost half a million transistors) at both the instruction-set and register-transfer levels and used the PVS theorem prover to show the microcode correctly implemented the instruction-level specification for a representative subset of instructions. The key results of the project were the development of a practical methodology for microprocessor verification in industrial settings and the discovery of both actual and seeded errors.
{"title":"Applying formal verification to a commercial microprocessor","authors":"Mandayam, Srivas, Steven P. Miller","doi":"10.1109/ASPDAC.1995.486361","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486361","url":null,"abstract":"Formal verification using interactive proof-checkers has been used successfully to verify a wide variety of moderate-sized hardware designs. The industry is beginning to look at formal verification as an alternative to simulation for obtaining higher assurance than is currently possible. However, many questions remain regarding its use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This paper describes a project recently undertaken by SRI International and Collins Commercial Avionics, a division of Rockwell International to explore some of these questions. The project formally specified in SRI's PVS language a Rockwell proprietary pipelined microprocessor (the AAMP5, built using almost half a million transistors) at both the instruction-set and register-transfer levels and used the PVS theorem prover to show the microcode correctly implemented the instruction-level specification for a representative subset of instructions. The key results of the project were the development of a practical methodology for microprocessor verification in industrial settings and the discovery of both actual and seeded errors.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129898382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486375
S. Rajan
This paper presents a formal approach to address the correctness of transformations in high-level synthesis. The novelty of the work is that a small set of properties that capture a general notion of refinement of control/data-flow graphs used in an industrial synthesis framework have been given, and the properties are independent of the underlying behaviour model. We have mechanized the specification and verification of several optimization and refinement transformations used in industrial hardware design. This work has enabled to find and rectify errors in the transformations. Further, the work has led to generalization of transformations typically used in high-level synthesis.
{"title":"Correctness of transformations in high level synthesis","authors":"S. Rajan","doi":"10.1109/ASPDAC.1995.486375","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486375","url":null,"abstract":"This paper presents a formal approach to address the correctness of transformations in high-level synthesis. The novelty of the work is that a small set of properties that capture a general notion of refinement of control/data-flow graphs used in an industrial synthesis framework have been given, and the properties are independent of the underlying behaviour model. We have mechanized the specification and verification of several optimization and refinement transformations used in industrial hardware design. This work has enabled to find and rectify errors in the transformations. Further, the work has led to generalization of transformations typically used in high-level synthesis.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"29 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129544207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486367
S. Venkatesan, K. Davis
In this paper, we investigate the database support needs of an engineering domain, and propose a conceptual model and database architecture to support electrical CAD applications. This paper emphasizes data representation for designs specified using a standard description language, VHDL. The research offers three basic contributions: (1) a VHDL data model is designed within the framework of a meta-model for electrical CAD modeling, (2) a database system architecture implementing the data model is developed, and (3) a CAD software environment for hardware/software codesign that can benefit from the proposed database technology is described. The data model and database architecture are the foundation for query processing and other database activities.
{"title":"Design of a DBMS for VHDL-based CAD environments","authors":"S. Venkatesan, K. Davis","doi":"10.1109/ASPDAC.1995.486367","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486367","url":null,"abstract":"In this paper, we investigate the database support needs of an engineering domain, and propose a conceptual model and database architecture to support electrical CAD applications. This paper emphasizes data representation for designs specified using a standard description language, VHDL. The research offers three basic contributions: (1) a VHDL data model is designed within the framework of a meta-model for electrical CAD modeling, (2) a database system architecture implementing the data model is developed, and (3) a CAD software environment for hardware/software codesign that can benefit from the proposed database technology is described. The data model and database architecture are the foundation for query processing and other database activities.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127035109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486402
Christoph Weiler, U. Kebschull, W. Rosenstiel
The paper introduces a novel method of specification, simulation and partitioning on the system level using a common and convenient language (C++). Special base classes provide explicit concurrency and additional possibilities for analyzing and simulating the whole system during an early design phase. The hardware/software partitioning algorithm uses the results of the analysis and simulation in order to partition the specification into hardware and software.
{"title":"C++ base classes for specification, simulation and partitioning of a hardware/software system","authors":"Christoph Weiler, U. Kebschull, W. Rosenstiel","doi":"10.1109/ASPDAC.1995.486402","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486402","url":null,"abstract":"The paper introduces a novel method of specification, simulation and partitioning on the system level using a common and convenient language (C++). Special base classes provide explicit concurrency and additional possibilities for analyzing and simulating the whole system during an early design phase. The hardware/software partitioning algorithm uses the results of the analysis and simulation in order to partition the specification into hardware and software.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1946 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486365
F. Wagner
A methodology for the development of integrated and open HDL-based design environments is proposed. It considers different tool integration approaches and the selection of either environment-independent or dependent HDLs and tools. Following this methodology, an application designer can develop an ideal environment with regard to integration and openness. The interplay between HDLs and integrated and open design environments is also discussed.
{"title":"A methodology for the development of integrated and open HDL-based design environments","authors":"F. Wagner","doi":"10.1109/ASPDAC.1995.486365","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486365","url":null,"abstract":"A methodology for the development of integrated and open HDL-based design environments is proposed. It considers different tool integration approaches and the selection of either environment-independent or dependent HDLs and tools. Following this methodology, an application designer can develop an ideal environment with regard to integration and openness. The interplay between HDLs and integrated and open design environments is also discussed.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486377
P. Wilsey, D.M. Benz, S. L. Pandey
Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize.
{"title":"A model of VHDL for the analysis, transformation, and optimization of digital system designs","authors":"P. Wilsey, D.M. Benz, S. L. Pandey","doi":"10.1109/ASPDAC.1995.486377","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486377","url":null,"abstract":"Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115744098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-08-29DOI: 10.1109/ASPDAC.1995.486410
M. Kaneko, H. Miyauchi
A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.
{"title":"A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy","authors":"M. Kaneko, H. Miyauchi","doi":"10.1109/ASPDAC.1995.486410","DOIUrl":"https://doi.org/10.1109/ASPDAC.1995.486410","url":null,"abstract":"A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130570060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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