Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409029
E. Gad, M. Nakhla
A new orthogonalization algorithm is presented for sensitivity analysis techniques based on the integrated congruence transform. The proposed technique does not require sensitivity moments to be computed explicitly to generate an orthogonal basis that spans their subspace. The proposed algorithm can be used to construct an orthogonal basis for a general set of elements in Hilbert space related through an inhomogeneous differential operator. Simulation results demonstrate improved numerical accuracy by using the new orthogonalization technique.
{"title":"Efficient algorithm for sensitivity analysis of nonuniform transmission lines","authors":"E. Gad, M. Nakhla","doi":"10.1109/SPI.2004.1409029","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409029","url":null,"abstract":"A new orthogonalization algorithm is presented for sensitivity analysis techniques based on the integrated congruence transform. The proposed technique does not require sensitivity moments to be computed explicitly to generate an orthogonal basis that spans their subspace. The proposed algorithm can be used to construct an orthogonal basis for a general set of elements in Hilbert space related through an inhomogeneous differential operator. Simulation results demonstrate improved numerical accuracy by using the new orthogonalization technique.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123666969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409006
F. Salhi, G. Sommer, W. John, H. Reichl
This paper introduces two basic test structures and its functionality for continuous determination of electrical properties of material as well as geometrical parameter of substrate designs. On the basis of a high frequency substrate with known characteristics, a method for determination of material properties in a frequency range of 1 GHz to at least 24 GHz is presented. Fundamental importance is attached to the relative permittivity. /spl epsiv//sub /spl Gamma//, and the dissipation factor, tan/spl delta/. High frequency measurements are compared to simulation results. Finally, the extracted material parameters are presented and discussed. Methods of line resonator and branch line coupler are compared concerning accuracy, sensitivity and manageability.
{"title":"Application of test structures for monitoring of high frequency characteristics of organic substrate materials","authors":"F. Salhi, G. Sommer, W. John, H. Reichl","doi":"10.1109/SPI.2004.1409006","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409006","url":null,"abstract":"This paper introduces two basic test structures and its functionality for continuous determination of electrical properties of material as well as geometrical parameter of substrate designs. On the basis of a high frequency substrate with known characteristics, a method for determination of material properties in a frequency range of 1 GHz to at least 24 GHz is presented. Fundamental importance is attached to the relative permittivity. /spl epsiv//sub /spl Gamma//, and the dissipation factor, tan/spl delta/. High frequency measurements are compared to simulation results. Finally, the extracted material parameters are presented and discussed. Methods of line resonator and branch line coupler are compared concerning accuracy, sensitivity and manageability.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409054
R. Abhari, G. Eleftheriades
In this paper, the global suppression of the power/ground noise induced by a transient current on vias within a parallel-plate power distribution system is studied. Two different methods of noise suppression, i.e. differential via routing and application of an electromagnetic bandgap (EBG) structure, are investigated. The latter offers noise suppression in all azimuthal directions, while the noise suppression achieved by differential routing depends on the location of the observation point and improves at farther distances from the source.
{"title":"Investigating the global suppression of the power/ground plane noise","authors":"R. Abhari, G. Eleftheriades","doi":"10.1109/SPI.2004.1409054","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409054","url":null,"abstract":"In this paper, the global suppression of the power/ground noise induced by a transient current on vias within a parallel-plate power distribution system is studied. Two different methods of noise suppression, i.e. differential via routing and application of an electromagnetic bandgap (EBG) structure, are investigated. The latter offers noise suppression in all azimuthal directions, while the noise suppression achieved by differential routing depends on the location of the observation point and improves at farther distances from the source.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131426964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409027
P. Heres, J. Niehof, W. Schilders, Prof. Holstlaan
Stable equivalent circuit models cannot be guaranteed by currently available EM simulation tooling, resulting in non-convergence in time domain simulations. Theoretically it is proven that available MOR methods preserve stability and passivity in the reduction process. Implementation of MOR methods and the realization of equivalent circuit models for actual use in circuit simulation are not straightforward. This paper describes the successful implementation of a MOR method, allowing the generation of equivalent circuit models suitable for time domain simulation. Two examples of time domain simulations performed on real-life interconnect structures are given.
{"title":"Implementation of MOR for time domain simulation on real-life interconnect structures","authors":"P. Heres, J. Niehof, W. Schilders, Prof. Holstlaan","doi":"10.1109/SPI.2004.1409027","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409027","url":null,"abstract":"Stable equivalent circuit models cannot be guaranteed by currently available EM simulation tooling, resulting in non-convergence in time domain simulations. Theoretically it is proven that available MOR methods preserve stability and passivity in the reduction process. Implementation of MOR methods and the realization of equivalent circuit models for actual use in circuit simulation are not straightforward. This paper describes the successful implementation of a MOR method, allowing the generation of equivalent circuit models suitable for time domain simulation. Two examples of time domain simulations performed on real-life interconnect structures are given.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121336676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409022
A. Lopez, D. Deschacht
Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. In this paper, we show the influence of on-chip self and mutual inductances on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and on the other with the drivers in opposite directions. The differences observed, when the currents in the lines flow in the same direction as opposed to the cases when the currents are in opposite directions shows clearly the influence of mutual inductance. A second comparison ignoring inductive effects shows a discrepancy rate reaching as high as 50% for the output switching delay.
{"title":"Illustration of the importance of on-chip self and mutual inductances","authors":"A. Lopez, D. Deschacht","doi":"10.1109/SPI.2004.1409022","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409022","url":null,"abstract":"Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. In this paper, we show the influence of on-chip self and mutual inductances on timing performances by considering two configurations of parallel coupled interconnects, one with both drivers on the same side, and on the other with the drivers in opposite directions. The differences observed, when the currents in the lines flow in the same direction as opposed to the cases when the currents are in opposite directions shows clearly the influence of mutual inductance. A second comparison ignoring inductive effects shows a discrepancy rate reaching as high as 50% for the output switching delay.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409015
D. Saraswat, R. Achar, M. Nakhla
With the increasing operating frequencies and functionality in modern designs, the resulting size of circuit equations of high-frequency modules are becoming large. Two-level passive model-reduction based algorithms were recently suggested to obtain compact macromodels for fast transient analysis of large scale circuits. This paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms.
{"title":"A fast algorithm for near optimal passive reduction of high-speed interconnect networks","authors":"D. Saraswat, R. Achar, M. Nakhla","doi":"10.1109/SPI.2004.1409015","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409015","url":null,"abstract":"With the increasing operating frequencies and functionality in modern designs, the resulting size of circuit equations of high-frequency modules are becoming large. Two-level passive model-reduction based algorithms were recently suggested to obtain compact macromodels for fast transient analysis of large scale circuits. This paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133670961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409000
J. Rauscher, H. Pfleiderer
In this paper a 2D signal line model is used to simulate the power distribution network (PDN). The proposed method uses an admittance function to model the frequency-dependent resistance and inductance in each direction. This admittance function can be gained directly by model order reduction from a partial element equivalent circuit (PEEC) model. Hence, it is possible to efficiently calculate the model parameters even for irregular PDNs. A fast transient simulation algorithm closely related to the finite-difference time-domain (FDTD) schemes is presented. The alternating-direction-implicit (ADI) method relaxes the time step for the simulation, because it is not limited by a stability criterion.
{"title":"PEEC methods in 2D signal line modeling for mid-frequency on-chip power supply noise simulations","authors":"J. Rauscher, H. Pfleiderer","doi":"10.1109/SPI.2004.1409000","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409000","url":null,"abstract":"In this paper a 2D signal line model is used to simulate the power distribution network (PDN). The proposed method uses an admittance function to model the frequency-dependent resistance and inductance in each direction. This admittance function can be gained directly by model order reduction from a partial element equivalent circuit (PEEC) model. Hence, it is possible to efficiently calculate the model parameters even for irregular PDNs. A fast transient simulation algorithm closely related to the finite-difference time-domain (FDTD) schemes is presented. The alternating-direction-implicit (ADI) method relaxes the time step for the simulation, because it is not limited by a stability criterion.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131408660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409023
R. Gordin, D. Goren
The paper presents a semi-analytical technique for modeling capacitance of on-chip coplanar transmission lines over conductive silicon substrate. The focus is put on developing expressions for high frequency capacitance which yield reasonable accuracy. The technique is based on the 2D approach and results in accurate and efficient expressions accounting for frequency dependent behavior of the silicon substrate, as well as for actual transmission lines geometry.
{"title":"Modeling capacitance of on-chip coplanar transmission lines over the silicon substrate","authors":"R. Gordin, D. Goren","doi":"10.1109/SPI.2004.1409023","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409023","url":null,"abstract":"The paper presents a semi-analytical technique for modeling capacitance of on-chip coplanar transmission lines over conductive silicon substrate. The focus is put on developing expressions for high frequency capacitance which yield reasonable accuracy. The technique is based on the 2D approach and results in accurate and efficient expressions accounting for frequency dependent behavior of the silicon substrate, as well as for actual transmission lines geometry.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409032
C. Kolleck, M. Stallein, G. Mrozynski
For the simulation of light transmission over optical interconnects an appropriate modeling of the coupling process is needed. Comprehensive methods like the mode matching method can offer accurate results as long as a very high number of modes on both sides of the coupling interface is available. In this paper, some simpler numerical methods are assessed and compared to the results of the mode matching method applied to a 2D coupling problem. It turns out that these methods can be used well under usual operating conditions for highly multimodal waveguides, but the errors increase with the deviation from the non-ideal coupling geometry.
{"title":"Models for the coupling of light into multimode waveguides","authors":"C. Kolleck, M. Stallein, G. Mrozynski","doi":"10.1109/SPI.2004.1409032","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409032","url":null,"abstract":"For the simulation of light transmission over optical interconnects an appropriate modeling of the coupling process is needed. Comprehensive methods like the mode matching method can offer accurate results as long as a very high number of modes on both sides of the coupling interface is available. In this paper, some simpler numerical methods are assessed and compared to the results of the mode matching method applied to a 2D coupling problem. It turns out that these methods can be used well under usual operating conditions for highly multimodal waveguides, but the errors increase with the deviation from the non-ideal coupling geometry.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120895691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409041
A. Bogliolo, F. Vaira, L. Vendrame, L. Bortesi
We present a new test structure for measuring on-chip cross-coupling capacitance by means of crosstalk-induced supply currents. The key advantage of the proposed approach over existing charge-based capacitance measurements (CBCMs) based on cross talk is that the victim line is kept at a constant voltage level, thus avoiding short-circuit currents and enabling complete compensation of charge redistribution effects. We present preliminary experimental results obtained from a 0.13 /spl mu/m CMOS implementation.
{"title":"A new test structure for measuring on-chip cross-coupling capacitances","authors":"A. Bogliolo, F. Vaira, L. Vendrame, L. Bortesi","doi":"10.1109/SPI.2004.1409041","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409041","url":null,"abstract":"We present a new test structure for measuring on-chip cross-coupling capacitance by means of crosstalk-induced supply currents. The key advantage of the proposed approach over existing charge-based capacitance measurements (CBCMs) based on cross talk is that the victim line is kept at a constant voltage level, thus avoiding short-circuit currents and enabling complete compensation of charge redistribution effects. We present preliminary experimental results obtained from a 0.13 /spl mu/m CMOS implementation.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130587780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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