Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1408989
A. Farcy, O. Cueto, B. Blampey, Thierry Lacrevaz, B. Fléchet, F. Crecy, Joaquim Torres
The speed of integrated circuits is increasingly fixed by interconnect performances. To address this issue, the development of new back-end of line technology schemes and materials should be driven by predictions of associated benefits. A new tool was developed and coupled to electromagnetic software to carry out time domain simulations. As a result, the dependences of interconnect performances on process parameters and design rules were extracted for the 65 nm and 45 nm technology nodes.
{"title":"Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters","authors":"A. Farcy, O. Cueto, B. Blampey, Thierry Lacrevaz, B. Fléchet, F. Crecy, Joaquim Torres","doi":"10.1109/SPI.2004.1408989","DOIUrl":"https://doi.org/10.1109/SPI.2004.1408989","url":null,"abstract":"The speed of integrated circuits is increasingly fixed by interconnect performances. To address this issue, the development of new back-end of line technology schemes and materials should be driven by predictions of associated benefits. A new tool was developed and coupled to electromagnetic software to carry out time domain simulations. As a result, the dependences of interconnect performances on process parameters and design rules were extracted for the 65 nm and 45 nm technology nodes.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409010
A. Korshak
To avoid unjustified optimism in noise prediction in the absence of accurate analysis of switching activity, commercial tools have to make the most conservative assumption about aggressor switching which leads to an overly pessimistic result in situations of strongly correlated signals connected by repeaters. Such pessimism in the noise analysis hides out the effect of interleaved repeaters used to minimize noise in long, coupled interconnects. In the proposed approach we accurately analyze coupled networks with repeaters by considering timing and logical correlations, and multiple signal switching. We demonstrate an 81% reduction in the number of false noise violations in a design where interleaved repeaters are used for crosstalk critical global interconnects.
{"title":"Cross-talk noise in repeater networks","authors":"A. Korshak","doi":"10.1109/SPI.2004.1409010","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409010","url":null,"abstract":"To avoid unjustified optimism in noise prediction in the absence of accurate analysis of switching activity, commercial tools have to make the most conservative assumption about aggressor switching which leads to an overly pessimistic result in situations of strongly correlated signals connected by repeaters. Such pessimism in the noise analysis hides out the effect of interleaved repeaters used to minimize noise in long, coupled interconnects. In the proposed approach we accurately analyze coupled networks with repeaters by considering timing and logical correlations, and multiple signal switching. We demonstrate an 81% reduction in the number of false noise violations in a design where interleaved repeaters are used for crosstalk critical global interconnects.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116372539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409004
U. Pfeiffer, A. Chandrasekhar, T. Zwick
In this paper we present the performance of flip-chip interconnects up to 40 GHz based on an alternative non-destructive measurement technique. The presented method unfolds the raw flip-chip interconnect, excluding any launch structures for an actually mounted silicon chip. A preliminary modeling approach for chip-package co-design is outlined.
{"title":"A new in-situ approach to flip-chip interconnect characterization up to millimeter wave frequencies","authors":"U. Pfeiffer, A. Chandrasekhar, T. Zwick","doi":"10.1109/SPI.2004.1409004","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409004","url":null,"abstract":"In this paper we present the performance of flip-chip interconnects up to 40 GHz based on an alternative non-destructive measurement technique. The presented method unfolds the raw flip-chip interconnect, excluding any launch structures for an actually mounted silicon chip. A preliminary modeling approach for chip-package co-design is outlined.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127845637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1408994
Heeseok Lee, Youngsoo Hong, D. Kam, Joungho Kim
Due to the high speed and low power trends, the design of the power distribution network (PDN) in multi-layer printed circuit board (PCB) becomes more important. This paper presents a fast and efficient analysis methodology for power/ground plane pair considering irregular shaped power plane and via effects in the frequency-domain. The proposed method uses parallel-plate transmission line theory and partitioning of the plane considering geometry properties. Using the popularly used circuit simulator SPICE, we have analyzed input-impedance of the power/ground plane pair. Due to the higher accuracy and the faster simulation time, the proposed method is applicable to the early design step of multi-layer PCB. Characteristic of power distribution network implemented by perforated plane is determined based on full-wave analysis using FDTD periodic structure modeling method.
{"title":"Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole","authors":"Heeseok Lee, Youngsoo Hong, D. Kam, Joungho Kim","doi":"10.1109/SPI.2004.1408994","DOIUrl":"https://doi.org/10.1109/SPI.2004.1408994","url":null,"abstract":"Due to the high speed and low power trends, the design of the power distribution network (PDN) in multi-layer printed circuit board (PCB) becomes more important. This paper presents a fast and efficient analysis methodology for power/ground plane pair considering irregular shaped power plane and via effects in the frequency-domain. The proposed method uses parallel-plate transmission line theory and partitioning of the plane considering geometry properties. Using the popularly used circuit simulator SPICE, we have analyzed input-impedance of the power/ground plane pair. Due to the higher accuracy and the faster simulation time, the proposed method is applicable to the early design step of multi-layer PCB. Characteristic of power distribution network implemented by perforated plane is determined based on full-wave analysis using FDTD periodic structure modeling method.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116897004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409001
T. Arabi, G. Ji, G. Taylor
In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors and on die capacitance. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Because the ESL is not zero, die capacitance is required to reduce the impact of this ESL on the power supply noise. Alternatively, in this paper, we present a novel approach of using an on-die metal resistor in series with the package capacitance to dampen the high frequency noise. We show by validation on the 90 nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the bus speed.
{"title":"Dampening high frequency noise in high performance microprocessor packaging","authors":"T. Arabi, G. Ji, G. Taylor","doi":"10.1109/SPI.2004.1409001","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409001","url":null,"abstract":"In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors and on die capacitance. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Because the ESL is not zero, die capacitance is required to reduce the impact of this ESL on the power supply noise. Alternatively, in this paper, we present a novel approach of using an on-die metal resistor in series with the package capacitance to dampen the high frequency noise. We show by validation on the 90 nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the bus speed.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409046
I. Kelander, A. Arslan, L. Hyvonen, S. Kangasmaa
This paper discusses the modeling of 3D electronic packages. A 3D model of a stacked die package solution is built and analyzed in a 3D electromagnetic (EM) simulation tool, and a lumped element RLC equivalent model is extracted. The challenges and possibilities of EM simulation are discussed. The parasitic components of the package are studied by analyzing the 3D model by parts. Strategies in specifying a Spice net list of the package model and its feasibility in circuit simulations are considered.
{"title":"Modeling of 3D packages using EM simulators","authors":"I. Kelander, A. Arslan, L. Hyvonen, S. Kangasmaa","doi":"10.1109/SPI.2004.1409046","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409046","url":null,"abstract":"This paper discusses the modeling of 3D electronic packages. A 3D model of a stacked die package solution is built and analyzed in a 3D electromagnetic (EM) simulation tool, and a lumped element RLC equivalent model is extracted. The challenges and possibilities of EM simulation are discussed. The parasitic components of the package are studied by analyzing the 3D model by parts. Strategies in specifying a Spice net list of the package model and its feasibility in circuit simulations are considered.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114756038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409028
I. Stievano, C. Siviero, I. Maio, F. Canavero
This paper addresses the development of behavioral macromodels of differential drivers for the assessment of signal integrity and electromagnetic compatibility effects in high-speed digital systems. The obtained macromodels are readily implemented as SPICE-like subcircuits to be included in any circuit simulation environment. Accuracy and efficiency of macromodels are assessed by applying the proposed methodology to actual differential devices.
{"title":"Behavioral macromodels of differential drivers","authors":"I. Stievano, C. Siviero, I. Maio, F. Canavero","doi":"10.1109/SPI.2004.1409028","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409028","url":null,"abstract":"This paper addresses the development of behavioral macromodels of differential drivers for the assessment of signal integrity and electromagnetic compatibility effects in high-speed digital systems. The obtained macromodels are readily implemented as SPICE-like subcircuits to be included in any circuit simulation environment. Accuracy and efficiency of macromodels are assessed by applying the proposed methodology to actual differential devices.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124357786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409040
M. Kadi, F. Ndagijimana, J. Dansou
The RF wireless interconnects are presented as an alternative solution to intra-chip clock distribution, which leads to severe power consumption and signal integrity limitations for over GHz digital applications. In this work, this concept is implemented in MCM package and board levels to meet the high-speed transmission performance. Miniaturized dipole antennas printed on high-K substrate are used and a good transmission gain is obtained for a separation distance of from 1 cm to 4 cm. In this paper, we focus our study in the analysis of the interferences generated by antennas used in the RF-wireless clock distribution. The parasitic coupling between antennas and multilayer interconnects is discussed for different configurations.
{"title":"Electromagnetic interference produced by printed dipole antennas for MCM wireless RF clock distribution","authors":"M. Kadi, F. Ndagijimana, J. Dansou","doi":"10.1109/SPI.2004.1409040","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409040","url":null,"abstract":"The RF wireless interconnects are presented as an alternative solution to intra-chip clock distribution, which leads to severe power consumption and signal integrity limitations for over GHz digital applications. In this work, this concept is implemented in MCM package and board levels to meet the high-speed transmission performance. Miniaturized dipole antennas printed on high-K substrate are used and a good transmission gain is obtained for a separation distance of from 1 cm to 4 cm. In this paper, we focus our study in the analysis of the interferences generated by antennas used in the RF-wireless clock distribution. The parasitic coupling between antennas and multilayer interconnects is discussed for different configurations.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130574147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409011
A. K. Palit, V. Meyer, W. Anheier, J. Schloeffel
Signal integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation by A. Attartha and M. Nourani (2002). SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. Therefore, this paper aims to analyze the cross-talk coupling effects between the two interconnects, namely the aggressor and victim lines, using the ABCD two-port network model. In order to reduce the simulation time a reduced order modeling of the interconnect line is considered. Furthermore, as stated in various literatures by A. Sinha et al. (1999) the rising (or falling) input signal represented by a simple step function is not accurate enough, therefore in this paper the rising transitions and the falling transitions are represented more accurately using the exponential terms, and based on such input representation the time domain output signal voltage in presence of crosstalk noise, at the far end side of both aggressor line and victim line, is determined. Such output voltage representation is very helpful in estimating the delay, overshoot or undershoot etc., which are believed to cause SI losses in the SoC.
A. Attartha和M. Nourani(2002)指出，互连中的信号完整性(SI)损耗是高频工作时寄生电容、电阻和电感的分布特性所产生的干扰。如果多个互连线相互耦合能量，则SI损耗会进一步加剧。因此，本文旨在利用ABCD双端口网络模型分析攻击线和受害线这两条互连线之间的串扰耦合效应。为了减少仿真时间，考虑对互连线进行降阶建模。此外，正如a . Sinha等人(1999)在各种文献中所述，由简单阶跃函数表示的上升(或下降)输入信号不够准确，因此本文使用指数项更准确地表示上升跃迁和下降跃迁，并基于这种输入表示来确定存在串扰噪声的时域输出信号电压，在攻击线和受害线的远端。这样的输出电压表示在估计延迟、超调或欠调等方面非常有帮助，这些被认为会导致SoC中的SI损耗。
{"title":"Analysis of crosstalk coupling effects between aggressor and victim interconnect using two-port network model","authors":"A. K. Palit, V. Meyer, W. Anheier, J. Schloeffel","doi":"10.1109/SPI.2004.1409011","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409011","url":null,"abstract":"Signal integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation by A. Attartha and M. Nourani (2002). SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. Therefore, this paper aims to analyze the cross-talk coupling effects between the two interconnects, namely the aggressor and victim lines, using the ABCD two-port network model. In order to reduce the simulation time a reduced order modeling of the interconnect line is considered. Furthermore, as stated in various literatures by A. Sinha et al. (1999) the rising (or falling) input signal represented by a simple step function is not accurate enough, therefore in this paper the rising transitions and the falling transitions are represented more accurately using the exponential terms, and based on such input representation the time domain output signal voltage in presence of crosstalk noise, at the far end side of both aggressor line and victim line, is determined. Such output voltage representation is very helpful in estimating the delay, overshoot or undershoot etc., which are believed to cause SI losses in the SoC.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129633951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409033
T. Nahring
Potentials of electrostatic fields in models of straight shielded cables are often assumed to be cylindrical (i.e., independent of the coordinate in axial direction of the cable). We give a rigorous motivation for this assumption. From the boundary conditions at the cable ends of shielded cables there result deviations of the potential from the cylindrical potential in the proximity of the cable ends. Such deviations were firstly introduced as residual potentials by us at ISTET '03. Here, we present new optimized estimations for residual potentials. To a nontrivial residual potential, there corresponds nontransversal electrostatic field strength, denoted as residual field strength. For the first time, we discuss an estimation of the residual field strength along the conductors of a cable model in this paper.
{"title":"Nontransversal electrostatic fields in cable models","authors":"T. Nahring","doi":"10.1109/SPI.2004.1409033","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409033","url":null,"abstract":"Potentials of electrostatic fields in models of straight shielded cables are often assumed to be cylindrical (i.e., independent of the coordinate in axial direction of the cable). We give a rigorous motivation for this assumption. From the boundary conditions at the cable ends of shielded cables there result deviations of the potential from the cylindrical potential in the proximity of the cable ends. Such deviations were firstly introduced as residual potentials by us at ISTET '03. Here, we present new optimized estimations for residual potentials. To a nontrivial residual potential, there corresponds nontransversal electrostatic field strength, denoted as residual field strength. For the first time, we discuss an estimation of the residual field strength along the conductors of a cable model in this paper.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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