Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409053
J. Wee, Seongsoo Lee, Yong-Ju Kim
This paper illustrates the noise characteristics under chip's operations according to types of packages and modules for DDR SDRAM. The impedance profiles and power noises are analyzed with SDRAM chips having TSOP package and FBGA package on TSOP-based DIMM and FBGA-based DIMM. In controversy with common concepts, the noise characteristics of FBGA package are more weak and sensitive than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.
{"title":"Analysis of chip-to-chip power noise coupling on several SDRAM modules","authors":"J. Wee, Seongsoo Lee, Yong-Ju Kim","doi":"10.1109/SPI.2004.1409053","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409053","url":null,"abstract":"This paper illustrates the noise characteristics under chip's operations according to types of packages and modules for DDR SDRAM. The impedance profiles and power noises are analyzed with SDRAM chips having TSOP package and FBGA package on TSOP-based DIMM and FBGA-based DIMM. In controversy with common concepts, the noise characteristics of FBGA package are more weak and sensitive than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409009
F. Bien, A. Raghavan, Z. Nami, C. Lee, A. Kim, M. Vrazel, E. Gebara, S. Bajekal, B. Schmukler, J. Laskar
A multi-rate crosstalk canceller for active cancellation of near end cross talk (NEXT) caused by a single aggressor in a backplane channel environment has been demonstrated in this paper. The proposed IC enhances the performance of existing legacy backplane at higher data rates, thereby avoiding the costs associated with upgrading to higher end backplanes and connectors. The IC has been fabricated in a 0.18/spl mu/m CMOS process and the prototype test bench demonstrated capability of improving the bit-error rate (BER) performance in excess of 5 orders of magnitude at data rates up to 6.25Gbps.
本文演示了一种多速率串扰消除器，用于主动消除背板信道环境中由单个干扰源引起的近端串扰。拟议的IC在更高的数据速率下增强了现有传统背板的性能，从而避免了升级到更高端的背板和连接器的相关成本。该集成电路已在0.18/spl μ m CMOS工艺中制造，原型测试台证明了在高达6.25Gbps的数据速率下将误码率(BER)性能提高超过5个数量级的能力。
{"title":"A 0.18/spl mu/m CMOS fully integrated 6.25Gbps single aggressor multi-rate crosstalk cancellation IC for legacy backplane and interconnect applications","authors":"F. Bien, A. Raghavan, Z. Nami, C. Lee, A. Kim, M. Vrazel, E. Gebara, S. Bajekal, B. Schmukler, J. Laskar","doi":"10.1109/SPI.2004.1409009","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409009","url":null,"abstract":"A multi-rate crosstalk canceller for active cancellation of near end cross talk (NEXT) caused by a single aggressor in a backplane channel environment has been demonstrated in this paper. The proposed IC enhances the performance of existing legacy backplane at higher data rates, thereby avoiding the costs associated with upgrading to higher end backplanes and connectors. The IC has been fabricated in a 0.18/spl mu/m CMOS process and the prototype test bench demonstrated capability of improving the bit-error rate (BER) performance in excess of 5 orders of magnitude at data rates up to 6.25Gbps.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409017
R. Gao, Y. Mekonnen, W. Beyene, J. Schutt-Ainé
In this paper, a rational function approach is used to approximate the transfer function of linear systems characterized by sampled data. The ill-conditioned Vandermonde-like matrix associated with the ordinary power series is avoided by using Chebyshev polynomials. Clenshaw's recurrence algorithm is applied in transforming the Chebyshev coefficients to the ordinary power series. The passivity of the system is enforced through certain constraints on the residues.
{"title":"Black-box modelling by rational function approximation","authors":"R. Gao, Y. Mekonnen, W. Beyene, J. Schutt-Ainé","doi":"10.1109/SPI.2004.1409017","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409017","url":null,"abstract":"In this paper, a rational function approach is used to approximate the transfer function of linear systems characterized by sampled data. The ill-conditioned Vandermonde-like matrix associated with the ordinary power series is avoided by using Chebyshev polynomials. Clenshaw's recurrence algorithm is applied in transforming the Chebyshev coefficients to the ordinary power series. The passivity of the system is enforced through certain constraints on the residues.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122563045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1408996
J. R. Vázquez, M. Meijer
High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.
{"title":"Modelling the dynamic response of on-chip decoupling capacitors","authors":"J. R. Vázquez, M. Meijer","doi":"10.1109/SPI.2004.1408996","DOIUrl":"https://doi.org/10.1109/SPI.2004.1408996","url":null,"abstract":"High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409005
C. Schuster, Y. Kwark, R. Frech, E. Klink, J. Diepenbrock, G. R. Edlund, T. Gneiting, R. Modinger
Current high-end inter-processor links run hundreds of signals at Gigabit per second data rates over one or two connectors and tens of inches of backplane. Suitable connectors have to fulfil tight crosstalk, reflection, and attenuation specifications. Accurate connector measurements and models are critical to the successful design of the whole link. However, due to high pin count and interdependencies with the backplane environment connector characterization is still a challenging task. Here, a 50 Ohm single-ended, pin-in-paste prototype connector system from ERNI is analyzed in detail. Comprehensive 3D full-wave EM simulations were done and compared to measurements. Several de-embedding techniques are presented to extract the connector response from the test environment. It will be shown that the connector footprint on the backplane has a major impact on the overall electrical performance.
{"title":"Issues and challenges of Gbps backplane connector characterization","authors":"C. Schuster, Y. Kwark, R. Frech, E. Klink, J. Diepenbrock, G. R. Edlund, T. Gneiting, R. Modinger","doi":"10.1109/SPI.2004.1409005","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409005","url":null,"abstract":"Current high-end inter-processor links run hundreds of signals at Gigabit per second data rates over one or two connectors and tens of inches of backplane. Suitable connectors have to fulfil tight crosstalk, reflection, and attenuation specifications. Accurate connector measurements and models are critical to the successful design of the whole link. However, due to high pin count and interdependencies with the backplane environment connector characterization is still a challenging task. Here, a 50 Ohm single-ended, pin-in-paste prototype connector system from ERNI is analyzed in detail. Comprehensive 3D full-wave EM simulations were done and compared to measurements. Several de-embedding techniques are presented to extract the connector response from the test environment. It will be shown that the connector footprint on the backplane has a major impact on the overall electrical performance.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131179707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409036
A. Engin, W. Mathis, W. John, G. Sommer, H. Reichl
Lumped models that represent a lossy substrate with constant loss tangent over a given bandwidth are presented. Two network representations are given, which are based on the continued fraction expansion (CFE) of a causal network function, and the Debye model. Proposed models are compared with per unit length conductance and capacitance extracted from measurements of a stripline using the calibration comparison method.
{"title":"Time-domain modeling of lossy substrates with constant loss tangent","authors":"A. Engin, W. Mathis, W. John, G. Sommer, H. Reichl","doi":"10.1109/SPI.2004.1409036","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409036","url":null,"abstract":"Lumped models that represent a lossy substrate with constant loss tangent over a given bandwidth are presented. Two network representations are given, which are based on the continued fraction expansion (CFE) of a causal network function, and the Debye model. Proposed models are compared with per unit length conductance and capacitance extracted from measurements of a stripline using the calibration comparison method.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124163917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-09DOI: 10.1109/SPI.2004.1409042
M. Linderman, D. Harris, D. Diaz
On-chip inductance depends on current return paths and is unreasonably computationally expensive to extract and model in the general case. A practical solution is to provide a well-defined power supply network so the current return paths are more predictable. This paper develops a model of bus delay and noise as a function of the physical dimensions of busses and the switching parameters. It applies this model to develop bounds on the inductive effects on delay and noise for on-chip busses in 180, 130 and 100 nm processes. If one power or ground line is interdigitated with every four bus lines, the RLC noise and delay are no more than 7% greater than RC models would predict. Designers may treat this delay and noise as small penalties for all busses rather than having to individually extract and model inductance on each bus.
{"title":"Bounding bus delay and noise effects of on-chip inductance","authors":"M. Linderman, D. Harris, D. Diaz","doi":"10.1109/SPI.2004.1409042","DOIUrl":"https://doi.org/10.1109/SPI.2004.1409042","url":null,"abstract":"On-chip inductance depends on current return paths and is unreasonably computationally expensive to extract and model in the general case. A practical solution is to provide a well-defined power supply network so the current return paths are more predictable. This paper develops a model of bus delay and noise as a function of the physical dimensions of busses and the switching parameters. It applies this model to develop bounds on the inductive effects on delay and noise for on-chip busses in 180, 130 and 100 nm processes. If one power or ground line is interdigitated with every four bus lines, the RLC noise and delay are no more than 7% greater than RC models would predict. Designers may treat this delay and noise as small penalties for all busses rather than having to individually extract and model inductance on each bus.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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