Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510767
T. Yuan
Multichip module (MCM) thermal performance for flip chip and wirebond (WE) die attach packages are evaluated using four chip, uniform size ceramic substrates. Thermal characteristics of each module are evaluated by conduction parametric analyser of individual module element properties and dimensions. Thermal performance is evaluated for conditions ranging from low air now and no heat sink to high air flow with high profile heat sinks. Flip chip modules are shown to be thermally superior to WB packages in both cavity up and cavity down configurations.
{"title":"Thermal performance characteristic comparison between flip-chip wirebond ceramic multichip modules","authors":"T. Yuan","doi":"10.1109/MCMC.1996.510767","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510767","url":null,"abstract":"Multichip module (MCM) thermal performance for flip chip and wirebond (WE) die attach packages are evaluated using four chip, uniform size ceramic substrates. Thermal characteristics of each module are evaluated by conduction parametric analyser of individual module element properties and dimensions. Thermal performance is evaluated for conditions ranging from low air now and no heat sink to high air flow with high profile heat sinks. Flip chip modules are shown to be thermally superior to WB packages in both cavity up and cavity down configurations.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114827033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510764
P. Magill, P. Deane, J. D. Mis, G. Rinne
Despite the current high level of interest in flip chip technology there remain many obstacles to its widespread acceptance. These include among others: 1) the cost of the bumping, 2) the cost for redistribution 3) reliability data on the assembled product, 4) compatibility issues with dielectrics, and 5) known good die. This paper describes processes that place bumps either on the existing I/O pattern, or on a redistributed connection footprint. The problem of added cost due to redistribution will be dealt with through the use of a novel fabrication process that allows the formation of the redistributed trace and the bump in a single mask. A test method is also described which provides a full metallurgical contact for burn-in and test. Full metallurgical contact has been recognized as the technique that provides the highest quality tested die. Some of the concurrent activities at MCNC associated with the Flip Chip Technology Center (FCTC) are also described.
{"title":"Flip chip overview","authors":"P. Magill, P. Deane, J. D. Mis, G. Rinne","doi":"10.1109/MCMC.1996.510764","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510764","url":null,"abstract":"Despite the current high level of interest in flip chip technology there remain many obstacles to its widespread acceptance. These include among others: 1) the cost of the bumping, 2) the cost for redistribution 3) reliability data on the assembled product, 4) compatibility issues with dielectrics, and 5) known good die. This paper describes processes that place bumps either on the existing I/O pattern, or on a redistributed connection footprint. The problem of added cost due to redistribution will be dealt with through the use of a novel fabrication process that allows the formation of the redistributed trace and the bump in a single mask. A test method is also described which provides a full metallurgical contact for burn-in and test. Full metallurgical contact has been recognized as the technique that provides the highest quality tested die. Some of the concurrent activities at MCNC associated with the Flip Chip Technology Center (FCTC) are also described.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132749844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510785
R. Glover, L. Schaper
The Interconnected Mesh Power System (IMPS) has been developed to reduce a conventional four-layer MCM-D structure to only a two-layer structure. IMPS uses interconnected, meshed power and ground planes to replace the solid power and ground planes found in a standard four-layer topology. A prototype of each topology has been produced using the M040 MCM design as a test vehicle, which consists of a Motorola MC68040 microprocessor and four IDT 7006 dual-port SRAMs. This paper will present results of the comparison between the standard four-layer and IMPS versions of the MO40 MCM. Results are based on tests performed on the MCMs, which include a functionality test of both the processor and memory as well as electrical measurements on each version of the M040 MCM. These tests indicate comparable performance between the four layer substrate and the IMPS substrate costing half as much.
{"title":"A functional module comparison of the interconnected mesh power system (IMPS) with a standard four-layer MCM topology","authors":"R. Glover, L. Schaper","doi":"10.1109/MCMC.1996.510785","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510785","url":null,"abstract":"The Interconnected Mesh Power System (IMPS) has been developed to reduce a conventional four-layer MCM-D structure to only a two-layer structure. IMPS uses interconnected, meshed power and ground planes to replace the solid power and ground planes found in a standard four-layer topology. A prototype of each topology has been produced using the M040 MCM design as a test vehicle, which consists of a Motorola MC68040 microprocessor and four IDT 7006 dual-port SRAMs. This paper will present results of the comparison between the standard four-layer and IMPS versions of the MO40 MCM. Results are based on tests performed on the MCMs, which include a functionality test of both the processor and memory as well as electrical measurements on each version of the M040 MCM. These tests indicate comparable performance between the four layer substrate and the IMPS substrate costing half as much.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510787
S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon
In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.
{"title":"Issues in partitioning integrated circuits for MCM-D/flip-chip technology","authors":"S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon","doi":"10.1109/MCMC.1996.510787","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510787","url":null,"abstract":"In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125104000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510779
Jun-Dong Cho
We introduce an optimum algorithm for the pin redistribution problem which arises in Multi-Chip Modules. The problem is to redistribute the pins in chip layer to the pin redistribution layers, using a minimum number of layers. The proposed algorithm is based on a two-stage approach, global routing followed by layer assignment. Each subproblem has an optimality structure. Based on min-cost flow formulation along with graph manipulations, we propose a performance-driven algorithm to minimize the number of layers and also simultaneously optimize the wirelength and the number of bends.
{"title":"An optimum pin redistribution for MultiChip modules","authors":"Jun-Dong Cho","doi":"10.1109/MCMC.1996.510779","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510779","url":null,"abstract":"We introduce an optimum algorithm for the pin redistribution problem which arises in Multi-Chip Modules. The problem is to redistribute the pins in chip layer to the pin redistribution layers, using a minimum number of layers. The proposed algorithm is based on a two-stage approach, global routing followed by layer assignment. Each subproblem has an optimality structure. Based on min-cost flow formulation along with graph manipulations, we propose a performance-driven algorithm to minimize the number of layers and also simultaneously optimize the wirelength and the number of bends.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510791
Tsang-Der Ni, D. Sturzebecher
Polymer optical waveguides are being used in next generation mixed signal transmitter/receiver module combining photonic and MMIC technologies. Polymer optical couplers have the advantages of flexible chip-to-chip interconnection, low loss, small size, and easy fabrication. A center-fed mode mixing coupler and a hybrid Y-junction coupler are demonstrated and compared. Both types of couplers can be fabricated on low temperature co-fired ceramic incorporating Si and GaAs components as found in standard multi-chip modules.
{"title":"Polymer optical couplers for applications in multi-chip modules","authors":"Tsang-Der Ni, D. Sturzebecher","doi":"10.1109/MCMC.1996.510791","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510791","url":null,"abstract":"Polymer optical waveguides are being used in next generation mixed signal transmitter/receiver module combining photonic and MMIC technologies. Polymer optical couplers have the advantages of flexible chip-to-chip interconnection, low loss, small size, and easy fabrication. A center-fed mode mixing coupler and a hybrid Y-junction coupler are demonstrated and compared. Both types of couplers can be fabricated on low temperature co-fired ceramic incorporating Si and GaAs components as found in standard multi-chip modules.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510771
G. Miller, M. Salatino
Harris Semiconductor participates in the Intelligent Power (IP) market, delivering various products used in industrial and commercial power supplies and power control systems. Intelligent Power refers to the integration of analog, logic, and high power handling circuits into a single chip. Harris Semiconductor's expertise in this arena has produced products which can deliver voltages up to 100 VDC and currents in excess of 10 amperes with switching speeds under 3 nanoseconds. Switching high currents this quickly can cause damaging voltage spikes when encapsulated in plastic packages. Much of our IP customer base is concerned with power supply size and efficiency. The subtleties of developing a power supply that transcends these issues can derail even the best die and package design efforts. To assist in our customers' system-level solutions, Harris is combining our Intelligent Power devices with other normally discrete components into a low cost, high performance laminate Multi-Chip Module (MCM-L) embodiment of a major power supply building block. This paper describes Harris' effort from the problem statement to the comparative physical and performance results of the solution.
{"title":"A high frequency, high power miniature DC to DC power supply utilizing MCM-L technology","authors":"G. Miller, M. Salatino","doi":"10.1109/MCMC.1996.510771","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510771","url":null,"abstract":"Harris Semiconductor participates in the Intelligent Power (IP) market, delivering various products used in industrial and commercial power supplies and power control systems. Intelligent Power refers to the integration of analog, logic, and high power handling circuits into a single chip. Harris Semiconductor's expertise in this arena has produced products which can deliver voltages up to 100 VDC and currents in excess of 10 amperes with switching speeds under 3 nanoseconds. Switching high currents this quickly can cause damaging voltage spikes when encapsulated in plastic packages. Much of our IP customer base is concerned with power supply size and efficiency. The subtleties of developing a power supply that transcends these issues can derail even the best die and package design efforts. To assist in our customers' system-level solutions, Harris is combining our Intelligent Power devices with other normally discrete components into a low cost, high performance laminate Multi-Chip Module (MCM-L) embodiment of a major power supply building block. This paper describes Harris' effort from the problem statement to the comparative physical and performance results of the solution.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510770
P. Pieters, S. Brebels, E. Beyne
Thin film multilayer Multichip Module technology (MCM-D) may be used to realise microwave circuits such as capacitors and inductors. These may be combined to form passive filter structures. Such filters are an essential element of microwave circuits. On monolithic microwave integrated circuits, these structures require a large area resulting in a high cost. In this paper we present microwave filters integrated in multilayer MCM-D technology. As MCM-D also provides the interconnect between the individual microwave components, an integrated microwave Junction is realised, reducing the global system cost. The inductive and capacitive elements that are used to realise the filters are presented. The design of a low pass and a band pass filter using these elements is discussed. Finally, measurements of realised filters are presented.
{"title":"Integrated microwave filters in MCM-D","authors":"P. Pieters, S. Brebels, E. Beyne","doi":"10.1109/MCMC.1996.510770","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510770","url":null,"abstract":"Thin film multilayer Multichip Module technology (MCM-D) may be used to realise microwave circuits such as capacitors and inductors. These may be combined to form passive filter structures. Such filters are an essential element of microwave circuits. On monolithic microwave integrated circuits, these structures require a large area resulting in a high cost. In this paper we present microwave filters integrated in multilayer MCM-D technology. As MCM-D also provides the interconnect between the individual microwave components, an integrated microwave Junction is realised, reducing the global system cost. The inductive and capacitive elements that are used to realise the filters are presented. The design of a low pass and a band pass filter using these elements is discussed. Finally, measurements of realised filters are presented.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"38-40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123639700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510761
L. Licciardi, M. Peretti, L. Pilati, J.J. Ichai, F. Martin, Y. Urena
the high industrial importance that ATM (asynchronous transfer mode) is assuming in the telecommunication environment strongly drives technology improvements. A MCM-C 16/spl times/16 Switching Element (MCM-BASE16) for the industrial ATM cross connect UTXC is presented; implementation details are described regarding both the substate characteristics and the new IBM CCGA (ceramic column grid array) packaging technique. Electrical and thermal analysis results are reported and finally the testing methodology is presented both at the substrate and at the module level. The MCM-BASEI6 has a global throughput of 5 Gbit/s, works at 77.8 MHz and dissipates approximately 10 W at the operating frequency; these results confirm the effectiveness of this new packaging technique in obtaining high speed and area performance.
{"title":"A multichip module solution for high performance ATM switching","authors":"L. Licciardi, M. Peretti, L. Pilati, J.J. Ichai, F. Martin, Y. Urena","doi":"10.1109/MCMC.1996.510761","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510761","url":null,"abstract":"the high industrial importance that ATM (asynchronous transfer mode) is assuming in the telecommunication environment strongly drives technology improvements. A MCM-C 16/spl times/16 Switching Element (MCM-BASE16) for the industrial ATM cross connect UTXC is presented; implementation details are described regarding both the substate characteristics and the new IBM CCGA (ceramic column grid array) packaging technique. Electrical and thermal analysis results are reported and finally the testing methodology is presented both at the substrate and at the module level. The MCM-BASEI6 has a global throughput of 5 Gbit/s, works at 77.8 MHz and dissipates approximately 10 W at the operating frequency; these results confirm the effectiveness of this new packaging technique in obtaining high speed and area performance.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127759547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510762
K. Becks, E. Heijne, P. Middelkamp, L. Scharfetter, W. Snoeys
In order to build large array pixel detectors for future experiments in High Energy Physics e.g. for experiments at the Large Hadron Collider (LHC) at CERN, one needs to construct easy to handle and manufacturable able modules which can be used to put together to big detector systems. Diode- (pixel-) arrays can be fabricated in wafer size dimensions (currently about 8 cm in length); read our chips have dimensions of about 1 cm/sup 2/. A natural (but not trivial) thing would be to use the silicon diode array as the basic building block for a detector system. Several read out chips have to be bonded onto this module. For easy module interconnections the data lines, control lines, and power distributions have to be connected to the periphery of the module. To avoid complicated wiring, all lines should be integrated onto the detector substrate. Such a module could be made using multichip module (MCM) technology. Some electrical considerations of such a module and possible realizations are discussed.
{"title":"A multichip module, the basic building block for large area pixel detectors","authors":"K. Becks, E. Heijne, P. Middelkamp, L. Scharfetter, W. Snoeys","doi":"10.1109/MCMC.1996.510762","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510762","url":null,"abstract":"In order to build large array pixel detectors for future experiments in High Energy Physics e.g. for experiments at the Large Hadron Collider (LHC) at CERN, one needs to construct easy to handle and manufacturable able modules which can be used to put together to big detector systems. Diode- (pixel-) arrays can be fabricated in wafer size dimensions (currently about 8 cm in length); read our chips have dimensions of about 1 cm/sup 2/. A natural (but not trivial) thing would be to use the silicon diode array as the basic building block for a detector system. Several read out chips have to be bonded onto this module. For easy module interconnections the data lines, control lines, and power distributions have to be connected to the periphery of the module. To avoid complicated wiring, all lines should be integrated onto the detector substrate. Such a module could be made using multichip module (MCM) technology. Some electrical considerations of such a module and possible realizations are discussed.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130567986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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