Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510773
J. Oliver, H. Kerkhoff
MultiChip Modules (MCMs) are seen as a future powerful integration methodology for systems manufacturing. However, MCM testing has become one of the most challenging problem we will have to face in the next few years. In order to find cost effective solutions to the test of MCMs, test structures on active substrate must be considered. In this way, this paper presents cost analysis results based on yield calculations of test structures placed on active substrates.
{"title":"A cost analysis study of deposited-MCM active substrates for testability purposes","authors":"J. Oliver, H. Kerkhoff","doi":"10.1109/MCMC.1996.510773","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510773","url":null,"abstract":"MultiChip Modules (MCMs) are seen as a future powerful integration methodology for systems manufacturing. However, MCM testing has become one of the most challenging problem we will have to face in the next few years. In order to find cost effective solutions to the test of MCMs, test structures on active substrate must be considered. In this way, this paper presents cost analysis results based on yield calculations of test structures placed on active substrates.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133750234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510786
P. Dehkordi, K. Ramamurthi, D. Bouldin, M. Davidson
Optimization of a microelectronic system is a difficult task involving a number of different disciplines. Often, an optimization in one discipline will result in a sub-optimal solution in other areas and the overall system. This paper looks into the optimization of a microelectronics system by concurrent consideration of the micro-architecture, package, and logic partitioning. This approach will attempt to identify an optimized design by helping the designer to explore the multi-dimensional solution space and evaluate the design candidates based on their system-level cost/performance. As a demonstration vehicle, we have evaluated the SUN MicroSparc CPU for possible MCM packaging based on sets of smaller dies using this approach. Cost/performance figure-of-merits are presented for various cache sizes using cost-optimized partitioning for flip-chip MCM-D packaging.
{"title":"Early cost/performance cache analysis of a split MCM-based MicroSparc CPU","authors":"P. Dehkordi, K. Ramamurthi, D. Bouldin, M. Davidson","doi":"10.1109/MCMC.1996.510786","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510786","url":null,"abstract":"Optimization of a microelectronic system is a difficult task involving a number of different disciplines. Often, an optimization in one discipline will result in a sub-optimal solution in other areas and the overall system. This paper looks into the optimization of a microelectronics system by concurrent consideration of the micro-architecture, package, and logic partitioning. This approach will attempt to identify an optimized design by helping the designer to explore the multi-dimensional solution space and evaluate the design candidates based on their system-level cost/performance. As a demonstration vehicle, we have evaluated the SUN MicroSparc CPU for possible MCM packaging based on sets of smaller dies using this approach. Cost/performance figure-of-merits are presented for various cache sizes using cost-optimized partitioning for flip-chip MCM-D packaging.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126768579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510769
D. Dromgoole, Ahmad Lotfi, A. Feygenson, R. Frye, B. J. Han, K. Tai
A mixed signal power controller is implemented in a silicon-on-silicon MCM. The application is space limited, in which a discrete component implementation is physically large and costly. A large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog ICs. Operational characteristics of the controller are verified after integration and are compared to the discrete version. High voltage isolation requirements and interference and noise issues are studied to determine the most critical portions of the MCM layout and design.
{"title":"The application of silicon-on-silicon MCMs to advanced analog power controllers","authors":"D. Dromgoole, Ahmad Lotfi, A. Feygenson, R. Frye, B. J. Han, K. Tai","doi":"10.1109/MCMC.1996.510769","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510769","url":null,"abstract":"A mixed signal power controller is implemented in a silicon-on-silicon MCM. The application is space limited, in which a discrete component implementation is physically large and costly. A large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog ICs. Operational characteristics of the controller are verified after integration and are compared to the discrete version. High voltage isolation requirements and interference and noise issues are studied to determine the most critical portions of the MCM layout and design.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115284940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510766
J. Goldstein, E. A. Logan, B.S. Femandez
The no-flux, Utilitarian Solder System ("No-FUSS") flip-chip process is a versatile technique that can be used with virtually any die. The process combines Au ball bumping of the die with Pb/Sn-indium electroplating of the substrate. Previous work demonstrated that substrates electroplated with an 8 /spl mu/m indium cap over 16 /spl mu/m of 95Pb/5Sn had shown consistently reliable interconnects after thermal shock and thermal aging testing. Preliminary evaluations of samples with only 2 /spl mu/m of indium over 22 /spl mu/m of 95Pb/5Sn had shown promising results from a metallurgical viewpoint and further work was recommended. The current study compares the reliability and reproducibility of flip-chip interconnects prepared with a 2 /spl mu/m indium cap with previous data from 8 /spl mu/m samples. The results indicate that, although it is possible to produce low resistance, reliable interconnect using a 2 /spl mu/m indium layer, the process is nor yet as reproducible as the 8 /spl mu/m process and requires further development before it can be fully utilized.
{"title":"Fluxless flip-chip for multichip modules","authors":"J. Goldstein, E. A. Logan, B.S. Femandez","doi":"10.1109/MCMC.1996.510766","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510766","url":null,"abstract":"The no-flux, Utilitarian Solder System (\"No-FUSS\") flip-chip process is a versatile technique that can be used with virtually any die. The process combines Au ball bumping of the die with Pb/Sn-indium electroplating of the substrate. Previous work demonstrated that substrates electroplated with an 8 /spl mu/m indium cap over 16 /spl mu/m of 95Pb/5Sn had shown consistently reliable interconnects after thermal shock and thermal aging testing. Preliminary evaluations of samples with only 2 /spl mu/m of indium over 22 /spl mu/m of 95Pb/5Sn had shown promising results from a metallurgical viewpoint and further work was recommended. The current study compares the reliability and reproducibility of flip-chip interconnects prepared with a 2 /spl mu/m indium cap with previous data from 8 /spl mu/m samples. The results indicate that, although it is possible to produce low resistance, reliable interconnect using a 2 /spl mu/m indium layer, the process is nor yet as reproducible as the 8 /spl mu/m process and requires further development before it can be fully utilized.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132857531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510783
C. Truzzi, E. Beyne, E. Ringoot
Thin film Multichip Modules (MCM-D) provide a high packaging density. The short interconnection lengths on MCM-D enable high speed digital operations. The analysis of the limits of the high speed performance of such a technology is a challenging task. Individual nets on the substrate are difficult to contact during operation of the module and measuring nets using hf-probes may very well influence the operating conditions of the module. A possible solution to this problem, especially suited for digital applications, is presented here. It consists of a testing methodology focused on the characterization of the interconnection technology itself. This solution provides a way to analyze, in a real-world environment, the electrical performance of a module as a function of geometrical, technological and electrical quantities as well as circuit and system parameters. This solution can bring useful information to MCM manufacturers on the system performance and operation limits of their products, as it can be used as a benchmark to validate the interconnection technology.
{"title":"MCM-D switching units for interconnection technology validation","authors":"C. Truzzi, E. Beyne, E. Ringoot","doi":"10.1109/MCMC.1996.510783","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510783","url":null,"abstract":"Thin film Multichip Modules (MCM-D) provide a high packaging density. The short interconnection lengths on MCM-D enable high speed digital operations. The analysis of the limits of the high speed performance of such a technology is a challenging task. Individual nets on the substrate are difficult to contact during operation of the module and measuring nets using hf-probes may very well influence the operating conditions of the module. A possible solution to this problem, especially suited for digital applications, is presented here. It consists of a testing methodology focused on the characterization of the interconnection technology itself. This solution provides a way to analyze, in a real-world environment, the electrical performance of a module as a function of geometrical, technological and electrical quantities as well as circuit and system parameters. This solution can bring useful information to MCM manufacturers on the system performance and operation limits of their products, as it can be used as a benchmark to validate the interconnection technology.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132630795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-12-31DOI: 10.1109/MCMC.1996.510782
D. Benson, R. Mitchell, M. Tuck, D. Adkins, D. Palmer
Multichip modules (MCMs) containing power components need a substrate with excellent heat spreading capability both to avoid hot spots and to move dissipated heat toward the system heat sinks. Polycrystalline diamond is an excellent MCM heat spreading substrate but remains several orders of magnitude too expensive and somewhat more difficult to process than conventional mother-board materials. Today's power MCMs concentrate on moderately priced silicon wafers and aluminum nitride ceramic with their improved thermal conductivity and good thermal expansion match to power semiconductor components in comparison to traditional alumina and printed wiring board materials. However even silicon and AIN substrates are challenged by designers' thermal needs. We report on the fabrication of micro-heat pipes embedded in silicon MCM substrates (5/spl times/5 cm) by the use of micromachined capillary wick structures and hermetic micro-cavities. This passive microstructure results in more than a 5 times improvement in heat spreading capability of the silicon MCM substrate over a large range of power densities and operating temperatures. Thus diamond-like cooling is possible at silicon prices.
{"title":"Micro-machined heat pipes in silicon MCM substrates","authors":"D. Benson, R. Mitchell, M. Tuck, D. Adkins, D. Palmer","doi":"10.1109/MCMC.1996.510782","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510782","url":null,"abstract":"Multichip modules (MCMs) containing power components need a substrate with excellent heat spreading capability both to avoid hot spots and to move dissipated heat toward the system heat sinks. Polycrystalline diamond is an excellent MCM heat spreading substrate but remains several orders of magnitude too expensive and somewhat more difficult to process than conventional mother-board materials. Today's power MCMs concentrate on moderately priced silicon wafers and aluminum nitride ceramic with their improved thermal conductivity and good thermal expansion match to power semiconductor components in comparison to traditional alumina and printed wiring board materials. However even silicon and AIN substrates are challenged by designers' thermal needs. We report on the fabrication of micro-heat pipes embedded in silicon MCM substrates (5/spl times/5 cm) by the use of micromachined capillary wick structures and hermetic micro-cavities. This passive microstructure results in more than a 5 times improvement in heat spreading capability of the silicon MCM substrate over a large range of power densities and operating temperatures. Thus diamond-like cooling is possible at silicon prices.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1995-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129562308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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