Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510776
R. Khazaka, J. Poltz, M. Nakhla, Q. Zhang
Simulation of large interconnect structures has become a necessity for the design of current systems. The efficiency of moment-matching techniques has made the simulation of high-speed circuits containing large numbers of interconnect networks practically possible. In this paper a new method is proposed to extend moment-matching techniques to the analysis of interconnect networks with frequency dependent parameters. The frequency dependent interconnect parameters are extracted using the integral form of the Helmholtz equation.
{"title":"A fast method for the simulation of lossy interconnects with frequency dependent parameters","authors":"R. Khazaka, J. Poltz, M. Nakhla, Q. Zhang","doi":"10.1109/MCMC.1996.510776","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510776","url":null,"abstract":"Simulation of large interconnect structures has become a necessity for the design of current systems. The efficiency of moment-matching techniques has made the simulation of high-speed circuits containing large numbers of interconnect networks practically possible. In this paper a new method is proposed to extend moment-matching techniques to the analysis of interconnect networks with frequency dependent parameters. The frequency dependent interconnect parameters are extracted using the integral form of the Helmholtz equation.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124579788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510789
J. G. Xi, W. Dai
Noise generated by digital circuit switching is a major challenge in designing mixing-signal systems. It is important to analyze the amount of noise prior to implementation so that appropriate design decisions can be made early to avoid performance and cost pitfalls. We project the power/ground noise and substrate coupling noise as functions of digital subsystems and technology parameters. The amount of switching digital circuits and their activities are accurately modeled. This can be used as an analysis tool to evaluate tradeoffs of different system implementation approaches and technology choices in the early design stage. This analysis is based on both single chip and silicon-on-silicon MCM mixed-signal systems such that the tradeoffs between a single-chip and an MCM implementation can be evaluated. Case studies have shown our analysis are in reasonable agreement with measured and detailed circuit simulation results.
{"title":"Early system noise analysis in mixed-signal silicon-on-silicon MCM systems","authors":"J. G. Xi, W. Dai","doi":"10.1109/MCMC.1996.510789","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510789","url":null,"abstract":"Noise generated by digital circuit switching is a major challenge in designing mixing-signal systems. It is important to analyze the amount of noise prior to implementation so that appropriate design decisions can be made early to avoid performance and cost pitfalls. We project the power/ground noise and substrate coupling noise as functions of digital subsystems and technology parameters. The amount of switching digital circuits and their activities are accurately modeled. This can be used as an analysis tool to evaluate tradeoffs of different system implementation approaches and technology choices in the early design stage. This analysis is based on both single chip and silicon-on-silicon MCM mixed-signal systems such that the tradeoffs between a single-chip and an MCM implementation can be evaluated. Case studies have shown our analysis are in reasonable agreement with measured and detailed circuit simulation results.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127762622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510765
H. Nakamura, M. Tago, M. Bonkohara, A. Dohya, Ikushi Morisaki, Y. Katou
A new low cost bare-chip LSI inter-connection lead-less-chip technology was installed by Au ball-bump (1976) and Ag-Sn solder on the printed wiring board under none flux condition. Au ball-bumps were made on the LSI Al pads directly by conventional wire bonding method and Ag-Sn bumps on the leads of the build-up processed PWB by the solder micro-press punching technology less than 120 microns pads-pitch. This micro-press punching technology has reached the higher stability of 500,000 times continuously at nearly 0.1 sec/piece speed with 50 /spl mu/m thickness soft solder tape. And the diameter of punched-out solder disk was realized at 50 /spl mu/m level on the tips of the PWB pads directly. This lead-less-chip technology of the flip-chip assembly on MCM-L, has the high reliability and the low cost possibility.
{"title":"An approach to the low cost flip-chip technology development with punched-out solder disks by micro-press punching method","authors":"H. Nakamura, M. Tago, M. Bonkohara, A. Dohya, Ikushi Morisaki, Y. Katou","doi":"10.1109/MCMC.1996.510765","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510765","url":null,"abstract":"A new low cost bare-chip LSI inter-connection lead-less-chip technology was installed by Au ball-bump (1976) and Ag-Sn solder on the printed wiring board under none flux condition. Au ball-bumps were made on the LSI Al pads directly by conventional wire bonding method and Ag-Sn bumps on the leads of the build-up processed PWB by the solder micro-press punching technology less than 120 microns pads-pitch. This micro-press punching technology has reached the higher stability of 500,000 times continuously at nearly 0.1 sec/piece speed with 50 /spl mu/m thickness soft solder tape. And the diameter of punched-out solder disk was realized at 50 /spl mu/m level on the tips of the PWB pads directly. This lead-less-chip technology of the flip-chip assembly on MCM-L, has the high reliability and the low cost possibility.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129126109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510790
H. Esbensen, E.S. Euh
A genetic algorithm for building-block placement of MCMs and ICs is presented which simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, S-dimensional cost function and searching for a set of distinct solutions representing the best tradeoffs of the cost dimensions. Designers can then choose from the output set of feasible solutions. In contrast to existing approaches such as simulated annealing, neither weights nor bounds are needed, thereby eliminating the inherent practical problems of specifying these quantities. Promising results are obtained for various placement problems, including a real-world MCM design.
{"title":"An MCM/IC timing-driven placement algorithm featuring explicit design space exploration","authors":"H. Esbensen, E.S. Euh","doi":"10.1109/MCMC.1996.510790","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510790","url":null,"abstract":"A genetic algorithm for building-block placement of MCMs and ICs is presented which simultaneously minimizes layout area and an Elmore-based estimate of the maximum path delay while trying to meet a target aspect ratio. Explicit design space exploration is performed by using a vector-valued, S-dimensional cost function and searching for a set of distinct solutions representing the best tradeoffs of the cost dimensions. Designers can then choose from the output set of feasible solutions. In contrast to existing approaches such as simulated annealing, neither weights nor bounds are needed, thereby eliminating the inherent practical problems of specifying these quantities. Promising results are obtained for various placement problems, including a real-world MCM design.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"15 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130496877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510760
W. Baker
Many of us are relying more and more heavily on wireless communications in our daily activities. Portable telephones, pagers, cellular telephones, wireless LANs and WANs and many other similar devices represent the wireless world and are becoming more and more indispensable. The number of active units is forecasted to exceed one billion by the year 2000 by far surpassing the installed base of personal computers. This growth will not happen without difficulty some of which is already being experienced. Calls are dropped or noisy, pages are lost, circuits are busy or the system use is difficult, not to mention security and administrative issues. The role MCMs play in this arena is discussed. Both the opportunity and challenge to MCMs in the growth wireless communications are outlined.
{"title":"The role of MCMs in wireless communications","authors":"W. Baker","doi":"10.1109/MCMC.1996.510760","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510760","url":null,"abstract":"Many of us are relying more and more heavily on wireless communications in our daily activities. Portable telephones, pagers, cellular telephones, wireless LANs and WANs and many other similar devices represent the wireless world and are becoming more and more indispensable. The number of active units is forecasted to exceed one billion by the year 2000 by far surpassing the installed base of personal computers. This growth will not happen without difficulty some of which is already being experienced. Calls are dropped or noisy, pages are lost, circuits are busy or the system use is difficult, not to mention security and administrative issues. The role MCMs play in this arena is discussed. Both the opportunity and challenge to MCMs in the growth wireless communications are outlined.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123846973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510777
T. Winkel, L. S. Dutta, H. Grabinski, E. Groteluschen
A new method has been developed to determine the propagation constant of symmetrical coupled lossy lines. The results are based on high frequency measurements of the scattering parameters of only two coupled two line systems of different lengths. The mathematical derivation of the method is be given. The proposed method is related to an eigenvalue calculation. Results obtained from measurements are presented and discussed. A comparison between the measured and calculated results is given and shows excellent agreement.
{"title":"Determination of the propagation constant of coupled lines on chips based on high frequency measurements","authors":"T. Winkel, L. S. Dutta, H. Grabinski, E. Groteluschen","doi":"10.1109/MCMC.1996.510777","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510777","url":null,"abstract":"A new method has been developed to determine the propagation constant of symmetrical coupled lossy lines. The results are based on high frequency measurements of the scattering parameters of only two coupled two line systems of different lengths. The mathematical derivation of the method is be given. The proposed method is related to an eigenvalue calculation. Results obtained from measurements are presented and discussed. A comparison between the measured and calculated results is given and shows excellent agreement.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126754996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510794
M. Çelik, A. Cangellaris, A. Deutsch
In this paper we propose a new method for moment calculation appropriate for dispersive, lossy interconnects and related package discontinuities, transitions and junctions that are modeled in terms of either numerically extracted or measured frequency-dependent scattering parameters. The method first constructs a local regional function approximation to the frequency domain measured data around an expansion point, and then finds the moments easily from the rational function. Comparisons with real measurements are presented which demonstrate the validity and accuracy of the proposed method.
{"title":"A new moment generation technique for interconnects characterized by measured or calculated S-parameters","authors":"M. Çelik, A. Cangellaris, A. Deutsch","doi":"10.1109/MCMC.1996.510794","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510794","url":null,"abstract":"In this paper we propose a new method for moment calculation appropriate for dispersive, lossy interconnects and related package discontinuities, transitions and junctions that are modeled in terms of either numerically extracted or measured frequency-dependent scattering parameters. The method first constructs a local regional function approximation to the frequency domain measured data around an expansion point, and then finds the moments easily from the rational function. Comparisons with real measurements are presented which demonstrate the validity and accuracy of the proposed method.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116962071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510784
H. Blennemann, Yaoyao Yang, R. Nikel
A 400 Mbps single-ended off-chip link including an open-drain driver and quasi-differential receiver has been designed, simulated, and measured. In this work, the design choices, in particular as related to noise tolerance, are discussed. To reduce the reflections inherent in signal propagation at a 400 Mbps rate, both the data and clock interconnects are restricted to non-resonant lengths. To further improve impedance matching, a daisy-chain termination is evaluated in which the net termination occurs after rather than before, the package pin. Other methods of reducing reflection noise are discussed, such as providing resistor terminations on an SCM or MCM package in order to reduce stub lengths. Measurements indicate good agreement with simulation; when the link is implemented with the noise-reducing features described the measured noise and jitter is sufficiently low for reliable operation at 400 Mbps.
{"title":"Off-chip 400 Mbps signal transmission: noise reduction using non-resonant lengths and other techniques","authors":"H. Blennemann, Yaoyao Yang, R. Nikel","doi":"10.1109/MCMC.1996.510784","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510784","url":null,"abstract":"A 400 Mbps single-ended off-chip link including an open-drain driver and quasi-differential receiver has been designed, simulated, and measured. In this work, the design choices, in particular as related to noise tolerance, are discussed. To reduce the reflections inherent in signal propagation at a 400 Mbps rate, both the data and clock interconnects are restricted to non-resonant lengths. To further improve impedance matching, a daisy-chain termination is evaluated in which the net termination occurs after rather than before, the package pin. Other methods of reducing reflection noise are discussed, such as providing resistor terminations on an SCM or MCM package in order to reduce stub lengths. Measurements indicate good agreement with simulation; when the link is implemented with the noise-reducing features described the measured noise and jitter is sufficiently low for reliable operation at 400 Mbps.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123992845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510772
L. Guérin, R. Sachot, M. Dutoit
A new multichip-on-silicon packaging scheme for microelectronic circuits, sensors and actuators is presented. Its main characteristics and advantages over other schemes are discussed. A description of some key fabrication steps is given. Finally, the realization and the characterization of passive integrated components such as inductors and capacitors are discussed.
{"title":"A new multichip-on-silicon packaging scheme with integrated passive components","authors":"L. Guérin, R. Sachot, M. Dutoit","doi":"10.1109/MCMC.1996.510772","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510772","url":null,"abstract":"A new multichip-on-silicon packaging scheme for microelectronic circuits, sensors and actuators is presented. Its main characteristics and advantages over other schemes are discussed. A description of some key fabrication steps is given. Finally, the realization and the characterization of passive integrated components such as inductors and capacitors are discussed.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-06DOI: 10.1109/MCMC.1996.510767
T. Yuan
Multichip module (MCM) thermal performance for flip chip and wirebond (WE) die attach packages are evaluated using four chip, uniform size ceramic substrates. Thermal characteristics of each module are evaluated by conduction parametric analyser of individual module element properties and dimensions. Thermal performance is evaluated for conditions ranging from low air now and no heat sink to high air flow with high profile heat sinks. Flip chip modules are shown to be thermally superior to WB packages in both cavity up and cavity down configurations.
{"title":"Thermal performance characteristic comparison between flip-chip wirebond ceramic multichip modules","authors":"T. Yuan","doi":"10.1109/MCMC.1996.510767","DOIUrl":"https://doi.org/10.1109/MCMC.1996.510767","url":null,"abstract":"Multichip module (MCM) thermal performance for flip chip and wirebond (WE) die attach packages are evaluated using four chip, uniform size ceramic substrates. Thermal characteristics of each module are evaluated by conduction parametric analyser of individual module element properties and dimensions. Thermal performance is evaluated for conditions ranging from low air now and no heat sink to high air flow with high profile heat sinks. Flip chip modules are shown to be thermally superior to WB packages in both cavity up and cavity down configurations.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114827033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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