Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301700
{"title":"APCCAS 2020 Index","authors":"","doi":"10.1109/apccas50809.2020.9301700","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301700","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301678
Burak Acar, T. Karalar
Chaotic systems have to be carefully designed in critical applications. Therefore, these systems need high-quality cryptanalysis methods to make sure they work securely. In this paper, a three dimensional no-equilibrium chaotic system to produce random number bits is analyzed with giving numerical and experimental results. Generating random numbers/bits is vital in security systems since they require unpredictable values to keep the key securely for the attackers. The master-slave synchronization method is used to present the security weakness of the "novel" no-equilibrium chaotic system with hidden attractors. The no equilibrium chaotic system is analyzed with a scalar time series. The simulation and experimental results demonstrate that random number bits generated through the target chaotic system can be estimated because its randomness is based on deterministic sources.
{"title":"Experimental Cryptanalysis of No-equilibrium Chaotic System Based Random Number Generator","authors":"Burak Acar, T. Karalar","doi":"10.1109/APCCAS50809.2020.9301678","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301678","url":null,"abstract":"Chaotic systems have to be carefully designed in critical applications. Therefore, these systems need high-quality cryptanalysis methods to make sure they work securely. In this paper, a three dimensional no-equilibrium chaotic system to produce random number bits is analyzed with giving numerical and experimental results. Generating random numbers/bits is vital in security systems since they require unpredictable values to keep the key securely for the attackers. The master-slave synchronization method is used to present the security weakness of the \"novel\" no-equilibrium chaotic system with hidden attractors. The no equilibrium chaotic system is analyzed with a scalar time series. The simulation and experimental results demonstrate that random number bits generated through the target chaotic system can be estimated because its randomness is based on deterministic sources.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124225493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301659
{"title":"APCCAS 2020 TOC","authors":"","doi":"10.1109/apccas50809.2020.9301659","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301659","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124233238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301662
Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, K. Mori
In studying damage detection in timber using the Timber Health Monitoring system, we have succeeded in classifying the positions of the weight of the timber by using vibration waveforms with machine learning. In this study, we investigated the generalization performance of the system, which is indispensable for practical applications. Previous studies have yet to confirm this type of performance. We prepared 90 timber pieces as we expected that the system's performance would be improved if more timbers were learned. We divided the pieces into nine classes, representing no damage and damage to eight different positions, respectively. A piezoelectric sensor was attached to the pieces to acquire their vibration waveforms. The waveforms were divided into training and evaluation data, and a neural network (NN) was used to learn the training data and classify the evaluation data. As a result, we found that the NN was able to classify the positions of the damage or no damage with up to 83.8% accuracy, even for unlearned timber pieces. This demonstrated good generalization performance in the Timber Health Monitoring system.
{"title":"Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning","authors":"Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, K. Mori","doi":"10.1109/APCCAS50809.2020.9301662","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301662","url":null,"abstract":"In studying damage detection in timber using the Timber Health Monitoring system, we have succeeded in classifying the positions of the weight of the timber by using vibration waveforms with machine learning. In this study, we investigated the generalization performance of the system, which is indispensable for practical applications. Previous studies have yet to confirm this type of performance. We prepared 90 timber pieces as we expected that the system's performance would be improved if more timbers were learned. We divided the pieces into nine classes, representing no damage and damage to eight different positions, respectively. A piezoelectric sensor was attached to the pieces to acquire their vibration waveforms. The waveforms were divided into training and evaluation data, and a neural network (NN) was used to learn the training data and classify the evaluation data. As a result, we found that the NN was able to classify the positions of the damage or no damage with up to 83.8% accuracy, even for unlearned timber pieces. This demonstrated good generalization performance in the Timber Health Monitoring system.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123137101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301674
Marcus Miguel V. Vicedo, F. Cruz, Ramon G. Garcia
This work developed a copper (Cu) coin structure embedded on a printed circuit board (PCB) to dissipate a 12 W peak power out of the device system working at less than 60 °C. The designed Cu coin was based on the manufacturing limitations and allowed the thermal setup to be mounted on the bottom side of the board for automated test equipment (ATE) applications of the device. Thermal simulations through computational fluid dynamics (CFD) were analyzed and presented both for Cu coin and thermal vertical interconnect access (VIA), to quantify the thermal performances and compare the thermal benefits. Size variations on the designed Cu coin were investigated and quantified setting a thermal decay rate per change in dimension. The actual thermal measurement for the fabricated Cu coin design was presented on the experimental results, matching the simulation values and proving the viability of thermal Cu coin.
{"title":"Copper Coin Over Thermal VIA in PCB for Thermal Management of 12W","authors":"Marcus Miguel V. Vicedo, F. Cruz, Ramon G. Garcia","doi":"10.1109/APCCAS50809.2020.9301674","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301674","url":null,"abstract":"This work developed a copper (Cu) coin structure embedded on a printed circuit board (PCB) to dissipate a 12 W peak power out of the device system working at less than 60 °C. The designed Cu coin was based on the manufacturing limitations and allowed the thermal setup to be mounted on the bottom side of the board for automated test equipment (ATE) applications of the device. Thermal simulations through computational fluid dynamics (CFD) were analyzed and presented both for Cu coin and thermal vertical interconnect access (VIA), to quantify the thermal performances and compare the thermal benefits. Size variations on the designed Cu coin were investigated and quantified setting a thermal decay rate per change in dimension. The actual thermal measurement for the fabricated Cu coin design was presented on the experimental results, matching the simulation values and proving the viability of thermal Cu coin.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130857803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Underwater real-time object recognition is essential to unmanned underwater drones, namely autonomous underwater vehicles (AUV), cruising in the ocean. As the deep learning technology evolves swiftly lately, the attempt for AUVs to fully understand the surrounding environment becomes an emerging demand for marine or military applications. No matter which approach that deep learning manages to adopt, a large dataset with sufficient number of images for each object is required. In this investigation, a dataset augmentation method based on 3D modeling is proposed to resolve the mentioned problem. By rotating and scaling the target object in 3 dimensions with different backgrounds, the number of underwater object images is increased over 1000 times. Through the proposed method, high quality image data are forged to improve the recognition accuracy of those rare underwater objects, which are very hard to collect enough number of images, by 20% based on real-time video clips’ experiment.
{"title":"3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations*","authors":"Chua-Chin Wang, Chia-Yi Huang, Chu-Han Lin, C. Yeh, Guan-Xian Liu, Yu-Cheng Chou","doi":"10.1109/APCCAS50809.2020.9301679","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301679","url":null,"abstract":"Underwater real-time object recognition is essential to unmanned underwater drones, namely autonomous underwater vehicles (AUV), cruising in the ocean. As the deep learning technology evolves swiftly lately, the attempt for AUVs to fully understand the surrounding environment becomes an emerging demand for marine or military applications. No matter which approach that deep learning manages to adopt, a large dataset with sufficient number of images for each object is required. In this investigation, a dataset augmentation method based on 3D modeling is proposed to resolve the mentioned problem. By rotating and scaling the target object in 3 dimensions with different backgrounds, the number of underwater object images is increased over 1000 times. Through the proposed method, high quality image data are forged to improve the recognition accuracy of those rare underwater objects, which are very hard to collect enough number of images, by 20% based on real-time video clips’ experiment.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121507131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301660
Xianfeng Tang, Peining Zhen, M. Kang, Hang Yi, Wei Wang, Hai-Bao Chen
Video denoising is of great significance in video processing when shooting conditions are complex such as dynamic scenes and low light. Although existing algorithms have already achieved remarkable denoising performance, the inference time of them is usually impractical for real-time applications. In this paper, we propose a convolutional neural network architecture for video denoising. In contrast to other existing CNN-based methods, our approach utilizes different proportion convolutional kernel numbers in a block for extracting enriched features. Channel attention mechanism is integrated in the network to enhance the denoising performance. The network only needs three contiguous frames and noise map as inputs, which leads to a similar excellent running time to the state-of-the-art. We compare our method with different conventional algorithms VBM4D, VNLB and the state-of-the-art CNN-based method FastDVDnet. Experiment results indicate that our method outputs more convincing results in visual and more robustness than others in both peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) indexes.
{"title":"Learning Enriched Features for Video Denoising with Convolutional Neural Network","authors":"Xianfeng Tang, Peining Zhen, M. Kang, Hang Yi, Wei Wang, Hai-Bao Chen","doi":"10.1109/APCCAS50809.2020.9301660","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301660","url":null,"abstract":"Video denoising is of great significance in video processing when shooting conditions are complex such as dynamic scenes and low light. Although existing algorithms have already achieved remarkable denoising performance, the inference time of them is usually impractical for real-time applications. In this paper, we propose a convolutional neural network architecture for video denoising. In contrast to other existing CNN-based methods, our approach utilizes different proportion convolutional kernel numbers in a block for extracting enriched features. Channel attention mechanism is integrated in the network to enhance the denoising performance. The network only needs three contiguous frames and noise map as inputs, which leads to a similar excellent running time to the state-of-the-art. We compare our method with different conventional algorithms VBM4D, VNLB and the state-of-the-art CNN-based method FastDVDnet. Experiment results indicate that our method outputs more convincing results in visual and more robustness than others in both peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) indexes.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301687
Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang
Fixed-point quantization techniques have attracted considerable attention in deep neural network (DNN) inference acceleration. Nevertheless, they often require time-consuming fine-tuning or retraining to keep the accuracy of a quantized model. Besides, DNNs involve massive multiplication operations, which are of much higher computational complexities compared with addition operations. To deal with the two problems, we propose an improved numerical format named logarithmic block floating point (LBFP) for post-training quantization. Firstly, logarithmic arithmetic is employed to convert multiplication operations to addition and shift operations. Then, Kullback-Leibler divergence is used to determine the shared exponent before inference. Thus, LBFP can significantly reduce the hard-ware complexity with negligible performance loss. Moreover, an efficient hardware architecture is designed to support the computation of LBFP. Hardware synthesis results show that our 8-bit LBFP multiplier can reduce power and area by 53% and 45%, respectively, compared with the 8-bit traditional fixed-point multiplier. Finally, a software library is developed with the CUDA-C language to evaluate the inference accuracy of LBFP. Without retraining, the accuracy of the selected DNN models with the 8-bit LBFP representation is comparable to that of the corresponding 32-bit floating-point baselines, showing the great potential in efficient DNN inference acceleration.
{"title":"LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks","authors":"Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang","doi":"10.1109/APCCAS50809.2020.9301687","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301687","url":null,"abstract":"Fixed-point quantization techniques have attracted considerable attention in deep neural network (DNN) inference acceleration. Nevertheless, they often require time-consuming fine-tuning or retraining to keep the accuracy of a quantized model. Besides, DNNs involve massive multiplication operations, which are of much higher computational complexities compared with addition operations. To deal with the two problems, we propose an improved numerical format named logarithmic block floating point (LBFP) for post-training quantization. Firstly, logarithmic arithmetic is employed to convert multiplication operations to addition and shift operations. Then, Kullback-Leibler divergence is used to determine the shared exponent before inference. Thus, LBFP can significantly reduce the hard-ware complexity with negligible performance loss. Moreover, an efficient hardware architecture is designed to support the computation of LBFP. Hardware synthesis results show that our 8-bit LBFP multiplier can reduce power and area by 53% and 45%, respectively, compared with the 8-bit traditional fixed-point multiplier. Finally, a software library is developed with the CUDA-C language to evaluate the inference accuracy of LBFP. Without retraining, the accuracy of the selected DNN models with the 8-bit LBFP representation is comparable to that of the corresponding 32-bit floating-point baselines, showing the great potential in efficient DNN inference acceleration.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301668
Pham-Khoi Dong, Hung K. Nguyen, Van‐Phuc Hoang, Xuan-Tu Tran
Nowadays, the Internet of Things (IoT) has been a focus of research that improves and optimizes our daily life based on intelligent sensors and smart objects working together. Thanks to Internet Protocol connectivity, devices can be connected to the Internet, thus allowing them to be read, controlled, and managed at any time and at any place. Security and privacy are the key issues for deploying IoT applications, and still face some enormous challenges; especially, for devices that require high throughput and low latency as IoT cameras, IoT gateways, high-quality video conferencing systems… In this paper, we proposed a 10-cores AES hardware architecture to achieve high throughput. These cores shared KeyExpansion Block so this architecture has high efficiency in term of area and power consumption. Fully parallel, outer round pipeline technique is also used to achieve low latency. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. On the other hand, clock gating technique is used to save power consumption. We use PrimeTime tool (Synopsys) to estimate the power consumption. Implementation results show that the proposed architecture achieves a throughput of 853.8 Gbps at the maximum operating frequency of 667 MHz and clock gating technique allows more power savings.
{"title":"Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture","authors":"Pham-Khoi Dong, Hung K. Nguyen, Van‐Phuc Hoang, Xuan-Tu Tran","doi":"10.1109/APCCAS50809.2020.9301668","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301668","url":null,"abstract":"Nowadays, the Internet of Things (IoT) has been a focus of research that improves and optimizes our daily life based on intelligent sensors and smart objects working together. Thanks to Internet Protocol connectivity, devices can be connected to the Internet, thus allowing them to be read, controlled, and managed at any time and at any place. Security and privacy are the key issues for deploying IoT applications, and still face some enormous challenges; especially, for devices that require high throughput and low latency as IoT cameras, IoT gateways, high-quality video conferencing systems… In this paper, we proposed a 10-cores AES hardware architecture to achieve high throughput. These cores shared KeyExpansion Block so this architecture has high efficiency in term of area and power consumption. Fully parallel, outer round pipeline technique is also used to achieve low latency. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. On the other hand, clock gating technique is used to save power consumption. We use PrimeTime tool (Synopsys) to estimate the power consumption. Implementation results show that the proposed architecture achieves a throughput of 853.8 Gbps at the maximum operating frequency of 667 MHz and clock gating technique allows more power savings.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301644
{"title":"APCCAS 2020 Cover Page","authors":"","doi":"10.1109/apccas50809.2020.9301644","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301644","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132984856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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