In this paper, a hardware-oriented lossless EEG compression algorithm including a two-stage prediction, voting prediction and tri-entropy coding is proposed. In two stages prediction, 27 conditions and 6 functions are used to decide how to predict the current data from previous data. Then, voting prediction finds optimal function according to 27 conditions for best function to produce best Error (the difference of predicted data and current data). Moreover, a tri-entropy coding technique is developed based on normal distribution. The two-stage Huffman coding and Golomb-Rice coding was used to generate the binary code of Error value. In CHB-MIT Scalp EEG Database, the novel EEG compression algorithm achieves average compression rate to 2.37. The proposed hardware-oriented algorithm is suitable for VLSI implementation due to its low complexity.
{"title":"Lossless EEG Compression Algorithm Based on Semi-Supervised Learning for VLSI Implementation","authors":"Yi-Hong Chen, Yan-Ting Liu, Tsun-Kuang Chi, Chiung-An Chen, Yih-Shyh Chiou, Ting-Lan Lin, Shih-Lun Chen","doi":"10.1109/APCCAS50809.2020.9301714","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301714","url":null,"abstract":"In this paper, a hardware-oriented lossless EEG compression algorithm including a two-stage prediction, voting prediction and tri-entropy coding is proposed. In two stages prediction, 27 conditions and 6 functions are used to decide how to predict the current data from previous data. Then, voting prediction finds optimal function according to 27 conditions for best function to produce best Error (the difference of predicted data and current data). Moreover, a tri-entropy coding technique is developed based on normal distribution. The two-stage Huffman coding and Golomb-Rice coding was used to generate the binary code of Error value. In CHB-MIT Scalp EEG Database, the novel EEG compression algorithm achieves average compression rate to 2.37. The proposed hardware-oriented algorithm is suitable for VLSI implementation due to its low complexity.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301705
Ziwei Li, Wenbin He, Fan Ye, Junyan Ren
An energy-efficient dynamic comparator is presented and analyzed in this paper. The pre-amplifier is dynamically powered by a floating reservoir capacitor and consists of an inverter-based CMOS input pair embedded in a latch. The dynamic power source enables input common-mode voltage insensitivity and the latch-embedding reduces its delay time and power consumption. The proposed comparator is simulated in 28-nm CMOS technology. It is shown that the delay time and energy efficiency are improved then the prior floating preamplifier comparator. The maximum clock frequency reaches 1.8 GHz, consuming only 0.7 pJ per comparison while achieving 30-μV input-referred noise. The energy efficiency is increased threefold than the previous floating pre-amplifier comparator with a faster comparator decision.
{"title":"A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier","authors":"Ziwei Li, Wenbin He, Fan Ye, Junyan Ren","doi":"10.1109/APCCAS50809.2020.9301705","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301705","url":null,"abstract":"An energy-efficient dynamic comparator is presented and analyzed in this paper. The pre-amplifier is dynamically powered by a floating reservoir capacitor and consists of an inverter-based CMOS input pair embedded in a latch. The dynamic power source enables input common-mode voltage insensitivity and the latch-embedding reduces its delay time and power consumption. The proposed comparator is simulated in 28-nm CMOS technology. It is shown that the delay time and energy efficiency are improved then the prior floating preamplifier comparator. The maximum clock frequency reaches 1.8 GHz, consuming only 0.7 pJ per comparison while achieving 30-μV input-referred noise. The energy efficiency is increased threefold than the previous floating pre-amplifier comparator with a faster comparator decision.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124041971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301713
Yeqing Wang, Zhouchen Ma, Yan Liu, Jian Zhao, Lei Zhang, Zongmin Wang
This paper presents a sub-sampling phase-locked loop with shorter locking time. An ultra-mini dead zone is proposed to increase the operation region of the high-gain frequency-locked loop, such that a fast settling can be achieved. A phase error adaptive charging pump control scheme is implemented to tune the phase/frequency detector’s outputs according to the remaining phase error. Simulation results show that it takes 2.5 μs for the system to settle down. When a step change of 100 or 500 mV is applied on the control voltage of the voltage-controlled oscillator, it takes 2 μs or 1.25 μs for the system to re-lock. When the divider ratio is reduced from 44 to 43, it takes 2 μs for the system to return to the locking state.
{"title":"Sub-Sampling Phase-Locked Loop with Ultra-mini Dead Zone For Locking Time Reduction","authors":"Yeqing Wang, Zhouchen Ma, Yan Liu, Jian Zhao, Lei Zhang, Zongmin Wang","doi":"10.1109/APCCAS50809.2020.9301713","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301713","url":null,"abstract":"This paper presents a sub-sampling phase-locked loop with shorter locking time. An ultra-mini dead zone is proposed to increase the operation region of the high-gain frequency-locked loop, such that a fast settling can be achieved. A phase error adaptive charging pump control scheme is implemented to tune the phase/frequency detector’s outputs according to the remaining phase error. Simulation results show that it takes 2.5 μs for the system to settle down. When a step change of 100 or 500 mV is applied on the control voltage of the voltage-controlled oscillator, it takes 2 μs or 1.25 μs for the system to re-lock. When the divider ratio is reduced from 44 to 43, it takes 2 μs for the system to return to the locking state.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132848461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301652
Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren
This paper presents a 16-channel 14bit 50MS/s ADC designed with a 0.18μm process, used in integrated ultrasound imaging systems. The design considerations of stage resolution distribution are thoroughly discussed. The optimal stage resolution for a 14bit pipelined-SAR is "5-5-6", achieving the best power and area efficiency. According to this, the prototype chip is designed with complete peripheral circuits including LVDS, SPI, bandgap, etc. The measurement results show that this compact design features the highest resolution and SNDR among recent designs with a competitive FoM.
{"title":"A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems","authors":"Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren","doi":"10.1109/APCCAS50809.2020.9301652","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301652","url":null,"abstract":"This paper presents a 16-channel 14bit 50MS/s ADC designed with a 0.18μm process, used in integrated ultrasound imaging systems. The design considerations of stage resolution distribution are thoroughly discussed. The optimal stage resolution for a 14bit pipelined-SAR is \"5-5-6\", achieving the best power and area efficiency. According to this, the prototype chip is designed with complete peripheral circuits including LVDS, SPI, bandgap, etc. The measurement results show that this compact design features the highest resolution and SNDR among recent designs with a competitive FoM.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134083726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301683
Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
The Internet of Things (IoT) with the advancements of many technologies opens a wide range of new applications such as smart appliances, smart cities and smart grids. Despite its popularity and usability, it also creates a new attack surface for the hackers especially on highly constrained devices which have limited memory footprints and processing power. These constrained devices often use Authenticated Encryption with Associated Data (AEAD) to secure data stored in the devices and transmitted over the network. In this work, we design a lightweight data encryption core in hardware with the support for AEAD to secure IoT applications on highly constrained devices. The design achieves a low area cost with only 23kGEs in TSMC 65nm technology and an encryption throughput of 123Mbps at 60MHz.
{"title":"A Lightweight AEAD encryption core to secure IoT applications","authors":"Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran","doi":"10.1109/APCCAS50809.2020.9301683","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301683","url":null,"abstract":"The Internet of Things (IoT) with the advancements of many technologies opens a wide range of new applications such as smart appliances, smart cities and smart grids. Despite its popularity and usability, it also creates a new attack surface for the hackers especially on highly constrained devices which have limited memory footprints and processing power. These constrained devices often use Authenticated Encryption with Associated Data (AEAD) to secure data stored in the devices and transmitted over the network. In this work, we design a lightweight data encryption core in hardware with the support for AEAD to secure IoT applications on highly constrained devices. The design achieves a low area cost with only 23kGEs in TSMC 65nm technology and an encryption throughput of 123Mbps at 60MHz.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132950564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301710
Hongyu Gu, Zhecheng Yang, Hong Chen
Tongue diagnosis is an important and widely used diagnosis method in traditional Chinese medicine. Automatic tongue segmentation is crucial in the digital tongue diagnosis system. In this paper, an automatic tongue segmentation algorithm is proposed, which consists of two steps. In the first step, a thresholding method that combines color and gray level information is designed, which provides the initial contour needed in the second step. Next, an improved level set model based on geodesic active contour and Chan Vese model is put forward for boundary refinement. The weight function of the new model is adapted for a better balance of two sub-models. Experiment results show that the segmented area is more complete and closer to the real target with a lowest average ME value of 0.081 compared with other methods. The robustness of our algorithm is also verified by different tongue images in terms of shapes, lighting conditions and resolutions.
{"title":"Automatic Tongue Image Segmentation Based on Thresholding and an Improved Level Set Model","authors":"Hongyu Gu, Zhecheng Yang, Hong Chen","doi":"10.1109/APCCAS50809.2020.9301710","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301710","url":null,"abstract":"Tongue diagnosis is an important and widely used diagnosis method in traditional Chinese medicine. Automatic tongue segmentation is crucial in the digital tongue diagnosis system. In this paper, an automatic tongue segmentation algorithm is proposed, which consists of two steps. In the first step, a thresholding method that combines color and gray level information is designed, which provides the initial contour needed in the second step. Next, an improved level set model based on geodesic active contour and Chan Vese model is put forward for boundary refinement. The weight function of the new model is adapted for a better balance of two sub-models. Experiment results show that the segmented area is more complete and closer to the real target with a lowest average ME value of 0.081 compared with other methods. The robustness of our algorithm is also verified by different tongue images in terms of shapes, lighting conditions and resolutions.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133318188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301684
Chua-Chin Wang, S. Lu
This investigation demonstrates a wide bandwidth random number generator (RNG) based on interleaved NAND-/NOR-based SR (set-reset) latches. More specifically, the metastability of SR latches driven by the same input causing undefined output states is exploited. To achieve higher irregular sampling of the SR latches, not only NAND-based SR latches and NOR-based SR latches are interleaved integrated, their inputs are also randomly selected by another array of metastable SR latches. Namely, a 2-layer RNG architecture is realized to avoid locking phenomenon and enhance randomness. The proposed 2-layer RNG is realized using typical 40-nm CMOS process. All-PTV-corner (process, temperature, voltage) post-layout simulations validate that the proposed RNG passes long run test and mono-bit test given 100 MHz clock rate.
{"title":"100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*","authors":"Chua-Chin Wang, S. Lu","doi":"10.1109/APCCAS50809.2020.9301684","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301684","url":null,"abstract":"This investigation demonstrates a wide bandwidth random number generator (RNG) based on interleaved NAND-/NOR-based SR (set-reset) latches. More specifically, the metastability of SR latches driven by the same input causing undefined output states is exploited. To achieve higher irregular sampling of the SR latches, not only NAND-based SR latches and NOR-based SR latches are interleaved integrated, their inputs are also randomly selected by another array of metastable SR latches. Namely, a 2-layer RNG architecture is realized to avoid locking phenomenon and enhance randomness. The proposed 2-layer RNG is realized using typical 40-nm CMOS process. All-PTV-corner (process, temperature, voltage) post-layout simulations validate that the proposed RNG passes long run test and mono-bit test given 100 MHz clock rate.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114869783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301697
Celal Erbay, Salih Ergün
Random number generators (RNG) are important hardware primitives for many fields including secure communication, cryptology, weather forecast, gambling that needs unpredictable and non-deterministic random bit sequences. Various entropy sources are available to generate random numbers and generation rate depends on the application that needs to use random numbers. In this work, a new approach is given to generate random bits based on miniature microbial fuel cells that convert electrochemical energy into electricity. Microorganisms inside of the microbial fuel cell play a critical role to generate electricity therefore it is unpredictable what they will produce. An output voltage generated by the microbial fuel cells used to produce random bits then it was shown that they were successfully passed the NIST 800-22 statistical randomness tests after the XOR corrector post-processing method. The proposed approach can be especially used in environmental applications that need secure data transfer and bioreactors that have to securely send critical data to headquarter.
{"title":"Random Number Generator Based on Miniature Microbial Fuel Cells","authors":"Celal Erbay, Salih Ergün","doi":"10.1109/APCCAS50809.2020.9301697","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301697","url":null,"abstract":"Random number generators (RNG) are important hardware primitives for many fields including secure communication, cryptology, weather forecast, gambling that needs unpredictable and non-deterministic random bit sequences. Various entropy sources are available to generate random numbers and generation rate depends on the application that needs to use random numbers. In this work, a new approach is given to generate random bits based on miniature microbial fuel cells that convert electrochemical energy into electricity. Microorganisms inside of the microbial fuel cell play a critical role to generate electricity therefore it is unpredictable what they will produce. An output voltage generated by the microbial fuel cells used to produce random bits then it was shown that they were successfully passed the NIST 800-22 statistical randomness tests after the XOR corrector post-processing method. The proposed approach can be especially used in environmental applications that need secure data transfer and bioreactors that have to securely send critical data to headquarter.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301709
Chia-Heng Lee, Ying-Tuan Hsu, Tsung-Te Liu, T. Chiueh
In memory computation for machine learning (ML) applications is a novel technique for neural-network computation accelerators, since it is highly parallel and can save a great amount of computation and memory access power. In this paper, we propose a compute in memory (CIM) design based on a new type of high-performance transistor, called Negative Capacitance Field Effect Transistor (NCFET). The proposed design demonstrates much higher energy efficiency than the CIM designs based on traditional CMOS transistors. Simulation results show that the proposed NCFET CIM achieves 3X energy reduction or 18X speed enhancement than the CMOS based CIM design.
{"title":"Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications","authors":"Chia-Heng Lee, Ying-Tuan Hsu, Tsung-Te Liu, T. Chiueh","doi":"10.1109/APCCAS50809.2020.9301709","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301709","url":null,"abstract":"In memory computation for machine learning (ML) applications is a novel technique for neural-network computation accelerators, since it is highly parallel and can save a great amount of computation and memory access power. In this paper, we propose a compute in memory (CIM) design based on a new type of high-performance transistor, called Negative Capacitance Field Effect Transistor (NCFET). The proposed design demonstrates much higher energy efficiency than the CIM designs based on traditional CMOS transistors. Simulation results show that the proposed NCFET CIM achieves 3X energy reduction or 18X speed enhancement than the CMOS based CIM design.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131795502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301677
Yuya Maekawa, Syuya Nakagawa, H. Ishikuro
This paper proposes a low power amp-less interface circuit for capacitive sensors. In the proposed circuit, the charge on the sensor capacitance is compared to the charge on the reference capacitance and converted to a digital value by SAR logic. The proposed circuit can achieve high linearity by using a 1-bit digital ΔΣ modulator and single reference capacitance. The effectiveness of the proposed system was demonstrated by system simulation.
{"title":"A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC","authors":"Yuya Maekawa, Syuya Nakagawa, H. Ishikuro","doi":"10.1109/APCCAS50809.2020.9301677","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301677","url":null,"abstract":"This paper proposes a low power amp-less interface circuit for capacitive sensors. In the proposed circuit, the charge on the sensor capacitance is compared to the charge on the reference capacitance and converted to a digital value by SAR logic. The proposed circuit can achieve high linearity by using a 1-bit digital ΔΣ modulator and single reference capacitance. The effectiveness of the proposed system was demonstrated by system simulation.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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