Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301666
Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, B. Gwee
We propose a high efficiency Early-Complete Brute Force Elimination method that speeds up the analysis flow of the Camouflage Integrated Circuit (IC). The proposed method is targeted for security qualification of the Camouflaged IC netlists in Intellectual Property (IP) protection. There are two main features in the proposed method. First, the proposed method features immediate elimination of the incorrect Camouflage gates combination for the rest of computation, concentrating the resources into other potential correct Camouflage gates combination. Second, the proposed method features early complete, i.e. revealing the correct Camouflage gates once all incorrect gates combination are eliminated, increasing the computation speed for the overall security analysis. Based on the Python programming platform, we implement the algorithm of the proposed method and test it for three circuits including ISCAS’89 benchmarks. From the simulation results, our proposed method, on average, features 71% lesser number of trials and 79% shorter run time as compared to the conventional method in revealing the correct Camouflage gates from the Camouflaged IC netlist.
{"title":"High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC","authors":"Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, B. Gwee","doi":"10.1109/APCCAS50809.2020.9301666","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301666","url":null,"abstract":"We propose a high efficiency Early-Complete Brute Force Elimination method that speeds up the analysis flow of the Camouflage Integrated Circuit (IC). The proposed method is targeted for security qualification of the Camouflaged IC netlists in Intellectual Property (IP) protection. There are two main features in the proposed method. First, the proposed method features immediate elimination of the incorrect Camouflage gates combination for the rest of computation, concentrating the resources into other potential correct Camouflage gates combination. Second, the proposed method features early complete, i.e. revealing the correct Camouflage gates once all incorrect gates combination are eliminated, increasing the computation speed for the overall security analysis. Based on the Python programming platform, we implement the algorithm of the proposed method and test it for three circuits including ISCAS’89 benchmarks. From the simulation results, our proposed method, on average, features 71% lesser number of trials and 79% shorter run time as compared to the conventional method in revealing the correct Camouflage gates from the Camouflaged IC netlist.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116377290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301648
{"title":"[APCCAS 2020 Copyright notice]","authors":"","doi":"10.1109/apccas50809.2020.9301648","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301648","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122429376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301657
Tieu-Khanh Luong, Hong-Hanh Hoang, Hoang-Anh Nguyen-Minh, C. D. Bui, Son Bui, Trung‐Kien Nguyen
Digital Delta-Sigma Modulators (DDSMs) are widely used in integrated circuits for wireless communications, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A large bus-width is often required to have fine frequency resolution especially in 5G, which causes a high hardware complexity. A nested bus-splitting DDSM has advantages of potential speed and compact area over the conventional DDSMs, and hence reduces hardware complexity thanks to its smaller bus width. However, this architecture still suffers from spurious tones, especially in the case of constant or periodic inputs. In this work, an SP-MASH architecture has been embedded into a nested bus-splitting DDSM to overcome the spur problem. The synthesis result by Synopsys Design Compiler using TSMC 28 nm CMOS standard cell shows that the advantage of hardware cost was preserved while the spur-free performance was achieved by this hybrid scheme. Its function and effectiveness was also successfully verified with Xilinx Virtex UltraScale+ field-programmable-gate-array (FPGA).
{"title":"A Spur-Free Low-Complexity Hybrid Nested Bus-Splitting/SP-MASH Digital Delta-Sigma Modulator","authors":"Tieu-Khanh Luong, Hong-Hanh Hoang, Hoang-Anh Nguyen-Minh, C. D. Bui, Son Bui, Trung‐Kien Nguyen","doi":"10.1109/APCCAS50809.2020.9301657","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301657","url":null,"abstract":"Digital Delta-Sigma Modulators (DDSMs) are widely used in integrated circuits for wireless communications, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A large bus-width is often required to have fine frequency resolution especially in 5G, which causes a high hardware complexity. A nested bus-splitting DDSM has advantages of potential speed and compact area over the conventional DDSMs, and hence reduces hardware complexity thanks to its smaller bus width. However, this architecture still suffers from spurious tones, especially in the case of constant or periodic inputs. In this work, an SP-MASH architecture has been embedded into a nested bus-splitting DDSM to overcome the spur problem. The synthesis result by Synopsys Design Compiler using TSMC 28 nm CMOS standard cell shows that the advantage of hardware cost was preserved while the spur-free performance was achieved by this hybrid scheme. Its function and effectiveness was also successfully verified with Xilinx Virtex UltraScale+ field-programmable-gate-array (FPGA).","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301656
{"title":"APCCAS 2020 Contributor Page","authors":"","doi":"10.1109/apccas50809.2020.9301656","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301656","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121441772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301664
Vannhu Le, MinhNghia Pham, Vandang Hoang
Light-sheet fluorescence microscopy has many advantages including high-speed, noninvasive and low photobleaching and photodamage. The light-sheet thickness of light-sheet microscopy is used to determine the axial resolution. However, the light-sheet thickness is limited by the light diffraction. In order to beyond this limit, inhere, we introduce a novel way based on the use of two light-sheets to achieve the enhancement of the axial resolution of light-sheet microscopy. Two images are captured by using both Gaussian light-sheet and negative light-sheet beams. From these two images, a new relationship between them is built to achieve the axial resolution image higher than the image of Gaussian light-sheet. Experimental result is performed, indicating that the effectiveness of the proposed method is better than traditional light-sheet microscopy.
{"title":"Axial Resolution Enhacement of Light-Sheet Microscopy via two Light-Sheets","authors":"Vannhu Le, MinhNghia Pham, Vandang Hoang","doi":"10.1109/APCCAS50809.2020.9301664","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301664","url":null,"abstract":"Light-sheet fluorescence microscopy has many advantages including high-speed, noninvasive and low photobleaching and photodamage. The light-sheet thickness of light-sheet microscopy is used to determine the axial resolution. However, the light-sheet thickness is limited by the light diffraction. In order to beyond this limit, inhere, we introduce a novel way based on the use of two light-sheets to achieve the enhancement of the axial resolution of light-sheet microscopy. Two images are captured by using both Gaussian light-sheet and negative light-sheet beams. From these two images, a new relationship between them is built to achieve the axial resolution image higher than the image of Gaussian light-sheet. Experimental result is performed, indicating that the effectiveness of the proposed method is better than traditional light-sheet microscopy.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124898179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301708
Heng-Sheng Lin, Jian-Jiun Ding, Jin-Yu Huang
Saliency detection is to detect the unique region of an image that may attract human attention. It is widely used in image/video segmentation, image enhancement, and image compression. Conventionally, saliency detection problem was solved by graph-based method cooperate with low-level features and heuristic rules. Recently, the convolutional neural networks (CNNs) based methods have been thrived in computer vision area and graph convolutional networks (GCNs), which are extended from the CNN, have been used in many graph data representations and also shown promising result in node classification problem. We proposed a novel saliency detection neural network model called the Graph Saliency Network (GSN), which use the Graph Convolutional Network as main architecture and the Jumping Knowledge Network as our backbone. For the graph creation, the Region Adjacency Graph is adopted as the image-graph transformation in the proposed architecture to propagate information through edges from the spatial boundary. We also revisit several graph-based saliency detection methods for our node feature representation. The propagation model of the GSN maintain the spatial relation of the CNN with a more flexible way and has less parameters to be optimized than the CNN from the advantage of information compression in superpixel and graph. Simulations showed that, using the proposed GCN- based model together with low-level features and heuristic rules, a saliency detection result with very less mean absolute error (MAE) can be achieved.
{"title":"Graph Saliency Network: Using Graph Convolution Network on Saliency Detection","authors":"Heng-Sheng Lin, Jian-Jiun Ding, Jin-Yu Huang","doi":"10.1109/APCCAS50809.2020.9301708","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301708","url":null,"abstract":"Saliency detection is to detect the unique region of an image that may attract human attention. It is widely used in image/video segmentation, image enhancement, and image compression. Conventionally, saliency detection problem was solved by graph-based method cooperate with low-level features and heuristic rules. Recently, the convolutional neural networks (CNNs) based methods have been thrived in computer vision area and graph convolutional networks (GCNs), which are extended from the CNN, have been used in many graph data representations and also shown promising result in node classification problem. We proposed a novel saliency detection neural network model called the Graph Saliency Network (GSN), which use the Graph Convolutional Network as main architecture and the Jumping Knowledge Network as our backbone. For the graph creation, the Region Adjacency Graph is adopted as the image-graph transformation in the proposed architecture to propagate information through edges from the spatial boundary. We also revisit several graph-based saliency detection methods for our node feature representation. The propagation model of the GSN maintain the spatial relation of the CNN with a more flexible way and has less parameters to be optimized than the CNN from the advantage of information compression in superpixel and graph. Simulations showed that, using the proposed GCN- based model together with low-level features and heuristic rules, a saliency detection result with very less mean absolute error (MAE) can be achieved.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301676
Matthew Brown, C. Saavedra
A fluidically-tuned substrate integrated waveguide (SIW) quasi-elliptic bandpass filter using reconfigurable TE101 mode cavity resonators is presented. A quadruplet filter with a pair of finite transmission zeros is presented using cross-coupled cavities to achieve a highly selective passband. The four SIW cavities have vias near their corners that are selectively filled with eutectic gallium indium (EGaIn) to tune the resonant frequency of the cavities. A symmetric via placement is implemented to maintain the par of finite transmission zeros equally spaced on either side of the passband. Measured results indicate that the filter’s center frequency can be discretely tuned between 7.96 GHz, 8.12 GHz, 8.24 GHz and 8.39 GHz, indicating a 400 MHz tuning range while maintaining a symmetric and sharp roll-off. The filter was designed and fabricated on a 1.54 mm thick Rogers 4003 substrate (ϵr = 3.55, tan δ = 0.0027).
{"title":"Frequency-Tunable Quasi-Elliptic Filter Using Liquid Metal","authors":"Matthew Brown, C. Saavedra","doi":"10.1109/APCCAS50809.2020.9301676","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301676","url":null,"abstract":"A fluidically-tuned substrate integrated waveguide (SIW) quasi-elliptic bandpass filter using reconfigurable TE101 mode cavity resonators is presented. A quadruplet filter with a pair of finite transmission zeros is presented using cross-coupled cavities to achieve a highly selective passband. The four SIW cavities have vias near their corners that are selectively filled with eutectic gallium indium (EGaIn) to tune the resonant frequency of the cavities. A symmetric via placement is implemented to maintain the par of finite transmission zeros equally spaced on either side of the passband. Measured results indicate that the filter’s center frequency can be discretely tuned between 7.96 GHz, 8.12 GHz, 8.24 GHz and 8.39 GHz, indicating a 400 MHz tuning range while maintaining a symmetric and sharp roll-off. The filter was designed and fabricated on a 1.54 mm thick Rogers 4003 substrate (ϵr = 3.55, tan δ = 0.0027).","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125383328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301681
Van-Toan Nguyen, Viet-Son Bui, Trung‐Kien Nguyen
In communication transceivers utilizing I/Q direct-conversion, the mismatches in gain and phase between analog I and Q branches are inevitable, which severely causes degradation of their image rejection. A compensator of I/Q mismatches is, therefore, essential to improve the performance of these communication systems. In this paper, we present a high-performance implementation of an adaptive I/Q mismatch compensator in direct-conversion transceivers using fixed-point representation to keep low complexity. Through experiments, the observed results demonstrate that our fixed-point compensation approach delivers good correction performance. Furthermore, it consumes reasonable hardware resources, and achieve a high operating frequency. Therefore, this compensator can be deployed in low-power and high-performance communication systems efficiently.
{"title":"High-Performance Implementation of Adaptive IQ Mismatch Compensator in Direct-Conversion Transceiver","authors":"Van-Toan Nguyen, Viet-Son Bui, Trung‐Kien Nguyen","doi":"10.1109/APCCAS50809.2020.9301681","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301681","url":null,"abstract":"In communication transceivers utilizing I/Q direct-conversion, the mismatches in gain and phase between analog I and Q branches are inevitable, which severely causes degradation of their image rejection. A compensator of I/Q mismatches is, therefore, essential to improve the performance of these communication systems. In this paper, we present a high-performance implementation of an adaptive I/Q mismatch compensator in direct-conversion transceivers using fixed-point representation to keep low complexity. Through experiments, the observed results demonstrate that our fixed-point compensation approach delivers good correction performance. Furthermore, it consumes reasonable hardware resources, and achieve a high operating frequency. Therefore, this compensator can be deployed in low-power and high-performance communication systems efficiently.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127002832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301707
Lu Lu, Ju Eon Kim, Vishal Sharma, T. T. Kim
ReRAMs have been demonstrated as promising next generation non-volatile memory solutions. However, they still employ high voltage, creating CMOS reliability issues. This paper discusses ReRAM device and circuit co-design in standard CMOS technology. We investigate various ReRAM device parameters such as resistance values and set/reset voltages, and ReRAM circuit operations in advanced CMOS technology. In the studied 1T1R structure, reset operation is much more critical compared to the set operation because of the larger voltage drop across the nMOS access transistor. It also determines the lower boundary of the low resistance (LRS) value. For scalable ReRAM, it is necessary to develop ReRAM technology that can scale the set/reset voltage more than the resistance.
{"title":"ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology","authors":"Lu Lu, Ju Eon Kim, Vishal Sharma, T. T. Kim","doi":"10.1109/APCCAS50809.2020.9301707","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301707","url":null,"abstract":"ReRAMs have been demonstrated as promising next generation non-volatile memory solutions. However, they still employ high voltage, creating CMOS reliability issues. This paper discusses ReRAM device and circuit co-design in standard CMOS technology. We investigate various ReRAM device parameters such as resistance values and set/reset voltages, and ReRAM circuit operations in advanced CMOS technology. In the studied 1T1R structure, reset operation is much more critical compared to the set operation because of the larger voltage drop across the nMOS access transistor. It also determines the lower boundary of the low resistance (LRS) value. For scalable ReRAM, it is necessary to develop ReRAM technology that can scale the set/reset voltage more than the resistance.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126643916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301654
Ting-Yuan Wang, Tsung-Te Liu
This paper introduces the ECC (Elliptic Curve Cryptography) processor, in which the τ-NAF converter and Square-Square-Add Algorithm are utilized, for point multiplication on Koblitz curves. The proposed ECC processor operates over GF(2163). The τ-NAF converter can turn the complicated point double to simple point square, and the Square-Square-Add Algorithm can decrease the number of point addition. With the proposed design, the execution time for executing point multiplication will decrease by 21%, and the AT value (Area-Time product) will be lowered by 15% than the state-of-the-art design, which achieves better efficiency on the execution of ECC over Koblitz curves.
{"title":"ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm","authors":"Ting-Yuan Wang, Tsung-Te Liu","doi":"10.1109/APCCAS50809.2020.9301654","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301654","url":null,"abstract":"This paper introduces the ECC (Elliptic Curve Cryptography) processor, in which the τ-NAF converter and Square-Square-Add Algorithm are utilized, for point multiplication on Koblitz curves. The proposed ECC processor operates over GF(2163). The τ-NAF converter can turn the complicated point double to simple point square, and the Square-Square-Add Algorithm can decrease the number of point addition. With the proposed design, the execution time for executing point multiplication will decrease by 21%, and the AT value (Area-Time product) will be lowered by 15% than the state-of-the-art design, which achieves better efficiency on the execution of ECC over Koblitz curves.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125217495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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