Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301695
Sarmad Ozan, Manish Nair, Tommaso A. Cappello, M. Beach
This paper proposes a wideband linearisation technique for third-order intercept point (IP3) improvement in low noise amplifiers (LNAs). The proposed LNA is designed for mid-band 5G (3-4GHz) wireless receivers and it is based on a cascode topology. An auxiliary transistor provides a feedforward correction path for third-order intermodulation (IM3) cancellation. The effects of the second harmonic on the IM3 are also considered in the modelling. Theoretical and simulation analysis of the circuit result in a DC power consumption of 306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise figure (NF) of 0.94dB and 13.8dB of power gain are obtained. The LNA is simulated for a hybrid circuit implementation using a 400um GaAs packaged transistor.
{"title":"Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers","authors":"Sarmad Ozan, Manish Nair, Tommaso A. Cappello, M. Beach","doi":"10.1109/APCCAS50809.2020.9301695","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301695","url":null,"abstract":"This paper proposes a wideband linearisation technique for third-order intercept point (IP3) improvement in low noise amplifiers (LNAs). The proposed LNA is designed for mid-band 5G (3-4GHz) wireless receivers and it is based on a cascode topology. An auxiliary transistor provides a feedforward correction path for third-order intermodulation (IM3) cancellation. The effects of the second harmonic on the IM3 are also considered in the modelling. Theoretical and simulation analysis of the circuit result in a DC power consumption of 306mW from a supply voltage of 3V, an OIP3 of 30.8dBm, noise figure (NF) of 0.94dB and 13.8dB of power gain are obtained. The LNA is simulated for a hybrid circuit implementation using a 400um GaAs packaged transistor.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131680147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301696
Jiayu Wen, Yufei Ma, Zhongfeng Wang
Pruning techniques can compress the CNN models by making the insignificant weights to be zeros to release the tremendous workload in large-scale CNNs. However, for hardware architecture, to efficiently load and operate on the nonzero data with high parallelism is a great challenge due to the random location of pruned weights. To address this issue, a sparsity aware CNN accelerator is proposed in this work to process the irregularly pruned CNN models. A candidate pool architecture is designed to only pick the randomly needed activations chosen by nonzero weights. It is set as a three-dimensional structure to relieve the problem of workload imbalance caused by random nonzero weight locations and high parallelism. Besides, a dedicated indexing method is designed to cooperate with the candidate pool architecture to accomplish the whole sparse dataflow. The proposed sparsity aware CNN accelerator is demonstrated on Intel Arria 10 FPGA for multiple popular CNN models that achieves up to 89.7% throughput improvement compared to the baseline design.
{"title":"An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference","authors":"Jiayu Wen, Yufei Ma, Zhongfeng Wang","doi":"10.1109/APCCAS50809.2020.9301696","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301696","url":null,"abstract":"Pruning techniques can compress the CNN models by making the insignificant weights to be zeros to release the tremendous workload in large-scale CNNs. However, for hardware architecture, to efficiently load and operate on the nonzero data with high parallelism is a great challenge due to the random location of pruned weights. To address this issue, a sparsity aware CNN accelerator is proposed in this work to process the irregularly pruned CNN models. A candidate pool architecture is designed to only pick the randomly needed activations chosen by nonzero weights. It is set as a three-dimensional structure to relieve the problem of workload imbalance caused by random nonzero weight locations and high parallelism. Besides, a dedicated indexing method is designed to cooperate with the candidate pool architecture to accomplish the whole sparse dataflow. The proposed sparsity aware CNN accelerator is demonstrated on Intel Arria 10 FPGA for multiple popular CNN models that achieves up to 89.7% throughput improvement compared to the baseline design.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123346548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301711
Kentaro Nagai, Jun Shiomi, H. Onodera
This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently so that the BBG can minimize total energy consumption under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which results in low energy consumption and small area. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor implemented on the same chip show that the proposed BBG can reduce energy consumption close to a minimum where the amount of excess energy is 3%. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.
{"title":"A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias","authors":"Kentaro Nagai, Jun Shiomi, H. Onodera","doi":"10.1109/APCCAS50809.2020.9301711","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301711","url":null,"abstract":"This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently so that the BBG can minimize total energy consumption under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which results in low energy consumption and small area. A test circuit is implemented in a 65-nm FDSOI process. Measurement results using a 32-bit RISC processor implemented on the same chip show that the proposed BBG can reduce energy consumption close to a minimum where the amount of excess energy is 3%. In this condition, energy and area overheads of the BBG are 0.2% and 0.12%, respectively.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126437344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301670
Wenbin He, Ziwei Li, Fan Ye, Junyan Ren
This paper introduces a low power reference voltage buffer(RVB) and a MIM-MOM combinational unit capacitor for high speed ADC. The proposed RVB adopts flipped voltage follower(FVF) technique achieving lower output impedance to reduce power consumption and a normal supply voltage can be used. The unit capacitor is a full surrounded structure, in which the top plate is enwrapped by the bottom plate to reduce the parasite capacitance on it. High density and good matching can be achieved. The concept is applied to a 12b 200MS/s SAR ADC with recombination redundancy scheme in 28 nm CMOS. The ADC and RVB consume 1.88mW and 2.4mW, respectively. The simulation shows that the SNDR and SFDR are 64.79dB and 76.71dB with a 95.3MHz input.
介绍了一种用于高速ADC的低功率参考电压缓冲器(RVB)和一种mimm - mom组合单元电容器。该RVB采用了翻转电压从动器(FVF)技术，实现了较低的输出阻抗，降低了功耗，并且可以使用正常的电源电压。单位电容器为全包围式结构，其顶板被底板包裹，以减少其上的寄生电容。可以实现高密度和良好的匹配。该概念应用于28纳米CMOS中具有重组冗余方案的12b 200MS/s SAR ADC。ADC和RVB的功耗分别为1.88mW和2.4mW。仿真结果表明，在95.3MHz输入时，SNDR和SFDR分别为64.79dB和76.71dB。
{"title":"A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC","authors":"Wenbin He, Ziwei Li, Fan Ye, Junyan Ren","doi":"10.1109/APCCAS50809.2020.9301670","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301670","url":null,"abstract":"This paper introduces a low power reference voltage buffer(RVB) and a MIM-MOM combinational unit capacitor for high speed ADC. The proposed RVB adopts flipped voltage follower(FVF) technique achieving lower output impedance to reduce power consumption and a normal supply voltage can be used. The unit capacitor is a full surrounded structure, in which the top plate is enwrapped by the bottom plate to reduce the parasite capacitance on it. High density and good matching can be achieved. The concept is applied to a 12b 200MS/s SAR ADC with recombination redundancy scheme in 28 nm CMOS. The ADC and RVB consume 1.88mW and 2.4mW, respectively. The simulation shows that the SNDR and SFDR are 64.79dB and 76.71dB with a 95.3MHz input.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, the verifiable delay function (VDF) is widely regarded as the core function for the next-generation blockchain system because it is slow to evaluate but easy to verify. In general, the squaring operation takes a significant proportion of VDF computation. Moreover, the squaring over a class group, including large-number extended greatest common divisor (GCD) computations, divisions, and multiplications, is extremely hard to be accelerated in hardware. In this paper, for the first time, we propose an efficient architecture for squaring by utilizing many algorithmic transformations and architectural optimizations to reduce the critical path and calculation cycles. Firstly, the squaring algorithm is modified to achieve partial parallel computing, and a very hardware-efficient extended GCD algorithm is selected to reduce the whole computation cycles. Secondly, highly-parallelized architectures for large-number division and multiplication are devised respectively. Finally, the proposed architecture is coded using hardware description language (HDL) and synthesized under the TSMC 28-nm CMOS technology. The synthesis results show that the proposed design with the input width of 2048 bits averagely takes 6.319us per squaring at a frequency of 500 MHz. Compared to the original squaring with the same setting running over an Intel(R) Core(TM) i7-6850K 3.60GHz CPU, our design achieves about 2x speedup.
{"title":"An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group","authors":"Danyang Zhu, Yifeng Song, Jing Tian, Zhongfeng Wang, Haobo Yu","doi":"10.1109/APCCAS50809.2020.9301680","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301680","url":null,"abstract":"Nowadays, the verifiable delay function (VDF) is widely regarded as the core function for the next-generation blockchain system because it is slow to evaluate but easy to verify. In general, the squaring operation takes a significant proportion of VDF computation. Moreover, the squaring over a class group, including large-number extended greatest common divisor (GCD) computations, divisions, and multiplications, is extremely hard to be accelerated in hardware. In this paper, for the first time, we propose an efficient architecture for squaring by utilizing many algorithmic transformations and architectural optimizations to reduce the critical path and calculation cycles. Firstly, the squaring algorithm is modified to achieve partial parallel computing, and a very hardware-efficient extended GCD algorithm is selected to reduce the whole computation cycles. Secondly, highly-parallelized architectures for large-number division and multiplication are devised respectively. Finally, the proposed architecture is coded using hardware description language (HDL) and synthesized under the TSMC 28-nm CMOS technology. The synthesis results show that the proposed design with the input width of 2048 bits averagely takes 6.319us per squaring at a frequency of 500 MHz. Compared to the original squaring with the same setting running over an Intel(R) Core(TM) i7-6850K 3.60GHz CPU, our design achieves about 2x speedup.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301690
Zaiyong Liu, Haiyuan Chen, Tianshu Hou
Electromigration-induced reliability (EM) is the major concern for design of modern power grids, characterized by high current densities and long metal lines. Due to their high inaccuracy of handling structures with large scale and complexity, traditional empirical EM prediction methods are not applicable for modern power grids. In this paper, we propose a novel analytical model of hydrostatic stress evolution during the void growth phase for general multi-segment wires, common interconnect structures in power grids, based on the adoption of Laplace transformation on Korhonen’s equation with coupled boundary conditions (BCs). The analytical solution is expressed with a set of auxiliary basis functions using the complementary error function. With analysis of the analytical expression form, the compact model is presented for practical EM analysis. Compared with the finite element analysis (FEA) results, our compact model can lead to less than 0.50% error on average for multi-segment wires extracted from IBM power grid benchmarks.
{"title":"Stress Evolution Analysis of EM-Induced Void Growth for Multi-Segment Interconnect Wires","authors":"Zaiyong Liu, Haiyuan Chen, Tianshu Hou","doi":"10.1109/APCCAS50809.2020.9301690","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301690","url":null,"abstract":"Electromigration-induced reliability (EM) is the major concern for design of modern power grids, characterized by high current densities and long metal lines. Due to their high inaccuracy of handling structures with large scale and complexity, traditional empirical EM prediction methods are not applicable for modern power grids. In this paper, we propose a novel analytical model of hydrostatic stress evolution during the void growth phase for general multi-segment wires, common interconnect structures in power grids, based on the adoption of Laplace transformation on Korhonen’s equation with coupled boundary conditions (BCs). The analytical solution is expressed with a set of auxiliary basis functions using the complementary error function. With analysis of the analytical expression form, the compact model is presented for practical EM analysis. Compared with the finite element analysis (FEA) results, our compact model can lead to less than 0.50% error on average for multi-segment wires extracted from IBM power grid benchmarks.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133204256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301682
Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren
This paper proposes a calibration scheme that compensates the nonlinearity of the SAR-Pipelined analog-to-digital converters(ADCs) based on a shared neural network. Due to the fitting ability of the nonlinear functions, the neural network based ADC calibration scheme requires no prior knowledge. Moreover, the introduction of the sharing mechanism not only guarantees the calibration effect for nonlinearity, but also simplifies the hardware complexity, compared to a calibrator with independent neural networks. We validate the scheme with a 14-bit 60MHz SAR-Pipelined ADC fabricated in 28 nm. The measurement results indicate that the ADCs achieve an SFDR of 93.3 dB and an ENOB of 10.63 b, with the assistance of the proposed calibrator. In the meantime, the memory is reduced by 46.7% due to the decrease of neural network parameters, with a sharing rate (ratio of shared quantity to total) of 93.75%.
{"title":"A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network","authors":"Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren","doi":"10.1109/APCCAS50809.2020.9301682","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301682","url":null,"abstract":"This paper proposes a calibration scheme that compensates the nonlinearity of the SAR-Pipelined analog-to-digital converters(ADCs) based on a shared neural network. Due to the fitting ability of the nonlinear functions, the neural network based ADC calibration scheme requires no prior knowledge. Moreover, the introduction of the sharing mechanism not only guarantees the calibration effect for nonlinearity, but also simplifies the hardware complexity, compared to a calibrator with independent neural networks. We validate the scheme with a 14-bit 60MHz SAR-Pipelined ADC fabricated in 28 nm. The measurement results indicate that the ADCs achieve an SFDR of 93.3 dB and an ENOB of 10.63 b, with the assistance of the proposed calibrator. In the meantime, the memory is reduced by 46.7% due to the decrease of neural network parameters, with a sharing rate (ratio of shared quantity to total) of 93.75%.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131790711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/apccas50809.2020.9301645
{"title":"[APCCAS 2020 Title page]","authors":"","doi":"10.1109/apccas50809.2020.9301645","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301645","url":null,"abstract":"","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132002765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-08DOI: 10.1109/APCCAS50809.2020.9301702
Ji-Ting Wu, Jian-Jiun Ding
Binary image is useful in our life. For instance, text, line art, halftone image, tax etc. could use this method, so lossless binary image compression is useful for improve this domain. We found that angle freeman chain code for eight connectivity (AF8) is effective in lossless binary image compression. Therefore, we use improved-adaptive-arithmetic-coding to encode character of AF8, and we also decrease character with global and local frequency table thanks to some characteristics of AF8 we found. Then, in experimental result, we show our proposed method is better than AF8 with static arithmetic coding (SAC), and we also show that the context modeling method we choose is better than the compression coding without context modeling. Furthermore, our method is also better than other method like the ZD code and the AAF8 code.
{"title":"Improved Angle Freeman Chain Code Using Improved Adaptive Arithmetic Coding","authors":"Ji-Ting Wu, Jian-Jiun Ding","doi":"10.1109/APCCAS50809.2020.9301702","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301702","url":null,"abstract":"Binary image is useful in our life. For instance, text, line art, halftone image, tax etc. could use this method, so lossless binary image compression is useful for improve this domain. We found that angle freeman chain code for eight connectivity (AF8) is effective in lossless binary image compression. Therefore, we use improved-adaptive-arithmetic-coding to encode character of AF8, and we also decrease character with global and local frequency table thanks to some characteristics of AF8 we found. Then, in experimental result, we show our proposed method is better than AF8 with static arithmetic coding (SAC), and we also show that the context modeling method we choose is better than the compression coding without context modeling. Furthermore, our method is also better than other method like the ZD code and the AAF8 code.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134067640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Near-threshold voltage (NTV) operation has potential to substantially improve the energy efficiency of digital integrated circuits (ICs). However, it also introduces excessive conservative timing margins. The timing resilient circuit was proved to be a promising solution to mitigate excessive timing margins. To realize more energy-efficient IC systems, the timing resilient circuits should be designed to be miniaturized and operate in wide-voltage-range (down to NTV).This paper develops a lightweight timing resilient scheme to enable the near-threshold efficient ICs. The proposed scheme based on our node transition signal detector (NTSD) design with merely 9 extra transistors. Combined with the data strobe Flip-Flops, the circuits are inserted into monitored points of the target ICs. To further reduce the overhead, we develop the mean-time-to-failure aware hybrid selection algorithm. Simulation results demonstrate that the proposed scheme enable the 40-nm CNN accelerator to work robustly at 0.38-1.1V with only 3.5% extra area overhead. Moreover, this scheme reduce area overhead by 54.68% and improve energy efficiency by 53.69% at 0.6V, compared with the presented Razor scheme. The advantage of our proposed method lies in that it consumes less extra overhead and can work stably in a wider voltage range.
{"title":"A Light-Weight Timing Resilient Scheme for Near-Threshold Efficient Digital ICs","authors":"Xuemei Fan, Hongwei Li, Qiang Li, Rujin Wang, Hao Liu, Shengli Lu","doi":"10.1109/APCCAS50809.2020.9301717","DOIUrl":"https://doi.org/10.1109/APCCAS50809.2020.9301717","url":null,"abstract":"Near-threshold voltage (NTV) operation has potential to substantially improve the energy efficiency of digital integrated circuits (ICs). However, it also introduces excessive conservative timing margins. The timing resilient circuit was proved to be a promising solution to mitigate excessive timing margins. To realize more energy-efficient IC systems, the timing resilient circuits should be designed to be miniaturized and operate in wide-voltage-range (down to NTV).This paper develops a lightweight timing resilient scheme to enable the near-threshold efficient ICs. The proposed scheme based on our node transition signal detector (NTSD) design with merely 9 extra transistors. Combined with the data strobe Flip-Flops, the circuits are inserted into monitored points of the target ICs. To further reduce the overhead, we develop the mean-time-to-failure aware hybrid selection algorithm. Simulation results demonstrate that the proposed scheme enable the 40-nm CNN accelerator to work robustly at 0.38-1.1V with only 3.5% extra area overhead. Moreover, this scheme reduce area overhead by 54.68% and improve energy efficiency by 53.69% at 0.6V, compared with the presented Razor scheme. The advantage of our proposed method lies in that it consumes less extra overhead and can work stably in a wider voltage range.","PeriodicalId":127075,"journal":{"name":"2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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