Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920518
D. Priore
It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical "RC" time constants in this environment dwarf the "time of flight" of light across the distances involved. However, with the advent of large chips running at upwards of 100MHz, this assumption is called into question. Furthermore, due to the lossy nature of the silicon environment, the "time of flight" in question does not follow simply from the delay rate of light in silicon dioxide (i.e. 66ps/cm). In general, it is greater. This paper attempts to frame the problem and suggest design principles to deal with it. These principles have been used extensively in the design of a 200MHz 64-bit dual-issue CMOS microprocessor.
{"title":"Inductance on silicon for sub-micron CMOS VLSI","authors":"D. Priore","doi":"10.1109/VLSIC.1993.920518","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920518","url":null,"abstract":"It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical \"RC\" time constants in this environment dwarf the \"time of flight\" of light across the distances involved. However, with the advent of large chips running at upwards of 100MHz, this assumption is called into question. Furthermore, due to the lossy nature of the silicon environment, the \"time of flight\" in question does not follow simply from the delay rate of light in silicon dioxide (i.e. 66ps/cm). In general, it is greater. This paper attempts to frame the problem and suggest design principles to deal with it. These principles have been used extensively in the design of a 200MHz 64-bit dual-issue CMOS microprocessor.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920566
J.Y.-C. Chang, A. Abidi
Low-power RF and IF components are essential building blocks for future portable wireless communicators. The conventional view holds that only GaAs or silicon bipolar technologies offer the required gain and low noise at an acceptably low power dissipation in an RF amplifier operating in the 900 MHz frequency band. A wireless transceiver will therefore consist of a mixture of technologies for RF, IF, and baseband signal processing. However, if the entire transceiver is integrated in a single technology, just the elimination of off-chip buffers between the RF and IF sections, say, can lead to considerable power savings. CMOS is the only viable technology for a digital transceiver. To this end, we describe here a 2-/spl mu/m CMOS tuned amplifier affording 14 dB gain centered at 750 MHz, 6 dB noise figure, and 7 mW power dissipation from a 3 V supply. The design of this prototype will be straightforwardly re-centered at 900 MHz in a future version.
{"title":"A 750 MHz RF amplifier in 2-/spl mu/m CMOS","authors":"J.Y.-C. Chang, A. Abidi","doi":"10.1109/VLSIC.1993.920566","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920566","url":null,"abstract":"Low-power RF and IF components are essential building blocks for future portable wireless communicators. The conventional view holds that only GaAs or silicon bipolar technologies offer the required gain and low noise at an acceptably low power dissipation in an RF amplifier operating in the 900 MHz frequency band. A wireless transceiver will therefore consist of a mixture of technologies for RF, IF, and baseband signal processing. However, if the entire transceiver is integrated in a single technology, just the elimination of off-chip buffers between the RF and IF sections, say, can lead to considerable power savings. CMOS is the only viable technology for a digital transceiver. To this end, we describe here a 2-/spl mu/m CMOS tuned amplifier affording 14 dB gain centered at 750 MHz, 6 dB noise figure, and 7 mW power dissipation from a 3 V supply. The design of this prototype will be straightforwardly re-centered at 900 MHz in a future version.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115663855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920550
H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, K. Miyazawa
A new reference voltage generator featuring the dynamic operation of a threshold voltage difference (/spl Delta/V/sub T/) generator and voltage-up converter with current mirror circuits has been proposed. This generator efficiently reduces average current to less than 1 /spl mu/A, while maintaining high-accuracy and high-stability. These performances are enough for realizing high-density battery operated DRAMs with a low active and data-retention current comparable to SRAMs.
{"title":"Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMs","authors":"H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, K. Miyazawa","doi":"10.1109/VLSIC.1993.920550","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920550","url":null,"abstract":"A new reference voltage generator featuring the dynamic operation of a threshold voltage difference (/spl Delta/V/sub T/) generator and voltage-up converter with current mirror circuits has been proposed. This generator efficiently reduces average current to less than 1 /spl mu/A, while maintaining high-accuracy and high-stability. These performances are enough for realizing high-density battery operated DRAMs with a low active and data-retention current comparable to SRAMs.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121347685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920555
T. Sakurai, A. El Gamal
Summary form only given. Discusses the ASIC technology, deployment, and applications for its use.
只提供摘要形式。讨论了ASIC技术、部署及其应用。
{"title":"Multi-million gate ASIC's","authors":"T. Sakurai, A. El Gamal","doi":"10.1109/VLSIC.1993.920555","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920555","url":null,"abstract":"Summary form only given. Discusses the ASIC technology, deployment, and applications for its use.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115860013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920513
K. Kinoshita
In this paper we applied the method known as checking experiments to generate test sequences for sequential circuits under the stuck-at fault model. To design a sequential circuit having a distinguishing sequence is a key in this method. As modification techniques of sequential circuits, two testable design techniques have been considered. One is a testable design technique at the state transition level and the other is at the gate level. We have also shown that it is possible to shorten the test sequence by using a fault simulator. Experimental results show that fault coverages for all stuck-at faults have reached 100% for the circuits under designed for testability both at the state transition level and at the gate level. As a result, it has been shown that the distinguishing sequence is very useful for test generation of sequential circuits.
{"title":"Design for testability of sequential circuits","authors":"K. Kinoshita","doi":"10.1109/VLSIC.1993.920513","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920513","url":null,"abstract":"In this paper we applied the method known as checking experiments to generate test sequences for sequential circuits under the stuck-at fault model. To design a sequential circuit having a distinguishing sequence is a key in this method. As modification techniques of sequential circuits, two testable design techniques have been considered. One is a testable design technique at the state transition level and the other is at the gate level. We have also shown that it is possible to shorten the test sequence by using a fault simulator. Experimental results show that fault coverages for all stuck-at faults have reached 100% for the circuits under designed for testability both at the state transition level and at the gate level. As a result, it has been shown that the distinguishing sequence is very useful for test generation of sequential circuits.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127889771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920539
Y. Choi, M. Kim, Tae-Jin Kim, Seung-hoon Lee, Ho-Cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Beornje Lee, Sooin Cho, E. Haq, J. Karp, D. Chin
The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.
{"title":"16 Mbit synchronous DRAM with 125 Mbyte/sec data rate","authors":"Y. Choi, M. Kim, Tae-Jin Kim, Seung-hoon Lee, Ho-Cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Beornje Lee, Sooin Cho, E. Haq, J. Karp, D. Chin","doi":"10.1109/VLSIC.1993.920539","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920539","url":null,"abstract":"The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127901310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920562
K. Ishibashi, K. Komiyaji, S. Morita, Toshiro Aoto, S. Ikeda, K. Asayama, Atsuyosi Koike, T. Yamanaka, N. Hashimoto, Haruhito Iida, F. Kojima, Koichi Motohashi, K. Sasaki
A high-speed circuit, a high-yield redundancy technique, and a soft-error immune cell are essential to realize ultra high density static RAMs. A 16 Mb (4Mx4/2Mx8) CMOS SRAM fabricated using 0.4 /spl mu/m CMOS technology is reported. An address access time of 12.5 ns is attained with 3.3 V supply voltage by using a common-centroid-geometry (CCG) layout sense amplifier and divided data bus architecture. A flexible redundancy technique (FRT) with high efficiency and with no access penalty has been incorporated into the 16 Mb SRAM. A 7.16 /spl mu/m/sup 2/ TFT load cell with stacked capacitors, achieves soft-error immunity even for the supply voltage of 3.3 V.
{"title":"A 12.5 ns 16 Mb CMOS SRAM","authors":"K. Ishibashi, K. Komiyaji, S. Morita, Toshiro Aoto, S. Ikeda, K. Asayama, Atsuyosi Koike, T. Yamanaka, N. Hashimoto, Haruhito Iida, F. Kojima, Koichi Motohashi, K. Sasaki","doi":"10.1109/VLSIC.1993.920562","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920562","url":null,"abstract":"A high-speed circuit, a high-yield redundancy technique, and a soft-error immune cell are essential to realize ultra high density static RAMs. A 16 Mb (4Mx4/2Mx8) CMOS SRAM fabricated using 0.4 /spl mu/m CMOS technology is reported. An address access time of 12.5 ns is attained with 3.3 V supply voltage by using a common-centroid-geometry (CCG) layout sense amplifier and divided data bus architecture. A flexible redundancy technique (FRT) with high efficiency and with no access penalty has been incorporated into the 16 Mb SRAM. A 7.16 /spl mu/m/sup 2/ TFT load cell with stacked capacitors, achieves soft-error immunity even for the supply voltage of 3.3 V.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115201549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920515
F. Arakawa, K. Uchiyama, H. Aoki, S. Narita, S. Matsui, M. Yamamoto, I. Kawasaki, N. Nakagawa, I. Kudoh, K. Hirose, H. Abe, K. Takagi, K. Hashimoto, K. Takakubo, Y. Miyairi, H. Kudoh, M. Furuyama, K. Hasegawa, M. Hamahara, K. C. Chen
Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A 64-entry branch-always target buffer (BTB) enables O-cycle branching. An 8-entry return buffer (RB) reduces execution cycles of returns from a subroutine. The processor incorporates 8-kB instruction and operand physical caches (IC and OC), 64-entry instruction and operand translation look-aside buffers (ITLB and OTLB), and a 4-entry store buffer (SB). We focus on two problems particular to adopting a superscalar architecture with a variable-length CISC instruction set. These are: 1) how to dispatch two variable-length instructions per cycle; 2) how to implement complicated operation instructions.
{"title":"A CMOS 50 MHz CISC superscalar microprocessor","authors":"F. Arakawa, K. Uchiyama, H. Aoki, S. Narita, S. Matsui, M. Yamamoto, I. Kawasaki, N. Nakagawa, I. Kudoh, K. Hirose, H. Abe, K. Takagi, K. Hashimoto, K. Takakubo, Y. Miyairi, H. Kudoh, M. Furuyama, K. Hasegawa, M. Hamahara, K. C. Chen","doi":"10.1109/VLSIC.1993.920515","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920515","url":null,"abstract":"Describes a CISC superscalar microprocessor. It executes 126 instructions with 14 addressing modes, which include floating-point processing fully compatible with the ANSI/IEEE 754-1985 standard. A 64-entry branch-always target buffer (BTB) enables O-cycle branching. An 8-entry return buffer (RB) reduces execution cycles of returns from a subroutine. The processor incorporates 8-kB instruction and operand physical caches (IC and OC), 64-entry instruction and operand translation look-aside buffers (ITLB and OTLB), and a 4-entry store buffer (SB). We focus on two problems particular to adopting a superscalar architecture with a variable-length CISC instruction set. These are: 1) how to dispatch two variable-length instructions per cycle; 2) how to implement complicated operation instructions.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121909395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/VLSIC.1993.920519
T. Knight, H. M. Wu
We have presented a novel technique that allows skew-free distribution of digital signals with known and controllable arrival times. The technique requires adjustments and measurements only at the sender. Our method is based on measuring the round trip delay of a signal and then adjusting it with a pair of matched delay lines. This technique can be modified to work without extra wiring, and is effective for receivers along as well as at the end of a wire. This method can be readily implemented using well-known circuit forms in ECL and CMOS technologies, and incorporates well into the boundary scan logic of a custom VLSI chip.
{"title":"A method for skew-free distribution of digital signals using matched variable delay lines","authors":"T. Knight, H. M. Wu","doi":"10.1109/VLSIC.1993.920519","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920519","url":null,"abstract":"We have presented a novel technique that allows skew-free distribution of digital signals with known and controllable arrival times. The technique requires adjustments and measurements only at the sender. Our method is based on measuring the round trip delay of a signal and then adjusting it with a pair of matched delay lines. This technique can be modified to work without extra wiring, and is effective for receivers along as well as at the end of a wire. This method can be readily implemented using well-known circuit forms in ECL and CMOS technologies, and incorporates well into the boundary scan logic of a custom VLSI chip.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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