Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920551
D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi
A new open/folded bit-line (BL) arrangement for ultra high-density DRAMs is proposed. The proposed arrangement was successfully verified by the test chip. This arrangement features a 6F/sup 2/ memory cell and relaxed sensing amplifier of 3 times the pitch of BL. The chip size with this arrangement can be reduced to 81.6% of that of the folded BL arrangement, without introducing the complicated memory cell structure and without sacrificing access speed and power dissipation. Moreover, the proposed arrangement has good array noise immunity in scaled DRAMs compared with the folded BL arrangement. This arrangement is one of the leading candidates for ultra high-density DRAMs.
{"title":"Open/folded bit-line arrangement for ultra high-density DRAMs","authors":"D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi","doi":"10.1109/VLSIC.1993.920551","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920551","url":null,"abstract":"A new open/folded bit-line (BL) arrangement for ultra high-density DRAMs is proposed. The proposed arrangement was successfully verified by the test chip. This arrangement features a 6F/sup 2/ memory cell and relaxed sensing amplifier of 3 times the pitch of BL. The chip size with this arrangement can be reduced to 81.6% of that of the folded BL arrangement, without introducing the complicated memory cell structure and without sacrificing access speed and power dissipation. Moreover, the proposed arrangement has good array noise immunity in scaled DRAMs compared with the folded BL arrangement. This arrangement is one of the leading candidates for ultra high-density DRAMs.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114040046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920544
H. Shirahama, K. Taniguchi, K. Nakashi
PLLs (phase locked loops) are expected to be desirable components for clock extraction in high speed digital communication systems, typically in optical systems, because of the low cost, compactness, suitability to integration, and ease of treatment. The PLL for clock extraction requires a fast pull-in and small output jitter characteristics. In this paper, we describe a total PLL system, in which a further improvement of the pull-in time is realized and a pseudo lock (i.e. harmonic lock), which has been a serious problem in the past, can be avoided automatically. We have constructed the PLL system using a monolithic PU-IC for the PLL core part and 1.2 micron design rule PLAs for most of the remaining part of the system, and measured total performances of the system.
{"title":"A new very fast pull-in PLL system with anti-pseudo-lock function","authors":"H. Shirahama, K. Taniguchi, K. Nakashi","doi":"10.1109/VLSIC.1993.920544","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920544","url":null,"abstract":"PLLs (phase locked loops) are expected to be desirable components for clock extraction in high speed digital communication systems, typically in optical systems, because of the low cost, compactness, suitability to integration, and ease of treatment. The PLL for clock extraction requires a fast pull-in and small output jitter characteristics. In this paper, we describe a total PLL system, in which a further improvement of the pull-in time is realized and a pseudo lock (i.e. harmonic lock), which has been a serious problem in the past, can be avoided automatically. We have constructed the PLL system using a monolithic PU-IC for the PLL core part and 1.2 micron design rule PLAs for most of the remaining part of the system, and measured total performances of the system.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114426067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920542
S. Bang, Joongho Choi, B. Sheu
Wireless communication is of crucial importance in the information era, especially with the rapid trends toward digital communication industries. Furthermore, the growing demand for physical mobility and service portability is one of the driving market forces for personal communication systems. A 3V data transceiver chip is described for both the conventional analog and dual-mode analog/digital cellular mobile telephone systems. With enhanced data reception capability, it features a low operating voltage, low power consumption and is suitable for battery-operated, hand-held operation. Our development of the data transceiver chip adopts the mixed analog/digital approach to greatly simplify the integration of the mobile phone set.
{"title":"A 3 V data transceiver chip for dual-mode cellular communication systems","authors":"S. Bang, Joongho Choi, B. Sheu","doi":"10.1109/VLSIC.1993.920542","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920542","url":null,"abstract":"Wireless communication is of crucial importance in the information era, especially with the rapid trends toward digital communication industries. Furthermore, the growing demand for physical mobility and service portability is one of the driving market forces for personal communication systems. A 3V data transceiver chip is described for both the conventional analog and dual-mode analog/digital cellular mobile telephone systems. With enhanced data reception capability, it features a low operating voltage, low power consumption and is suitable for battery-operated, hand-held operation. Our development of the data transceiver chip adopts the mixed analog/digital approach to greatly simplify the integration of the mobile phone set.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115127861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920535
P. Bosshart
There will always be chips designed with the highly manual approaches required to extract the utmost in performance. However, unless the market for a chip is well into the hundreds of millions of dollars, this approach may not be economically justified. A better approach for the vast majority of chip designs is to start with a methodology with proven high productivity, and carefully examine extensions to that methodology which can be added in order to meet performance, area or power objectives. If new capabilities are added in a way which does not break major design tools, technology utilization can be brought from what ASICs achieve to near that of the leading edge full-custom designs, while at the same time having a controlled impact on design productivity. On the other hand, if the approach starts with highly optimized manual circuits and a lack of discipline with respect to tool compatibility, poor productivity is certain to result.
{"title":"The myth of the pushbutton chip","authors":"P. Bosshart","doi":"10.1109/VLSIC.1993.920535","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920535","url":null,"abstract":"There will always be chips designed with the highly manual approaches required to extract the utmost in performance. However, unless the market for a chip is well into the hundreds of millions of dollars, this approach may not be economically justified. A better approach for the vast majority of chip designs is to start with a methodology with proven high productivity, and carefully examine extensions to that methodology which can be added in order to meet performance, area or power objectives. If new capabilities are added in a way which does not break major design tools, technology utilization can be brought from what ASICs achieve to near that of the leading edge full-custom designs, while at the same time having a controlled impact on design productivity. On the other hand, if the approach starts with highly optimized manual circuits and a lack of discipline with respect to tool compatibility, poor productivity is certain to result.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129558833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920534
A. Matsuzawa
Portable equipment such as compact disc players, camcorders, and cellular phones employ both analog and digital LSIs. In the future, portable equipment will use more complicated processing, such as audio/video compression and decompression technologies which need many more logic gates. But the use of analog circuits will continue in future portable equipment, even if such complicated digital processing is used. Hence, attention must be paid to the low voltage and low power design of mixed analog/digital circuits for portable equipment. Therefore, the author presents some viewpoints on the design of low voltage and low power digital and analog circuits with a focus on analog circuits technology rather than digital.
{"title":"Low voltage mixed analog/digital circuit design for portable equipment","authors":"A. Matsuzawa","doi":"10.1109/VLSIC.1993.920534","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920534","url":null,"abstract":"Portable equipment such as compact disc players, camcorders, and cellular phones employ both analog and digital LSIs. In the future, portable equipment will use more complicated processing, such as audio/video compression and decompression technologies which need many more logic gates. But the use of analog circuits will continue in future portable equipment, even if such complicated digital processing is used. Hence, attention must be paid to the low voltage and low power design of mixed analog/digital circuits for portable equipment. Therefore, the author presents some viewpoints on the design of low voltage and low power digital and analog circuits with a focus on analog circuits technology rather than digital.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115297944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920537
A. Yamazaki, K. Dosaka, T. Ogawa, M. Kuroiwa, H. Fukuda, G. Johnson, M. Kumanoya
This paper describes a concurrent operating cache DRAM (CDRAM) for low cost multi-media systems, in which the program and graphic data coexist in the main memory. The concurrent operation of the DRAM and SRAM completely removes the idle cycles. As a result, the average access time is equal to the SRAM access time of 6.5 ns with 0.6 /spl mu/m CMOS process. The flash write and direct read/write are also useful for the multi-media systems.
{"title":"A concurrent operating CDRAM for low cost multi-media","authors":"A. Yamazaki, K. Dosaka, T. Ogawa, M. Kuroiwa, H. Fukuda, G. Johnson, M. Kumanoya","doi":"10.1109/VLSIC.1993.920537","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920537","url":null,"abstract":"This paper describes a concurrent operating cache DRAM (CDRAM) for low cost multi-media systems, in which the program and graphic data coexist in the main memory. The concurrent operation of the DRAM and SRAM completely removes the idle cycles. As a result, the average access time is equal to the SRAM access time of 6.5 ns with 0.6 /spl mu/m CMOS process. The flash write and direct read/write are also useful for the multi-media systems.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122540718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920545
T. Takashi, S. Miyazawa, K. Iwabuchi, Y. Shimura, H. Miyasaka
Timing recovery circuits in magnetic recording systems have to have high bit rate and fast acquisition cycles, so they are usually equipped with an analog phase-locked loop (PLL). We propose a new method of digital timing recovery circuit that is different from the conventional digital PLL and that can be operated under a faster acquisition and wider capture range. This report describes the new digital timing recovery circuit architecture for magnetic recording that uses feedback delay compensators for fast acquisition and wide capture range on CMOS LSI circuit.
{"title":"Digital timing recovery circuit with feedback delay compensators for magnetic recording systems","authors":"T. Takashi, S. Miyazawa, K. Iwabuchi, Y. Shimura, H. Miyasaka","doi":"10.1109/VLSIC.1993.920545","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920545","url":null,"abstract":"Timing recovery circuits in magnetic recording systems have to have high bit rate and fast acquisition cycles, so they are usually equipped with an analog phase-locked loop (PLL). We propose a new method of digital timing recovery circuit that is different from the conventional digital PLL and that can be operated under a faster acquisition and wider capture range. This report describes the new digital timing recovery circuit architecture for magnetic recording that uses feedback delay compensators for fast acquisition and wide capture range on CMOS LSI circuit.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117095176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920563
C. Jung, H. C. Park, K. Ahn, J. Lee, K. H. Kweon, J. Choi, E. Haq, H. Lim
Achieving fast access time at low voltage and low power is still a demanding task for high density SRAM. Although some previous BiCMOS designs operate at 3.3 V, the access time is usually slower than at 5 V. The speed is mainly dependent on the I/O interface conversion and delay due to long data lines. We developed a look-ahead input buffer to reduce the speed delay at the input stage and a dynamic load sensing scheme to minimize the sensing delay due to long data line. A 3.3 V 1 Mbit(l28K x 8) SRAM is designed to achieve 4.5 ns access time under typical conditions using 0.5 /spl mu/m BiCMOS technology.
对于高密度SRAM来说，在低电压和低功耗下实现快速访问时间仍然是一项艰巨的任务。虽然以前的一些BiCMOS设计工作在3.3 V，但访问时间通常比5 V慢。速度主要取决于I/O接口转换和由于长数据线造成的延迟。我们开发了一种前瞻性输入缓冲器来减少输入阶段的速度延迟，并开发了一种动态负载传感方案来减少由于长数据线引起的传感延迟。3.3 V 1mbit (l28K x 8) SRAM采用0.5 /spl mu/m BiCMOS技术，在典型条件下实现4.5 ns的访问时间。
{"title":"Look-ahead input buffer and dynamic load sensing scheme for 3.3 V ultrafast BiCMOS SRAMs","authors":"C. Jung, H. C. Park, K. Ahn, J. Lee, K. H. Kweon, J. Choi, E. Haq, H. Lim","doi":"10.1109/VLSIC.1993.920563","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920563","url":null,"abstract":"Achieving fast access time at low voltage and low power is still a demanding task for high density SRAM. Although some previous BiCMOS designs operate at 3.3 V, the access time is usually slower than at 5 V. The speed is mainly dependent on the I/O interface conversion and delay due to long data lines. We developed a look-ahead input buffer to reduce the speed delay at the input stage and a dynamic load sensing scheme to minimize the sensing delay due to long data line. A 3.3 V 1 Mbit(l28K x 8) SRAM is designed to achieve 4.5 ns access time under typical conditions using 0.5 /spl mu/m BiCMOS technology.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920520
C. Portmann, T. Meng
We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.
{"title":"Loading effects on metastable parameters of CMOS latches","authors":"C. Portmann, T. Meng","doi":"10.1109/VLSIC.1993.920520","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920520","url":null,"abstract":"We have discussed the behavior of buffered and unbuffered latches versus loading from a metastable performance viewpoint. A formula to determine T/sub 0/ for a buffered latch from an unbuffered one has been described. Measured results were presented for buffered and unbuffered latches. The results shown here are relevant to standard cell or gate array ASIC designers who generally use cells contained within a library and have little control over the cells, but some control over the selection and loading. Our results show the buffered version is superior for all fanouts greater than one; however, the MTBF performance is still exponentially related to loading.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920549
Y. Tsukikawa, T. Kajimoto, Yasuhiko Okasaka, Y. Morooka, K. Furutani, H. Miyamoto, H. Ozaki
The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.
{"title":"An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAMs","authors":"Y. Tsukikawa, T. Kajimoto, Yasuhiko Okasaka, Y. Morooka, K. Furutani, H. Miyamoto, H. Ozaki","doi":"10.1109/VLSIC.1993.920549","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920549","url":null,"abstract":"The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131419523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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