Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920567
P. Pai, A. Abidi
After an extensive study of waveforms measured on several popular disk head-medium combinations, we have found that the combination of the head and medium itself often distorts the read pulse in phase, and a simple equalizer correcting for this phase distortion yields dramatic improvements in bit error rate. This equalizer surprisingly requires only four poles and one zero in the right-half s-plane to perform as well as a conventional flat group delay filter, and its constellation seems to apply to all the packing densities and drive types we have evaluated. We describe here a 2-/spl mu/m CMOS monolithic implementation of this new equalizing filter, with a maximum pole frequency of 25 MHz and an active core power dissipation of only 40 mW from a 5 V supply, including all tuning and subsidiary circuits.
{"title":"A simplified, low power 25 MHz CMOS equalizer for disk drive read channels","authors":"P. Pai, A. Abidi","doi":"10.1109/VLSIC.1993.920567","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920567","url":null,"abstract":"After an extensive study of waveforms measured on several popular disk head-medium combinations, we have found that the combination of the head and medium itself often distorts the read pulse in phase, and a simple equalizer correcting for this phase distortion yields dramatic improvements in bit error rate. This equalizer surprisingly requires only four poles and one zero in the right-half s-plane to perform as well as a conventional flat group delay filter, and its constellation seems to apply to all the packing densities and drive types we have evaluated. We describe here a 2-/spl mu/m CMOS monolithic implementation of this new equalizing filter, with a maximum pole frequency of 25 MHz and an active core power dissipation of only 40 mW from a 5 V supply, including all tuning and subsidiary circuits.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"33 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124331266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920530
Takayulu Kawahara, Y. Kawajiri, M. Horiguchi, T. Akiba, G. Kitsukawa, T. Kure, M. Aoki
A low-power charge recycle refresh featuring alternative operation of two arrays was proposed. After amplification in the first array, the charges in that array are transferred to the other array, where they are recycled for half the amplification there. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is also reduced. This technique can reduce the data retention current in Gb-scale or subGb-scale DRAMs, where the reduction of data-retention current by extending the refresh period is limited by the cell retention time.
{"title":"A charge recycle refresh for Gb-scale DRAMs in file applications","authors":"Takayulu Kawahara, Y. Kawajiri, M. Horiguchi, T. Akiba, G. Kitsukawa, T. Kure, M. Aoki","doi":"10.1109/VLSIC.1993.920530","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920530","url":null,"abstract":"A low-power charge recycle refresh featuring alternative operation of two arrays was proposed. After amplification in the first array, the charges in that array are transferred to the other array, where they are recycled for half the amplification there. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is also reduced. This technique can reduce the data retention current in Gb-scale or subGb-scale DRAMs, where the reduction of data-retention current by extending the refresh period is limited by the cell retention time.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122907267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920564
T. Yabe, F. Matsuoka, K. Sato, S. Hayakawa, M. Matsui, A. Aono, H. Yoshimura, K. Ishimaru, H. Gojohbori, S. Morita, Y. Unno, M. Kakumu, K. Ochii
This paper describes high-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM. Several 1 V operating SRAMs have been reported so far, but none of them achieves both fast access time of 200 ns at 1 V and low standby power below O.1 /spl mu/W under 1-3 V range compatibly. This 1Mb SRAM is designed to achieve the performance above, which is suitable for both 1.5 V battery-operational application and 3 V use. Several circuit techniques such as Multi-Vth CMOS gates, Switched Delay-Line Pulse Generator ( SDLPG) and Resistor-inserted Current mirror sense Amplifier (RCSA) have been developed.
{"title":"High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM","authors":"T. Yabe, F. Matsuoka, K. Sato, S. Hayakawa, M. Matsui, A. Aono, H. Yoshimura, K. Ishimaru, H. Gojohbori, S. Morita, Y. Unno, M. Kakumu, K. Ochii","doi":"10.1109/VLSIC.1993.920564","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920564","url":null,"abstract":"This paper describes high-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM. Several 1 V operating SRAMs have been reported so far, but none of them achieves both fast access time of 200 ns at 1 V and low standby power below O.1 /spl mu/W under 1-3 V range compatibly. This 1Mb SRAM is designed to achieve the performance above, which is suitable for both 1.5 V battery-operational application and 3 V use. Several circuit techniques such as Multi-Vth CMOS gates, Switched Delay-Line Pulse Generator ( SDLPG) and Resistor-inserted Current mirror sense Amplifier (RCSA) have been developed.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133974045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920525
B. Razavi, Y. Ota, R. Swartz
This paper describes design techniques for multi-GHz digital bipolar circuits that operate with supply voltages as low as 1.5 V. Examples include a multiplexer (MUX), a latch, two exclusive OR (XOR) gates, and a buffer/level shifter, circuits that typically employ stacked differential pairs in conventional ECL and hence do not easily lend themselves to low voltage operation. When implemented in a 1.5 /spl mu/m, 12-GHz bipolar technology, these circuits exhibit a speed comparable with that of their 1.5 V CMOS counterparts designed in a 0.5 /spl mu/m process with a threshold voltage of 0.5 V. These results suggest that, although V/sub BE/ of bipolar transistors does not scale as easily as the threshold voltage of MOS devices, the large bipolar transconductance can be advantageous even in 1.5 V systems. In order to ensure reliable operation, the circuits described herein employ 400 mV single-ended swings and can also provide differential outputs.
{"title":"Low voltage techniques for high speed digital bipolar circuits","authors":"B. Razavi, Y. Ota, R. Swartz","doi":"10.1109/VLSIC.1993.920525","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920525","url":null,"abstract":"This paper describes design techniques for multi-GHz digital bipolar circuits that operate with supply voltages as low as 1.5 V. Examples include a multiplexer (MUX), a latch, two exclusive OR (XOR) gates, and a buffer/level shifter, circuits that typically employ stacked differential pairs in conventional ECL and hence do not easily lend themselves to low voltage operation. When implemented in a 1.5 /spl mu/m, 12-GHz bipolar technology, these circuits exhibit a speed comparable with that of their 1.5 V CMOS counterparts designed in a 0.5 /spl mu/m process with a threshold voltage of 0.5 V. These results suggest that, although V/sub BE/ of bipolar transistors does not scale as easily as the threshold voltage of MOS devices, the large bipolar transconductance can be advantageous even in 1.5 V systems. In order to ensure reliable operation, the circuits described herein employ 400 mV single-ended swings and can also provide differential outputs.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123037921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920558
L. De Vito, M. Ishikawa
Summary form only given. Rapid process enhancement and broad applicability of mixed-signal LSIs require shrinking the analog section to the same short development cycle time as the digital section. However, in contrast to digital, where a simple linear shrink works fine, there are many thorny issues to be considered for the analog shrink, such as noise, crosstalk, unwanted oscillation, and a variety of undesirable interactions.
{"title":"Fundamental limits to analog scaling","authors":"L. De Vito, M. Ishikawa","doi":"10.1109/VLSIC.1993.920558","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920558","url":null,"abstract":"Summary form only given. Rapid process enhancement and broad applicability of mixed-signal LSIs require shrinking the analog section to the same short development cycle time as the digital section. However, in contrast to digital, where a simple linear shrink works fine, there are many thorny issues to be considered for the analog shrink, such as noise, crosstalk, unwanted oscillation, and a variety of undesirable interactions.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"3 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920512
B. Ackland
The adoption of video coding standards, the deployment of digital communication services and the availability of high performance full custom VLSI will open up a wide range of exciting new multimedia products and services. These devices stretch the limits of our silicon technology but will continue to benefit from advances in processing, circuit design, packaging and CAD tools.
{"title":"The role of VLSI in multimedia","authors":"B. Ackland","doi":"10.1109/VLSIC.1993.920512","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920512","url":null,"abstract":"The adoption of video coding standards, the deployment of digital communication services and the availability of high performance full custom VLSI will open up a wide range of exciting new multimedia products and services. These devices stretch the limits of our silicon technology but will continue to benefit from advances in processing, circuit design, packaging and CAD tools.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125243255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920518
D. Priore
It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical "RC" time constants in this environment dwarf the "time of flight" of light across the distances involved. However, with the advent of large chips running at upwards of 100MHz, this assumption is called into question. Furthermore, due to the lossy nature of the silicon environment, the "time of flight" in question does not follow simply from the delay rate of light in silicon dioxide (i.e. 66ps/cm). In general, it is greater. This paper attempts to frame the problem and suggest design principles to deal with it. These principles have been used extensively in the design of a 200MHz 64-bit dual-issue CMOS microprocessor.
{"title":"Inductance on silicon for sub-micron CMOS VLSI","authors":"D. Priore","doi":"10.1109/VLSIC.1993.920518","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920518","url":null,"abstract":"It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical \"RC\" time constants in this environment dwarf the \"time of flight\" of light across the distances involved. However, with the advent of large chips running at upwards of 100MHz, this assumption is called into question. Furthermore, due to the lossy nature of the silicon environment, the \"time of flight\" in question does not follow simply from the delay rate of light in silicon dioxide (i.e. 66ps/cm). In general, it is greater. This paper attempts to frame the problem and suggest design principles to deal with it. These principles have been used extensively in the design of a 200MHz 64-bit dual-issue CMOS microprocessor.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920554
S. Schuster, N. Lu
Summary form only given. Rapid advances in technology and design have resulted in microprocessors with greater than 200 MHz clock rates and several hundred I/O. In this high speed environment the reliable transmission of signals between logic and memory is a fundamental requirement.The problem is further exacerbated by the widening gap between processor and memory performance.
{"title":"Interfacing of high speed logic and memory","authors":"S. Schuster, N. Lu","doi":"10.1109/VLSIC.1993.920554","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920554","url":null,"abstract":"Summary form only given. Rapid advances in technology and design have resulted in microprocessors with greater than 200 MHz clock rates and several hundred I/O. In this high speed environment the reliable transmission of signals between logic and memory is a fundamental requirement.The problem is further exacerbated by the widening gap between processor and memory performance.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129597364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920565
M. Iwabuchi, M. Usami, M. Kashiyama, Takashi Oomori, Shigeharu Murata, T. Hiramoto, T. Hashimoto, Yasuhiro Nakajima
High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.
高速存储器已在计算机中用作缓冲存储器。这种存储器与高速算术单元相互连接，存储器的运算周期时间支配着计算机的性能。此外，为了扩大数据吞吐量，提供双端口RAM功能的高速循环存储器是非常有利的，可以同时读取和写入。本文报道了一种工作周期为1.5 ns的伪双端口RAM。该芯片包含18kbit RAM (256word x 9bit x 8block)和9k门外设逻辑门，工作周期为1.5 ns。它是采用SOI晶圆和沟槽隔离的双多晶硅自对准双极工艺制造的。
{"title":"A 1.5 ns cycle-time 18 kb pseudo-dual-port RAM","authors":"M. Iwabuchi, M. Usami, M. Kashiyama, Takashi Oomori, Shigeharu Murata, T. Hiramoto, T. Hashimoto, Yasuhiro Nakajima","doi":"10.1109/VLSIC.1993.920565","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920565","url":null,"abstract":"High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920533
M. Horiguchi, T. Sakata, K. Itoh
The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.
{"title":"Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's","authors":"M. Horiguchi, T. Sakata, K. Itoh","doi":"10.1109/VLSIC.1993.920533","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920533","url":null,"abstract":"The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature. This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode. The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance. This scheme permits battery backup even for giga-scale LSIs.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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