Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920524
T. Kuroda, T. Fujita, Makato Noda, Y. Itabashi, S. Kabumoto, T. S. Wong, D. Beeson, D. Gray
This paper introduces a new, self-adjusting active pull-down circuit for ECL that uses voltage regulation rather than traditional load-dependent capacitive coupling. Depending on the application, a 3.5X speed improvement over traditional ECL at comparable power, or a 7.1X power reduction at comparable performance can be obtained. A voltage regulation and distribution circuit for the required V/sub REG/ reference voltage is also presented.
{"title":"Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability","authors":"T. Kuroda, T. Fujita, Makato Noda, Y. Itabashi, S. Kabumoto, T. S. Wong, D. Beeson, D. Gray","doi":"10.1109/VLSIC.1993.920524","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920524","url":null,"abstract":"This paper introduces a new, self-adjusting active pull-down circuit for ECL that uses voltage regulation rather than traditional load-dependent capacitive coupling. Depending on the application, a 3.5X speed improvement over traditional ECL at comparable power, or a 7.1X power reduction at comparable performance can be obtained. A voltage regulation and distribution circuit for the required V/sub REG/ reference voltage is also presented.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132228815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920527
H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, Y. Nagano
We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).
我们讨论了一种使用量化神经元的数字神经处理器，用于字符或图像识别和学习。神经网络中突触的数量对图像的准确识别是一个非常重要的因素。具有大量突触的神经网络可以达到较高的识别精度，但由于网络计算量大，使得处理速度降低。为了实现大量突触和高速处理，采用多功能分层网络(MFLN)模型制作了一种神经处理器。该神经处理器采用1.2 /spl μ m双金属CMOS，即栅极海洋技术，在一个芯片上包含27000个栅极。芯片尺寸为10.99 mm × 10.93 mm。神经处理器以25秒的时钟周期运行。在组合函数宽度为3的情况下，以4,736个神经元和200万个突触权重在2.8毫秒内模拟了MFLN模型。因此，性能为0.76 GCPS (Giga Connections Per Second)。当组合函数的宽度为1时，得到20.5 GCPS。它可以以20.0 MCUPS(每秒更新的兆连接)的速度执行Hebbian学习。
{"title":"A digital neuroprocessor using quantizer neurons","authors":"H. Nakahira, S. Sakiyama, M. Maruyama, K. Hasegawa, T. Kouda, S. Maruno, Y. Shimeki, T. Satonaka, Y. Nagano","doi":"10.1109/VLSIC.1993.920527","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920527","url":null,"abstract":"We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 /spl mu/m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second).","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133761055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920540
R. Swartz, Y. Ota, M. Tarsia, V. Archer
This paper describes a burst mode amplifier for packet mode, optical bus applications in the range of 1 Mb/s to 50 Mb/s. The circuit establishes an instantaneous logic threshold at the beginning of an optical data burst, handling photo-data packets differing by much as 50:1 in amplitude and separated by <145 ns, and with background light levels up to 100 times larger than the data signal.
{"title":"A burst mode, packet receiver with precision reset and automatic dark level compensation for optical bus communications","authors":"R. Swartz, Y. Ota, M. Tarsia, V. Archer","doi":"10.1109/VLSIC.1993.920540","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920540","url":null,"abstract":"This paper describes a burst mode amplifier for packet mode, optical bus applications in the range of 1 Mb/s to 50 Mb/s. The circuit establishes an instantaneous logic threshold at the beginning of an optical data burst, handling photo-data packets differing by much as 50:1 in amplitude and separated by <145 ns, and with background light levels up to 100 times larger than the data signal.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920559
S. Kobayashi, Hiroaki Nakai, Y. Kunori, T. Nakayama, Y. Miyawaki, Y. Terada, H. Onoda, N. Ajika, M. Hatanaka, H. Miyoshi, T. Yoshihara
A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc. A 4 Mb test device was fabricated in a 0.5 /spl mu/m CMOS triple well process and a typical access time of 90 ns was obtained at Vcc of 3 V.
{"title":"Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory","authors":"S. Kobayashi, Hiroaki Nakai, Y. Kunori, T. Nakayama, Y. Miyawaki, Y. Terada, H. Onoda, N. Ajika, M. Hatanaka, H. Miyoshi, T. Yoshihara","doi":"10.1109/VLSIC.1993.920559","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920559","url":null,"abstract":"A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc. A 4 Mb test device was fabricated in a 0.5 /spl mu/m CMOS triple well process and a typical access time of 90 ns was obtained at Vcc of 3 V.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920514
Shigeya Tanaka, T. Hotta, F. Murabayashi, H. Yamada, Shoji Yoshida, K. Shimamura, K. Katsura, T. Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, T. Nakano, Teruhisa Shimizu, R. Satomura
Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.
{"title":"A 120 MHz BiCMOS superscalar RISC processor","authors":"Shigeya Tanaka, T. Hotta, F. Murabayashi, H. Yamada, Shoji Yoshida, K. Shimamura, K. Katsura, T. Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, T. Nakano, Teruhisa Shimizu, R. Satomura","doi":"10.1109/VLSIC.1993.920514","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920514","url":null,"abstract":"Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126297339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920516
A. Maki, Y. Nagano, M. Mori, M. Shigenaga
Recently, the demand for using low-end RISC-CPUs in small equipment devices such as handy terminals is increasing. On-chip cache and direct connections to page mode DRAM is one of the best solution to achieve high-performance and low-cost systems. However, integrating the conventional cache will have a penalty of cache miss increase when page mode DRAM is used for burst transfer mode. This paper describes a new on-chip small instruction cache (called Variable Line Length Cache) for low-end RISC CPU. When a cache-miss signal occurs, this cache continuously reloads, pre-fetches and supplies the instructions though it consists of conventional RAMs. With this new cache, the reduction of the total waits is 20 to 30 percent less compared to the conventional cache when it is adapted to the application specified RISC processor, so that the new cache improves the cache hit ratio.
{"title":"A continuous reload on-chip instruction cache for low-end RISC","authors":"A. Maki, Y. Nagano, M. Mori, M. Shigenaga","doi":"10.1109/VLSIC.1993.920516","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920516","url":null,"abstract":"Recently, the demand for using low-end RISC-CPUs in small equipment devices such as handy terminals is increasing. On-chip cache and direct connections to page mode DRAM is one of the best solution to achieve high-performance and low-cost systems. However, integrating the conventional cache will have a penalty of cache miss increase when page mode DRAM is used for burst transfer mode. This paper describes a new on-chip small instruction cache (called Variable Line Length Cache) for low-end RISC CPU. When a cache-miss signal occurs, this cache continuously reloads, pre-fetches and supplies the instructions though it consists of conventional RAMs. With this new cache, the reduction of the total waits is 20 to 30 percent less compared to the conventional cache when it is adapted to the application specified RISC processor, so that the new cache improves the cache hit ratio.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920538
T. Sugibayashi, T. Takeshima, I. Naritake, T. Matano, H. Takada, Y. Aimoto, M. Fujita
This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.
{"title":"A distributive serial multi-bit parallel test scheme for large capacity DRAMs","authors":"T. Sugibayashi, T. Takeshima, I. Naritake, T. Matano, H. Takada, Y. Aimoto, M. Fujita","doi":"10.1109/VLSIC.1993.920538","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920538","url":null,"abstract":"This paper describes a distributive serial multi-bit parallel test scheme suitable for large capacity DRAMs. It achieves a high parallel test bit number and, with regard to cells and sense amplifiers, the same operational margin as normal mode. Further, it imposes little restriction on test patterns. The scheme has successfully achieved a 512 bit parallel test on an experimental 256Mb DRAM.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920553
M. Asakura, T. Oishi, S. Tomishima, H. Hidaka, K. Arimoto, K. Fujishima
The density of DRAM has at last reached 256Mb at experimental level. Nevertheless, to realize a mass produced device, serious design problems still remain even if the performance related problems such as access time and power consumption are excluded. They are the problem of yield and test time explosion. This paper describes a new array architecture which implements a flexible redundant scheme and a new test time reduction capability with the reduction of chip size. In this architecture, the number of sense-amplifiers is reduced using a hierarchical bit-line (main/sub bit-line) without degradation of basic parameters such as bit-line parasitic capacitance and bit-line resistance. This redundant scheme features the flexibility of row replacement without a complicated control sequence. The new test mode is "block compare test" (BCT), in which the data stored in memory cells connected to two word-lines belonging to different blocks can be checked simultaneously for any data pattern.
{"title":"A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM","authors":"M. Asakura, T. Oishi, S. Tomishima, H. Hidaka, K. Arimoto, K. Fujishima","doi":"10.1109/VLSIC.1993.920553","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920553","url":null,"abstract":"The density of DRAM has at last reached 256Mb at experimental level. Nevertheless, to realize a mass produced device, serious design problems still remain even if the performance related problems such as access time and power consumption are excluded. They are the problem of yield and test time explosion. This paper describes a new array architecture which implements a flexible redundant scheme and a new test time reduction capability with the reduction of chip size. In this architecture, the number of sense-amplifiers is reduced using a hierarchical bit-line (main/sub bit-line) without degradation of basic parameters such as bit-line parasitic capacitance and bit-line resistance. This redundant scheme features the flexibility of row replacement without a complicated control sequence. The new test mode is \"block compare test\" (BCT), in which the data stored in memory cells connected to two word-lines belonging to different blocks can be checked simultaneously for any data pattern.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920572
T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, K. Okada
This paper describes a low-power BiCMOS A/D converter using a "differential voltage subconverter", which directly converts a voltage difference of complementary analog inputs to a digital code. This conversion technique reduces power consumption and signal delay in the A/D converter. Several circuit techniques have also been newly developed to achieve high-accuracy conversion with single 5 V power supply. The 10-bit A/D converter is fabricated in a 0.8 /spl mu/m BiCMOS process and it operates at 50 MS/s with 500 mW.
本文介绍了一种低功耗BiCMOS a /D转换器，该转换器采用“差分电压子转换器”，将互补模拟输入的电压差直接转换为数字代码。这种转换技术降低了A/D转换器的功耗和信号延迟。一些新的电路技术也被开发出来，以实现单5v电源的高精度转换。该10位A/D转换器采用0.8 /spl mu/m BiCMOS工艺制造，工作速度为50 MS/s，功率为500 mW。
{"title":"A 10-bit 50 MS/s 500 mW A/D converter using differential-voltage subconverter","authors":"T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, K. Okada","doi":"10.1109/VLSIC.1993.920572","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920572","url":null,"abstract":"This paper describes a low-power BiCMOS A/D converter using a \"differential voltage subconverter\", which directly converts a voltage difference of complementary analog inputs to a digital code. This conversion technique reduces power consumption and signal delay in the A/D converter. Several circuit techniques have also been newly developed to achieve high-accuracy conversion with single 5 V power supply. The 10-bit A/D converter is fabricated in a 0.8 /spl mu/m BiCMOS process and it operates at 50 MS/s with 500 mW.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122522760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920568
A. Stevens, G. Miller
A new method for boosting the slew rate of a switched-capacitor integrator is introduced. The enhanced integrator contains an output booster stage which reduces the settling time by approximately a factor of three over an unboosted integrator. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by a factor of 40% and the total die area by a factor of 20%.
{"title":"A high-slew integrator for switched-capacitor circuits","authors":"A. Stevens, G. Miller","doi":"10.1109/VLSIC.1993.920568","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920568","url":null,"abstract":"A new method for boosting the slew rate of a switched-capacitor integrator is introduced. The enhanced integrator contains an output booster stage which reduces the settling time by approximately a factor of three over an unboosted integrator. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by a factor of 40% and the total die area by a factor of 20%.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115424375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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