Whereas the last four decades have seen a steady stream of new and new-generation devices for all forms of computing and communications, the next decade will see an increase in emphasis on low-cost manufacture. The reasons are manifold, but include new technical challenges, the structure of the industry, and an ever tighter focus on return on investment. The author discuss the challenges of achieving low-cost manufacture for a state-of-the-art (tunnelling-based) microwave detector, where the thickness of a critical layer must be controlled to within /spl plusmn/0/spl middot/2 monolayers to achieve a sufficiently high yield. The implications for the manufacture of other quantum-effect devices are also discussed.
{"title":"Manufacturability of high-performance discrete electronic devices","authors":"M. Kelly","doi":"10.1049/ECEJ:20020204","DOIUrl":"https://doi.org/10.1049/ECEJ:20020204","url":null,"abstract":"Whereas the last four decades have seen a steady stream of new and new-generation devices for all forms of computing and communications, the next decade will see an increase in emphasis on low-cost manufacture. The reasons are manifold, but include new technical challenges, the structure of the industry, and an ever tighter focus on return on investment. The author discuss the challenges of achieving low-cost manufacture for a state-of-the-art (tunnelling-based) microwave detector, where the thickness of a critical layer must be controlled to within /spl plusmn/0/spl middot/2 monolayers to achieve a sufficiently high yield. The implications for the manufacture of other quantum-effect devices are also discussed.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130345152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces an approach to managing quality-of-service (QoS) for a residential video-on-demand (VoD) service employing MPEG-2 transport streams using an experimental asynchronous transfer mode (ATM)/asymmetric digital subscriber line (ADSL) access network testbed. The paper examines the complex multilayer propagation of ATM layer parameters over an underlying physical layer and their relationship to video quality. The results obtained from the testbed provide an important insight into the factors relevant to the provisioning and management of new multiservice network infrastructures. Overall, these results contribute to an understanding of the multilayer QoS relationship and provide a basis for comparison with, and development of, similar systems. The paper proposes a method to aid the comparison of results based on a multilayer QoS approach.
{"title":"Quality-of-service management for broadband residential video services","authors":"R. Green, Sandra I. Woolley, N. Garnham, K. Jones","doi":"10.1049/ECEJ:20010604","DOIUrl":"https://doi.org/10.1049/ECEJ:20010604","url":null,"abstract":"This paper introduces an approach to managing quality-of-service (QoS) for a residential video-on-demand (VoD) service employing MPEG-2 transport streams using an experimental asynchronous transfer mode (ATM)/asymmetric digital subscriber line (ADSL) access network testbed. The paper examines the complex multilayer propagation of ATM layer parameters over an underlying physical layer and their relationship to video quality. The results obtained from the testbed provide an important insight into the factors relevant to the provisioning and management of new multiservice network infrastructures. Overall, these results contribute to an understanding of the multilayer QoS relationship and provide a basis for comparison with, and development of, similar systems. The paper proposes a method to aid the comparison of results based on a multilayer QoS approach.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124952085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits.
{"title":"Efficient methods for modelling substrate coupling in mixed-signal integrated circuits","authors":"R. Singh, S. Sali, W. L. Woo","doi":"10.1049/ECEJ:20010601","DOIUrl":"https://doi.org/10.1049/ECEJ:20010601","url":null,"abstract":"A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adaptive active phased-array radars are seen as the vehicle to address the current requirements for a true 'multifunction' radar system. Their ability to adapt to the environment and schedule their tasks in real time allows them to operate with performance levels well above those that can be achieved from conventional radar designs in addressing the current and future threats. Their ability to make effective use of all the available RF power and to minimise RF losses also makes them a good candidate for future very long range radars. This paper addresses the design of such radars in terms of the system and its component parts and the operational requirements that drive the design. The paper also considers some futures uses outside the military field.
{"title":"Design considerations for adaptive active phased-array 'multifunction' radars","authors":"J. Holloway","doi":"10.1049/ECEJ:20010605","DOIUrl":"https://doi.org/10.1049/ECEJ:20010605","url":null,"abstract":"Adaptive active phased-array radars are seen as the vehicle to address the current requirements for a true 'multifunction' radar system. Their ability to adapt to the environment and schedule their tasks in real time allows them to operate with performance levels well above those that can be achieved from conventional radar designs in addressing the current and future threats. Their ability to make effective use of all the available RF power and to minimise RF losses also makes them a good candidate for future very long range radars. This paper addresses the design of such radars in terms of the system and its component parts and the operational requirements that drive the design. The paper also considers some futures uses outside the military field.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Regulation is as controversial today as ever before. Some call for a 'lighter touch' while others demand stronger intervention to create 'Broadband Britain'. The author describes what regulators do and why, Oftel's accountability, the role of the engineer within Oftel and the forthcoming changes that will create OFCOM, the Office for Communications, from five existing communications regulators.
{"title":"Www.regulation: the why, what and whither of communications regulation","authors":"P. Walker","doi":"10.1049/ECEJ:20010603","DOIUrl":"https://doi.org/10.1049/ECEJ:20010603","url":null,"abstract":"Regulation is as controversial today as ever before. Some call for a 'lighter touch' while others demand stronger intervention to create 'Broadband Britain'. The author describes what regulators do and why, Oftel's accountability, the role of the engineer within Oftel and the forthcoming changes that will create OFCOM, the Office for Communications, from five existing communications regulators.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130525753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A quantitative comparison is made between the computational requirements of typical systems-on-chip and the computational capabilities of silicon. This is illustrated by the evolution of TV and other video appliances on the one hand and the progress of silicon technology on the other. As a basic benchmark figure the concept of the intrinsic computational efficiency (ICE) of silicon is introduced, and this is compared with the computational efficiency of commercial microprocessors and digital signal processors. It is shown that processors designed by application-specific architectural synthesis can approximate the ICE limit and that they exceed the computational efficiency of general-purpose devices by several orders of magnitude. To close the gap between flexibility and efficiency, the silicon system platform concept is introduced. Finally, it is shown how Moore's law of exponential growth together with Claasen's law of logarithmic usefulness make the perceived progression in systems a linear function of time.
{"title":"Systems-on-chip: what are the limits?","authors":"E. Roza","doi":"10.1049/ECEJ:20010602","DOIUrl":"https://doi.org/10.1049/ECEJ:20010602","url":null,"abstract":"A quantitative comparison is made between the computational requirements of typical systems-on-chip and the computational capabilities of silicon. This is illustrated by the evolution of TV and other video appliances on the one hand and the progress of silicon technology on the other. As a basic benchmark figure the concept of the intrinsic computational efficiency (ICE) of silicon is introduced, and this is compared with the computational efficiency of commercial microprocessors and digital signal processors. It is shown that processors designed by application-specific architectural synthesis can approximate the ICE limit and that they exceed the computational efficiency of general-purpose devices by several orders of magnitude. To close the gap between flexibility and efficiency, the silicon system platform concept is introduced. Finally, it is shown how Moore's law of exponential growth together with Claasen's law of logarithmic usefulness make the perceived progression in systems a linear function of time.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optoelectronic interconnects between VLSI chips have been identified by the Semiconductor Industry Association (SIA) Roadmap as one of the few solutions to overcoming the communication bandwidth bottleneck between VLSI chips. Large-scale demonstrators based on optical interconnects, when fully operational, can exhibit today the same aggregate bandwidth as that foreseen by the Roadmap for the year 2007. Massive parallelism, low input/output driving energy over large distances, and synchronous processing of hundreds of optical information input channels mean that these prototypes can potentially provide on/off communication rates in the tera-pin-Hz region (i.e., a total capacity of one terabit/s). After discussing the limitations of electrical interconnects this paper reviews the means of integrating optoelectronic components with VLSI chips, suitable types of optoelectronic device and the three main approaches to constructing optical data links: fibre-ribbons, planar waveguides and free-space optics.
{"title":"Optically interconnected electronic chips: a tutorial and review of the technology","authors":"M. G. Forbes, J. Gourlay, M. Desmulliez","doi":"10.1049/ECEJ:20010506","DOIUrl":"https://doi.org/10.1049/ECEJ:20010506","url":null,"abstract":"Optoelectronic interconnects between VLSI chips have been identified by the Semiconductor Industry Association (SIA) Roadmap as one of the few solutions to overcoming the communication bandwidth bottleneck between VLSI chips. Large-scale demonstrators based on optical interconnects, when fully operational, can exhibit today the same aggregate bandwidth as that foreseen by the Roadmap for the year 2007. Massive parallelism, low input/output driving energy over large distances, and synchronous processing of hundreds of optical information input channels mean that these prototypes can potentially provide on/off communication rates in the tera-pin-Hz region (i.e., a total capacity of one terabit/s). After discussing the limitations of electrical interconnects this paper reviews the means of integrating optoelectronic components with VLSI chips, suitable types of optoelectronic device and the three main approaches to constructing optical data links: fibre-ribbons, planar waveguides and free-space optics.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127773997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The limits to the 'dot.com revolution' have been discovered the hard way and it has been recognised that TV and audio products are likely to be significant drivers in the development of digital networks in the home. The paper provides an overview of developments in the consumer electronics field from the TV manufacturer's perspective, their relationship to the home network and some of the problems faced.
{"title":"Home networking: a TV perspective","authors":"P. Marshall","doi":"10.1049/ECEJ:20010503","DOIUrl":"https://doi.org/10.1049/ECEJ:20010503","url":null,"abstract":"The limits to the 'dot.com revolution' have been discovered the hard way and it has been recognised that TV and audio products are likely to be significant drivers in the development of digital networks in the home. The paper provides an overview of developments in the consumer electronics field from the TV manufacturer's perspective, their relationship to the home network and some of the problems faced.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130235726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The availability of digital entertainment devices is increasing rapidly and the need to interconnect them is ever more important. This paper gives a description of the technical standards that are key to the definition and design of high-speed integrated digital networks and the approach that is being taken to extend the network into the wireless domain. These standards address both the method of interconnection and the means to ensure that there is full interoperability between digital entertainment appliances in a user-friendly manner.
{"title":"In-home wireless networking: an entertainment perspective","authors":"D. Evans","doi":"10.1049/ECEJ:20010504","DOIUrl":"https://doi.org/10.1049/ECEJ:20010504","url":null,"abstract":"The availability of digital entertainment devices is increasing rapidly and the need to interconnect them is ever more important. This paper gives a description of the technical standards that are key to the definition and design of high-speed integrated digital networks and the approach that is being taken to extend the network into the wireless domain. These standards address both the method of interconnection and the means to ensure that there is full interoperability between digital entertainment appliances in a user-friendly manner.","PeriodicalId":127784,"journal":{"name":"Electronics & Communication Engineering Journal","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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