Pub Date : 2023-09-22DOI: 10.1109/TETC.2023.3315748
Sarad Venugopalan;Ivana Stančíková;Ivan Homoliak
Elections repeat commonly after a fixed time interval, ranging from months to years. This results in limitations on governance since elected candidates or policies are difficult to remove before the next elections, if needed, and allowed by the corresponding law. Participants may decide (through a public deliberation) to change their choices but have no opportunity to vote for these choices before the next elections. Another issue is the peak-end effect, where the judgment of voters is based on how they felt a short time before the elections. To address these issues, we propose Always on Voting (AoV) – a repetitive voting framework that allows participants to vote and change elected candidates or policies without waiting for the next elections. Participants are permitted to privately change their vote at any point in time, while the effect of their change is manifested at the end of each epoch, whose duration is shorter than the time between two main elections. To thwart the problem of peak-end effect in epochs, the ends of epochs are randomized and made unpredictable, while preserved within soft bounds. These goals are achieved using the synergy between a Bitcoin puzzle oracle, verifiable delay function, and smart contracts.
选举通常在固定的时间间隔后重复进行，间隔时间从数月到数年不等。这就造成了对治理的限制，因为当选的候选人或政策很难在下次选举前（如果需要）被撤换，而且相应的法律也允许这样做。参与者可以（通过公开讨论）决定改变他们的选择，但没有机会在下次选举前对这些选择进行投票。另一个问题是峰末效应，即选民的判断是基于选举前不久的感受。为了解决这些问题，我们提出了 "随时投票"（Always on Voting，AoV）--一种重复投票框架，允许参与者投票并改变当选的候选人或政策，而无需等待下一次选举。参与者可以在任何时间点私下更改投票，而更改的效果会在每个纪元结束时体现出来，每个纪元的持续时间比两次主要选举之间的时间短。为了避免历时峰值效应的问题，历时的结束时间是随机的，不可预测，同时保持在软约束范围内。这些目标是通过比特币谜题甲骨文、可验证延迟函数和智能合约之间的协同作用来实现的。
{"title":"Always on Voting: A Framework for Repetitive Voting on the Blockchain","authors":"Sarad Venugopalan;Ivana Stančíková;Ivan Homoliak","doi":"10.1109/TETC.2023.3315748","DOIUrl":"https://doi.org/10.1109/TETC.2023.3315748","url":null,"abstract":"Elections repeat commonly after a fixed time interval, ranging from months to years. This results in limitations on governance since elected candidates or policies are difficult to remove before the next elections, if needed, and allowed by the corresponding law. Participants may decide (through a public deliberation) to change their choices but have no opportunity to vote for these choices before the next elections. Another issue is the peak-end effect, where the judgment of voters is based on how they felt a short time before the elections. To address these issues, we propose Always on Voting (AoV) – a repetitive voting framework that allows participants to vote and change elected candidates or policies without waiting for the next elections. Participants are permitted to privately change their vote at any point in time, while the effect of their change is manifested at the end of each epoch, whose duration is shorter than the time between two main elections. To thwart the problem of peak-end effect in epochs, the ends of epochs are randomized and made unpredictable, while preserved within soft bounds. These goals are achieved using the synergy between a Bitcoin puzzle oracle, verifiable delay function, and smart contracts.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138558040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-22DOI: 10.1109/TETC.2023.3316121
Marco Paul E. Apolinario;Adarsh Kumar Kosta;Utkarsh Saxena;Kaushik Roy
Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard GPUs are not optimized to deploy SNNs, resulting in high energy and latency. While analog In-Memory Computing (IMC) platforms can serve as energy-efficient inference engines, they are accursed by the immense energy, latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing the benefits of in-memory computations. We propose a hardware/software co-design methodology to deploy SNNs into an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating the above issues. Our proposed framework incurs minimal accuracy degradation by performing hardware-aware training and is able to scale beyond simple image classification tasks to more complex sequential regression tasks. Experiments on complex tasks of optical flow estimation and gesture recognition show that progressively increasing the hardware awareness during SNN training allows the model to adapt and learn the errors due to the non-idealities associated with ADC-Less IMC. Also, the proposed ADC-Less IMC offers significant energy and latency improvements, $2-7times$ and $8.9-24.6times$ , respectively, depending on the SNN model and the workload, compared to HP-ADC IMC.
{"title":"Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks","authors":"Marco Paul E. Apolinario;Adarsh Kumar Kosta;Utkarsh Saxena;Kaushik Roy","doi":"10.1109/TETC.2023.3316121","DOIUrl":"10.1109/TETC.2023.3316121","url":null,"abstract":"Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard GPUs are not optimized to deploy SNNs, resulting in high energy and latency. While analog In-Memory Computing (IMC) platforms can serve as energy-efficient inference engines, they are accursed by the immense energy, latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing the benefits of in-memory computations. We propose a hardware/software co-design methodology to deploy SNNs into an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating the above issues. Our proposed framework incurs minimal accuracy degradation by performing hardware-aware training and is able to scale beyond simple image classification tasks to more complex sequential regression tasks. Experiments on complex tasks of optical flow estimation and gesture recognition show that progressively increasing the hardware awareness during SNN training allows the model to adapt and learn the errors due to the non-idealities associated with ADC-Less IMC. Also, the proposed ADC-Less IMC offers significant energy and latency improvements, \u0000<inline-formula><tex-math>$2-7times$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$8.9-24.6times$</tex-math></inline-formula>\u0000, respectively, depending on the SNN model and the workload, compared to HP-ADC IMC.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135599176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Group cohesion is regarded as a central group property across both social psychology and sociology. It facilities the understanding of the organizational behavior of users, and in turn guides the users to work well together in order to achieve goals within a social network. Therefore, group cohesion assessment is a crucial research issue for social network analysis. Group cohesion is often viewed as network density in the current state-of-the-art. Due to the advantages of characterizing the cohesion of a network with concept stability, this article presents a novel group cohesion measure, called concept stability entropy inspired by Shannon Entropy. Particularly, the scale of concept stability entropy is investigated. Considering the dynamic nature of social networks, an incremental algorithm for concept stability entropy computation is devised. In addition, we explore the correlation between concept stability entropy and other related metrics, i.e., network density, average degree, and average clustering coefficient. Extensive experimental results first validate that the concept stability entropy falls into the range of $[0, log(k)]$ ( $k$ is the number of formal concepts), and then demonstrate that the concept stability entropy has a positive correlation with the average degree and a negative correlation with the network density and average clustering coefficient. Practically, a case study on the COVID-2019 virus network is conducted for illustrating the usefulness of our proposed group cohesion assessment approach.
{"title":"Concept Stability Entropy: A Novel Group Cohesion Measure in Social Networks","authors":"Fei Hao;Jie Gao;Yaguang Lin;Yulei Wu;Jiaxing Shang","doi":"10.1109/TETC.2023.3315335","DOIUrl":"10.1109/TETC.2023.3315335","url":null,"abstract":"Group cohesion is regarded as a central group property across both social psychology and sociology. It facilities the understanding of the organizational behavior of users, and in turn guides the users to work well together in order to achieve goals within a social network. Therefore, group cohesion assessment is a crucial research issue for social network analysis. Group cohesion is often viewed as network density in the current state-of-the-art. Due to the advantages of characterizing the cohesion of a network with concept stability, this article presents a novel group cohesion measure, called concept stability entropy inspired by Shannon Entropy. Particularly, the scale of concept stability entropy is investigated. Considering the dynamic nature of social networks, an incremental algorithm for concept stability entropy computation is devised. In addition, we explore the correlation between concept stability entropy and other related metrics, i.e., network density, average degree, and average clustering coefficient. Extensive experimental results first validate that the concept stability entropy falls into the range of \u0000<inline-formula><tex-math>$[0, log(k)]$</tex-math></inline-formula>\u0000 (\u0000<inline-formula><tex-math>$k$</tex-math></inline-formula>\u0000 is the number of formal concepts), and then demonstrate that the concept stability entropy has a positive correlation with the average degree and a negative correlation with the network density and average clustering coefficient. Practically, a case study on the COVID-2019 virus network is conducted for illustrating the usefulness of our proposed group cohesion assessment approach.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2023-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135556035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-20DOI: 10.1109/TETC.2023.3315298
Abbas Dehghani;Sadegh Fadaei;Bahman Ravaei;Keyvan RahimiZadeh
Hybrid Wireless Network-on-Chip (HWNoC) architecture has been introduced as a promising communication infrastructure for multicore systems. HWNoC-based multicore systems encounter extremely dynamic application workloads that are submitted at run-time. Mapping and scheduling of these applications are critical for system performance, especially for real-time applications. The existing resource allocation approaches either ignore the use of wireless links in task allocation on cores or ignore the timing characteristic of tasks. In this paper, we propose a new deadline-aware and energy-efficient dynamic task mapping and scheduling approach for the HWNoC-based multicore system. By using of core utilization threshold and tasks laxity time, the proposed approach aims to minimize communication energy consumption and satisfy the deadline of the real-time applications tasks. Through cycle-accurate simulation, the performance of the proposed approach has been compared with state-of-the-art approaches in terms of communication energy consumption, deadline violation rate, communication latency, and runtime overhead. The experimental results confirmed that the proposed approach is a very competitive approach among the alternative approaches.
{"title":"Deadline-Aware and Energy-Efficient Dynamic Task Mapping and Scheduling for Multicore Systems Based on Wireless Network-on-Chip","authors":"Abbas Dehghani;Sadegh Fadaei;Bahman Ravaei;Keyvan RahimiZadeh","doi":"10.1109/TETC.2023.3315298","DOIUrl":"10.1109/TETC.2023.3315298","url":null,"abstract":"Hybrid Wireless Network-on-Chip (HWNoC) architecture has been introduced as a promising communication infrastructure for multicore systems. HWNoC-based multicore systems encounter extremely dynamic application workloads that are submitted at run-time. Mapping and scheduling of these applications are critical for system performance, especially for real-time applications. The existing resource allocation approaches either ignore the use of wireless links in task allocation on cores or ignore the timing characteristic of tasks. In this paper, we propose a new deadline-aware and energy-efficient dynamic task mapping and scheduling approach for the HWNoC-based multicore system. By using of core utilization threshold and tasks laxity time, the proposed approach aims to minimize communication energy consumption and satisfy the deadline of the real-time applications tasks. Through cycle-accurate simulation, the performance of the proposed approach has been compared with state-of-the-art approaches in terms of communication energy consumption, deadline violation rate, communication latency, and runtime overhead. The experimental results confirmed that the proposed approach is a very competitive approach among the alternative approaches.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135555776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-19DOI: 10.1109/TETC.2023.3315189
Ben Perach;Ronny Ronen;Benny Kimelfeld;Shahar Kvatinsky
Bulk-bitwise processing-in-memory (PIM), where large bitwise operations are performed in parallel by the memory array itself, is an emerging form of computation with the potential to mitigate the memory wall problem. This article examines the capabilities of bulk-bitwise PIM by constructing PIMDB, a fully-digital system based on memristive stateful logic, utilizing and focusing on in-memory bulk-bitwise operations, designed to accelerate a real-life workload: analytical processing of relational databases. We introduce a host processor programming model to support bulk-bitwise PIM in virtual memory, develop techniques to efficiently perform in-memory filtering and aggregation operations, and adapt the application data set into the memory. To understand bulk-bitwise PIM, we compare it to an equivalent in-memory database on the same host system. We show that bulk-bitwise PIM substantially lowers the number of required memory read operations, thus accelerating TPC-H filter operations by 1.6×–18× and full queries by 56×–608×, while reducing the energy consumption by 1.7×–18.6× and 0.81×–12× for these benchmarks, respectively. Our extensive evaluation uses the gem5 full-system simulation environment. The simulations also evaluate cell endurance, showing that the required endurance is within the range of existing endurance of RRAM devices.
{"title":"Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics","authors":"Ben Perach;Ronny Ronen;Benny Kimelfeld;Shahar Kvatinsky","doi":"10.1109/TETC.2023.3315189","DOIUrl":"10.1109/TETC.2023.3315189","url":null,"abstract":"Bulk-bitwise processing-in-memory (PIM), where large bitwise operations are performed in parallel by the memory array itself, is an emerging form of computation with the potential to mitigate the memory wall problem. This article examines the capabilities of bulk-bitwise PIM by constructing PIMDB, a fully-digital system based on memristive stateful logic, utilizing and focusing on in-memory bulk-bitwise operations, designed to accelerate a real-life workload: analytical processing of relational databases. We introduce a host processor programming model to support bulk-bitwise PIM in virtual memory, develop techniques to efficiently perform in-memory filtering and aggregation operations, and adapt the application data set into the memory. To understand bulk-bitwise PIM, we compare it to an equivalent in-memory database on the same host system. We show that bulk-bitwise PIM substantially lowers the number of required memory read operations, thus accelerating TPC-H filter operations by 1.6×–18× and full queries by 56×–608×, while reducing the energy consumption by 1.7×–18.6× and 0.81×–12× for these benchmarks, respectively. Our extensive evaluation uses the gem5 full-system simulation environment. The simulations also evaluate cell endurance, showing that the required endurance is within the range of existing endurance of RRAM devices.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135551143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-05DOI: 10.1109/TETC.2023.3299150
Michael Grottke;Alberto Avritzer;Hironori Washizaki;Kishor Trivedi
Since the publication of the first paper on software aging and rejuvenation by Huang et al. in 1995 [1], considerable research has been devoted to this topic. It deals with the phenomenon that continuously-running software systems may show an increasing failure rate and/or a degrading performance, either because error conditions accumulate inside the running system or because the rate at which faults are activated and errors are propagated is positively correlated with system uptime. Software rejuvenation relates to techniques counteracting aging (for example, by regularly stopping and restarting the software) in order to remove aging effects and to proactively prevent failures from occurring.
{"title":"Guest Editorial Special Section on Applied Software Aging and Rejuvenation","authors":"Michael Grottke;Alberto Avritzer;Hironori Washizaki;Kishor Trivedi","doi":"10.1109/TETC.2023.3299150","DOIUrl":"10.1109/TETC.2023.3299150","url":null,"abstract":"Since the publication of the first paper on software aging and rejuvenation by Huang et al. in 1995 [1], considerable research has been devoted to this topic. It deals with the phenomenon that continuously-running software systems may show an increasing failure rate and/or a degrading performance, either because error conditions accumulate inside the running system or because the rate at which faults are activated and errors are propagated is positively correlated with system uptime. Software rejuvenation relates to techniques counteracting aging (for example, by regularly stopping and restarting the software) in order to remove aging effects and to proactively prevent failures from occurring.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10241255","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62529112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-05DOI: 10.1109/TETC.2023.3300132
{"title":"IEEE Transactions on Emerging Topics in Computing Information for Authors","authors":"","doi":"10.1109/TETC.2023.3300132","DOIUrl":"10.1109/TETC.2023.3300132","url":null,"abstract":"","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10241262","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135804629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a Residue Numbering System (RNS)-based Convolutional Neural Network (CNN) accelerator utilizing a multiplier-free distributed-arithmetic Processing Element (PE) is proposed. A method for maximizing the utilization of the arithmetic hardware resources is presented. It leads to an increase of the system's throughput, by exploiting bit-level sparsity within the weight vectors. The proposed PE design takes advantage of the properties of RNS and Canonical Signed Digit (CSD) encoding to achieve higher energy efficiency and effective processing rate, without requiring any compression mechanism or introducing any approximation. An extensive design space exploration for various parameters (RNS base, PE micro-architecture, encoding) using analytical models as well as experimental results from CNN benchmarks is conducted and the various trade-offs are analyzed. A complete end-to-end RNS accelerator is developed based on the proposed PE. The introduced accelerator is compared to traditional binary and RNS counterparts as well as to other state-of-the-art systems. Implementation results in a 22-nm process show that the proposed PE can lead to $1.85times$ and $1.54times$ more energy-efficient processing compared to binary and conventional RNS, respectively, with a $1.88times$ maximum increase of effective throughput for the employed benchmarks. Compared to a state-of-the-art, all-digital, RNS-based system, the proposed accelerator is $8.87times$ and $1.11times$ more energy- and area-efficient, respectively.
{"title":"A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity","authors":"Vasilis Sakellariou;Vassilis Paliouras;Ioannis Kouretas;Hani Saleh;Thanos Stouraitis","doi":"10.1109/TETC.2023.3301590","DOIUrl":"10.1109/TETC.2023.3301590","url":null,"abstract":"In this work, a Residue Numbering System (RNS)-based Convolutional Neural Network (CNN) accelerator utilizing a multiplier-free distributed-arithmetic Processing Element (PE) is proposed. A method for maximizing the utilization of the arithmetic hardware resources is presented. It leads to an increase of the system's throughput, by exploiting bit-level sparsity within the weight vectors. The proposed PE design takes advantage of the properties of RNS and Canonical Signed Digit (CSD) encoding to achieve higher energy efficiency and effective processing rate, without requiring any compression mechanism or introducing any approximation. An extensive design space exploration for various parameters (RNS base, PE micro-architecture, encoding) using analytical models as well as experimental results from CNN benchmarks is conducted and the various trade-offs are analyzed. A complete end-to-end RNS accelerator is developed based on the proposed PE. The introduced accelerator is compared to traditional binary and RNS counterparts as well as to other state-of-the-art systems. Implementation results in a 22-nm process show that the proposed PE can lead to \u0000<inline-formula><tex-math>$1.85times$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$1.54times$</tex-math></inline-formula>\u0000 more energy-efficient processing compared to binary and conventional RNS, respectively, with a \u0000<inline-formula><tex-math>$1.88times$</tex-math></inline-formula>\u0000 maximum increase of effective throughput for the employed benchmarks. Compared to a state-of-the-art, all-digital, RNS-based system, the proposed accelerator is \u0000<inline-formula><tex-math>$8.87times$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$1.11times$</tex-math></inline-formula>\u0000 more energy- and area-efficient, respectively.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62529168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-01DOI: 10.1109/TETC.2023.3299516
Kleanthis Papachatzopoulos;Vassilis Paliouras
Stochastic computations have attracted significant attention for applications with moderate fixed-point accuracy requirements, as they offer minimal complexity. In these systems, a stochastic bit-stream encodes a data sample. The derived bit-stream is used for processing. The bit-stream length determines the computation latency for bit-serial implementations and hardware complexity for bit-parallel ones. Noise shaping is a feedback technique that moves the quantization noise outside the bandwidth of interest of a signal. This article proposes a technique that builds on noise shaping and reduces the length of the stochastic bit-stream required to achieve a specific Signal-to-Quantization-Noise Ratio (SQNR). The technique is realized by digital units that encode binary samples into stochastic streams, hereafter called as binary-to-stochastic converters. Furthermore, formulas are derived that relate the bit-stream length reduction to the signal bandwidth. First-order and second-order converters that implement the proposed technique are analyzed. Two architectures are introduced, distinguished by placing a stochastic converter either inside or outside of the noise-shaping loop. The proposed bit-stream length reduction is quantitatively compared to conventional binary-to-stochastic converters for the same signal quality level. Departing from conventional approaches, this article employs bit-stream lengths that are not a power of two, and proposes a modified stochastic-to-binary conversion scheme as a part of the proposed binary-to-stochastic converter. Particularly, SQNR gains of 29.8 dB and 42.1 dB are achieved for the first-order and second-order converters compared to the conventional converters for equal-length bit-streams and low signal bandwidth. The investigated converters are designed and synthesized at a 28-nm FDSOI technology for a range of bit widths.
{"title":"Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams","authors":"Kleanthis Papachatzopoulos;Vassilis Paliouras","doi":"10.1109/TETC.2023.3299516","DOIUrl":"10.1109/TETC.2023.3299516","url":null,"abstract":"Stochastic computations have attracted significant attention for applications with moderate fixed-point accuracy requirements, as they offer minimal complexity. In these systems, a stochastic bit-stream encodes a data sample. The derived bit-stream is used for processing. The bit-stream length determines the computation latency for bit-serial implementations and hardware complexity for bit-parallel ones. Noise shaping is a feedback technique that moves the quantization noise outside the bandwidth of interest of a signal. This article proposes a technique that builds on noise shaping and reduces the length of the stochastic bit-stream required to achieve a specific Signal-to-Quantization-Noise Ratio (SQNR). The technique is realized by digital units that encode binary samples into stochastic streams, hereafter called as binary-to-stochastic converters. Furthermore, formulas are derived that relate the bit-stream length reduction to the signal bandwidth. First-order and second-order converters that implement the proposed technique are analyzed. Two architectures are introduced, distinguished by placing a stochastic converter either inside or outside of the noise-shaping loop. The proposed bit-stream length reduction is quantitatively compared to conventional binary-to-stochastic converters for the same signal quality level. Departing from conventional approaches, this article employs bit-stream lengths that are not a power of two, and proposes a modified stochastic-to-binary conversion scheme as a part of the proposed binary-to-stochastic converter. Particularly, SQNR gains of 29.8 dB and 42.1 dB are achieved for the first-order and second-order converters compared to the conventional converters for equal-length bit-streams and low signal bandwidth. The investigated converters are designed and synthesized at a 28-nm FDSOI technology for a range of bit widths.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62529127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-24DOI: 10.1109/TETC.2023.3297066
Jun Zhou;Masaaki Kondo
Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware way to provide the capacity-constrained portable terminals with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of the human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transportation, Internet of Things (IoT), etc. These application domains often manage a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize complex problems where graph-based data is involved. In consideration of the relatively insufficient resource provisioning of the edge devices, in this article, for the first time to our knowledge, we propose a reliable edge-cloud collaboration framework that facilitates the graph primitives based on a lightweight interactive graph processing library (GPL), especially for shortest path search (SPS) operations as the demonstrative example. Two types of different practical cases are also presented to show the typical application scenarios of our graph processing strategy. Experimental evaluations indicate that the acceleration rate of performance can reach 6.87x via graph reduction, and less than 3% and 20% extra latency is required for much better user experiences for navigation and pandemic control, respectively, while the online security measures merely consume about 1% extra time of the overall data transmission. Our framework can efficiently execute the applications with considering of user-friendliness, low-latency response, interactions among edge devices, collaboration between edge and cloud, and privacy protection at an acceptable overhead.
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