Pub Date : 2024-11-15DOI: 10.1109/TETC.2024.3495218
Satanu Maity;Mayank Goel;Manojit Ghose
As we head toward a data-centric era, conventional computing systems become inadequate to meet the evolving demands of the applications. As a result, the near-memory processing (NMP) computing paradigm emerges as a potential alternative framework where regions of an application are offloaded for execution near the memory. Although some interesting research works have been proposed in recent times, none of them have considered placing processing cores jointly on the primary memories and cache memory. Further, they did not consider the data locality offered by the last level cache (LLC) and the estimated execution time of an application region together while designing the offloading strategy. This paper presents a novel hybrid NMP computation framework comprising a traditional multicore processor, NMP-enabled 3D memories and NMP-enabled LLC. The application source code is processed through a compilation framework to identify potential offloadable regions. The paper further proposes a two-stage offloading strategy, CoaT, which determines the execution location of the application regions based on the region’s overall execution time and the data locality offered by the LLC. A comprehensive series of experiments conducted using well-established simulators for large data-intensive applications, provides strong evidence of the efficacy of our approach. The results demonstrate significant reductions in execution time (averaging 60% with a maximum reduction of 64%), un-core energy consumption (averaging 34% with a maximum reduction of 44%), and off-chip data block transfer count (averaging 61% with a maximum reduction of 80%) compared to the state-of-the-art policies. The proposed policy achieves a speedup of 2.6x (on average) and 3.1x (maximum) w.r.t. the conventional execution.
{"title":"CoaT: Compiler-Assisted Two-Stage Offloading Approach for Data-Intensive Applications Under NMP Framework","authors":"Satanu Maity;Mayank Goel;Manojit Ghose","doi":"10.1109/TETC.2024.3495218","DOIUrl":"https://doi.org/10.1109/TETC.2024.3495218","url":null,"abstract":"As we head toward a data-centric era, conventional computing systems become inadequate to meet the evolving demands of the applications. As a result, the near-memory processing (NMP) computing paradigm emerges as a potential alternative framework where regions of an application are offloaded for execution near the memory. Although some interesting research works have been proposed in recent times, none of them have considered placing processing cores jointly on the primary memories and cache memory. Further, they did not consider the data locality offered by the last level cache (LLC) and the estimated execution time of an application region together while designing the offloading strategy. This paper presents a novel hybrid NMP computation framework comprising a traditional multicore processor, NMP-enabled 3D memories and NMP-enabled LLC. The application source code is processed through a compilation framework to identify potential offloadable regions. The paper further proposes a two-stage offloading strategy, <italic>CoaT</i>, which determines the execution location of the application regions based on the region’s overall execution time and the data locality offered by the LLC. A comprehensive series of experiments conducted using well-established simulators for large data-intensive applications, provides strong evidence of the efficacy of our approach. The results demonstrate significant reductions in execution time (averaging 60% with a maximum reduction of 64%), un-core energy consumption (averaging 34% with a maximum reduction of 44%), and off-chip data block transfer count (averaging 61% with a maximum reduction of 80%) compared to the state-of-the-art policies. The proposed policy achieves a speedup of 2.6x (on average) and 3.1x (maximum) w.r.t. the conventional execution.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 3","pages":"753-767"},"PeriodicalIF":5.4,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
False-positive or false-negative detection, and the resulting inappropriate treatments in cancer metastasis cases, have led to numerous fatal instances due to human errors. Traditional cancer diagnoses are often subjectively interpreted through naked-eye observation, which can vary among different medical practitioners. In this research, we propose a novel deep learning-based framework called Intelligent Tumor Analytics (ITA). ITA facilitates on-the-fly assessment of Whole Slide Imaging (WSI) at the histopathological level, primarily utilizing cellular appearance, spatial arrangement, and the relative proximities of various cell types (e.g., tumor cells, immune cells, and other objects of interest) observed within scanned WSI images of tumors. By automatically quantifying relevant indicators and estimating their scores, ITA establishes a standardized evaluation that aligns with widely recognized international tumor grading standards, including the TNM and Nottingham Grading Standards. The objective measurements and assessments offered by ITA provide informative and unbiased insights to users (i.e., pathologists) involved in determining prognosis and treatment plans. The quantified information regarding tumor risk and potential for further metastasis possibilities serves as crucial early knowledge during cancer development.
{"title":"Deep Learning Based Intelligent Tumor Analytics Framework for Quantitative Grading and Analyzing Cancer Metastasis: Case of Lymph Node Breast Cancer","authors":"Tengyue Li;Simon Fong;Yaoyang Wu;Xin Zhang;Qun Song;Huafeng Qin;Sabah Mohammed;Tian Feng;Juntao Gao;Andrea Sciarrone","doi":"10.1109/TETC.2024.3487258","DOIUrl":"https://doi.org/10.1109/TETC.2024.3487258","url":null,"abstract":"False-positive or false-negative detection, and the resulting inappropriate treatments in cancer metastasis cases, have led to numerous fatal instances due to human errors. Traditional cancer diagnoses are often subjectively interpreted through naked-eye observation, which can vary among different medical practitioners. In this research, we propose a novel deep learning-based framework called Intelligent Tumor Analytics (ITA). ITA facilitates on-the-fly assessment of Whole Slide Imaging (WSI) at the histopathological level, primarily utilizing cellular appearance, spatial arrangement, and the relative proximities of various cell types (e.g., tumor cells, immune cells, and other objects of interest) observed within scanned WSI images of tumors. By automatically quantifying relevant indicators and estimating their scores, ITA establishes a standardized evaluation that aligns with widely recognized international tumor grading standards, including the TNM and Nottingham Grading Standards. The objective measurements and assessments offered by ITA provide informative and unbiased insights to users (i.e., pathologists) involved in determining prognosis and treatment plans. The quantified information regarding tumor risk and potential for further metastasis possibilities serves as crucial early knowledge during cancer development.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 1","pages":"90-104"},"PeriodicalIF":5.1,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143570604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The significant data movement between processing units and DRAM adversely affects the performance and energy efficiency of the systems to process bulk bitwise logical operations (BLOs). Researchers have addressed the problem by employing processing-in-memory (PIM) techniques, where bulk bitwise operations are processed in DRAM. Among existing techniques, semi-digital PIMs, which support bulk BLOs by utilizing DRAM core circuits, are one of the most viable designs due to their moderate area penalties. However, our study reveals that state-of-the-art (SOTA) semi-digital PIMs suffer from considerable computation errors caused by process variations. This paper presents PABLO, a novel PIM architecture based on DRAM, to address the challenge. The essential contribution is to develop a generic bitwise unit integrated with the conventional local sense amplifier, enabling bulk BLOs with minimal overhead and modifications of commodity DRAM. As a result, the proposed design allows for simplified bitwise operations while hardly affecting conventional DRAM core operations. We comprehensively demonstrate the enhanced variation tolerance of PABLO compared to SOTA semi-digital PIMs through Monte Carlo simulations. Furthermore, our evaluation results indicate that PABLO achieves a speedup of up to ${sim} 3.97times$ and energy savings of up to ${sim} 3.87times$ compared to existing solutions.
{"title":"PABLO: A Variation-Robust PIM Architecture for Bulk Bitwise Logical Operations in DRAM","authors":"Minh-Son Le;Thanh-Dat Nguyen;Jeong Hoan Park;Seungkyu Choi;Ik-Joon Chang","doi":"10.1109/TETC.2024.3486348","DOIUrl":"https://doi.org/10.1109/TETC.2024.3486348","url":null,"abstract":"The significant data movement between processing units and DRAM adversely affects the performance and energy efficiency of the systems to process bulk bitwise logical operations (BLOs). Researchers have addressed the problem by employing processing-in-memory (PIM) techniques, where bulk bitwise operations are processed in DRAM. Among existing techniques, semi-digital PIMs, which support bulk BLOs by utilizing DRAM core circuits, are one of the most viable designs due to their moderate area penalties. However, our study reveals that state-of-the-art (SOTA) semi-digital PIMs suffer from considerable computation errors caused by process variations. This paper presents PABLO, a novel PIM architecture based on DRAM, to address the challenge. The essential contribution is to develop a generic bitwise unit integrated with the conventional local sense amplifier, enabling bulk BLOs with minimal overhead and modifications of commodity DRAM. As a result, the proposed design allows for simplified bitwise operations while hardly affecting conventional DRAM core operations. We comprehensively demonstrate the enhanced variation tolerance of PABLO compared to SOTA semi-digital PIMs through Monte Carlo simulations. Furthermore, our evaluation results indicate that PABLO achieves a speedup of up to <inline-formula><tex-math>${sim} 3.97times$</tex-math></inline-formula> and energy savings of up to <inline-formula><tex-math>${sim} 3.87times$</tex-math></inline-formula> compared to existing solutions.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 4","pages":"1424-1439"},"PeriodicalIF":5.4,"publicationDate":"2024-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TETC.2024.3482324
Shao-I Chu;Syuan-An Ke
Post-quantum cryptography (PQC) has recently gained intensive attention as the existing public-key cryptosystems are vulnerable to quantum attacks. The ring-learning-with-errors (RLWE)-based PQC is one promising type of the lattice-based schemes. A light variant, called binary RLWE (BRLWE), was developed with applications to Internet-of-Things (IoT) and edge computing. However, deploying the number theoretic transform (NTT) is not beneficial to the parameter settings of the BRLWE-based scheme. This article presents three high-speed architectures of decryption for the BRLWE-based scheme with low area-time complexity. The first one is modified and corrected from the low-latency design of the previous work. The second and third ones utilize the multiplexer-based design for multiplication and innovatively exploit the property of the skew-circulant matrix to reduce the computational latency. Moreover, the third one applies the Karatsuba algorithm to reduce the number of multiplications. However, the results demonstrate that it is not in favor of the design since the multiplication is involved in an integer and a binary number, not both integers. Let the lengths of the secret and public keys be $n$ and $nlog _{2}q$ bits. The synthesized results reveal that the second and third architectures are superior to the lookup table (LUT)-based and linear-feedback shift register (LFSR)-based designs in the previous works in terms of area-time complexity. The FPGA implementation results indicate the second design outperforms the Karatsuba and Toeplitz matrix vector product (TMVP)-initiated accelerators in the literatures by reductions of 62.4% and 51.7% in area-time complexity for the case of $(n, q) = (256, 256)$. As $(n,q)=(512,256)$, the improvements are 44.3% and 28.3%. The third architecture is also superior to these high-speed designs. The proposed implementations are efficient in area-time complexity and are suitable for high-performance applications.
{"title":"Area-Time Efficient Hardware Implementation for Binary Ring-LWE Based Post-Quantum Cryptography","authors":"Shao-I Chu;Syuan-An Ke","doi":"10.1109/TETC.2024.3482324","DOIUrl":"https://doi.org/10.1109/TETC.2024.3482324","url":null,"abstract":"Post-quantum cryptography (PQC) has recently gained intensive attention as the existing public-key cryptosystems are vulnerable to quantum attacks. The ring-learning-with-errors (RLWE)-based PQC is one promising type of the lattice-based schemes. A light variant, called binary RLWE (BRLWE), was developed with applications to Internet-of-Things (IoT) and edge computing. However, deploying the number theoretic transform (NTT) is not beneficial to the parameter settings of the BRLWE-based scheme. This article presents three high-speed architectures of decryption for the BRLWE-based scheme with low area-time complexity. The first one is modified and corrected from the low-latency design of the previous work. The second and third ones utilize the multiplexer-based design for multiplication and innovatively exploit the property of the skew-circulant matrix to reduce the computational latency. Moreover, the third one applies the Karatsuba algorithm to reduce the number of multiplications. However, the results demonstrate that it is not in favor of the design since the multiplication is involved in an integer and a binary number, not both integers. Let the lengths of the secret and public keys be <inline-formula><tex-math>$n$</tex-math></inline-formula> and <inline-formula><tex-math>$nlog _{2}q$</tex-math></inline-formula> bits. The synthesized results reveal that the second and third architectures are superior to the lookup table (LUT)-based and linear-feedback shift register (LFSR)-based designs in the previous works in terms of area-time complexity. The FPGA implementation results indicate the second design outperforms the Karatsuba and Toeplitz matrix vector product (TMVP)-initiated accelerators in the literatures by reductions of 62.4% and 51.7% in area-time complexity for the case of <inline-formula><tex-math>$(n, q) = (256, 256)$</tex-math></inline-formula>. As <inline-formula><tex-math>$(n,q)=(512,256)$</tex-math></inline-formula>, the improvements are 44.3% and 28.3%. The third architecture is also superior to these high-speed designs. The proposed implementations are efficient in area-time complexity and are suitable for high-performance applications.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 3","pages":"724-738"},"PeriodicalIF":5.4,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1109/TETC.2024.3481997
Teresa Arauz;José M. Maestre;Paula Chanfreut;Daniel E. Quevedo;Eduardo F. Camacho
Software rejuvenation is a cyberdefense mechanism that periodically resets the control software of a system to limit the impact of cyberattacks. We propose open and closed-loop tree-based model predictive controllers to explicitly account for the software refresh events and the cyberattacks. The benefits of the proposed methods are illustrated using a simulated microgrid as a case study and randomized tests with different types of attacks.
{"title":"Open and Closed-Loop Predictive Control Strategies for Software Rejuvenation","authors":"Teresa Arauz;José M. Maestre;Paula Chanfreut;Daniel E. Quevedo;Eduardo F. Camacho","doi":"10.1109/TETC.2024.3481997","DOIUrl":"https://doi.org/10.1109/TETC.2024.3481997","url":null,"abstract":"Software rejuvenation is a cyberdefense mechanism that periodically resets the control software of a system to limit the impact of cyberattacks. We propose open and closed-loop tree-based model predictive controllers to explicitly account for the software refresh events and the cyberattacks. The benefits of the proposed methods are illustrated using a simulated microgrid as a case study and randomized tests with different types of attacks.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 2","pages":"330-340"},"PeriodicalIF":5.1,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144323168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the tolerance of Triplet Networks (TNs) with a focus on faults in the training process. For compatibility with the existing literature. So-called stuck-at faults of a functional nature are considered for the operation of the neurons and activation function. While TNs are shown to be generally robust against such faults in the anchor and positive subnetworks, the presented analysis reveals a significant vulnerability in the negative subnetwork, in which stuck-at faults can lead to false convergence and training failures. An in-depth treatment is provided to show the incorrect convergence of training in the presence of stuck-at faults, highlighting the behavior of the network with faulty neurons. Extensive simulations are presented to evaluate the impact of these faults and propose two innovative fault-tolerant methods: the regularization of the anchor outputs and the modified margin. Simulation shows that false convergence can be very efficiently avoided by utilizing the proposed techniques, and thus the overall accuracy loss of the TN is negligible. These findings contribute to the understanding of fault tolerance in emerging neural networks such as TNs and offer practical solutions for enhancing their robustness against faults.
{"title":"Fault Tolerance in Triplet Network Training: Analysis, Evaluation and Protection Methods","authors":"Ziheng Wang;Farzad Niknia;Shanshan Liu;Pedro Reviriego;Ahmed Louri;Fabrizio Lombardi","doi":"10.1109/TETC.2024.3481962","DOIUrl":"https://doi.org/10.1109/TETC.2024.3481962","url":null,"abstract":"This paper investigates the tolerance of Triplet Networks (TNs) with a focus on faults in the training process. For compatibility with the existing literature. So-called stuck-at faults of a functional nature are considered for the operation of the neurons and activation function. While TNs are shown to be generally robust against such faults in the anchor and positive subnetworks, the presented analysis reveals a significant vulnerability in the negative subnetwork, in which stuck-at faults can lead to false convergence and training failures. An in-depth treatment is provided to show the incorrect convergence of training in the presence of stuck-at faults, highlighting the behavior of the network with faulty neurons. Extensive simulations are presented to evaluate the impact of these faults and propose two innovative fault-tolerant methods: the regularization of the anchor outputs and the modified margin. Simulation shows that false convergence can be very efficiently avoided by utilizing the proposed techniques, and thus the overall accuracy loss of the TN is negligible. These findings contribute to the understanding of fault tolerance in emerging neural networks such as TNs and offer practical solutions for enhancing their robustness against faults.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 3","pages":"714-723"},"PeriodicalIF":5.4,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1109/TETC.2024.3480700
Sepehr Tabrizchi;Rebati Gaire;Mehrdad Morsali;Maximilian Liehr;Nathaniel C. Cady;Shaahin Angizi;Arman Roohi
Artificial-intelligence-powered edge devices are inspiring interest in always-on, intelligent, and self-powered visual perception systems. Due to the high energy cost of converting raw data and the limited computing and energy resources available, designing energy-efficient and low bandwidth CMOS vision sensors is vital as these emerging systems require continuous sensing and instant processing. This paper proposes a low-power integrated sensing and computing engine, namely APRIS, including a novel software/hardware co-design technique. This method provides a highly parallel analog multiplication and accumulation-in-pixel scheme, which realizes low-precision quantized weight neural networks to mitigate the overhead of analog-to-digital converters and analog buffers. Moreover, in order to reduce the size and power consumption, we propose the implementation of an approximate ADC in the readout circuit. Our system utilizes eight memory banks to increase computation parallelism, which has a dramatic effect on its speed and efficiency. Moreover, the proposed structure supports a zero-skipping scheme to reduce power consumption further. Our circuit-to-application co-simulation results demonstrate a comparable accuracy for our platform to the full-precision baseline on various object classification tasks while reaching an efficiency of $sim$3.48 TOp/s/W.
{"title":"APRIS: Approximate Processing ReRAM In-Sensor Architecture Enabling Artificial-Intelligence-Powered Edge","authors":"Sepehr Tabrizchi;Rebati Gaire;Mehrdad Morsali;Maximilian Liehr;Nathaniel C. Cady;Shaahin Angizi;Arman Roohi","doi":"10.1109/TETC.2024.3480700","DOIUrl":"https://doi.org/10.1109/TETC.2024.3480700","url":null,"abstract":"Artificial-intelligence-powered edge devices are inspiring interest in always-on, intelligent, and self-powered visual perception systems. Due to the high energy cost of converting raw data and the limited computing and energy resources available, designing energy-efficient and low bandwidth CMOS vision sensors is vital as these emerging systems require continuous sensing and instant processing. This paper proposes a low-power integrated sensing and computing engine, namely <monospace>APRIS</monospace>, including a novel software/hardware co-design technique. This method provides a highly parallel analog multiplication and accumulation-in-pixel scheme, which realizes low-precision quantized weight neural networks to mitigate the overhead of analog-to-digital converters and analog buffers. Moreover, in order to reduce the size and power consumption, we propose the implementation of an approximate ADC in the readout circuit. Our system utilizes eight memory banks to increase computation parallelism, which has a dramatic effect on its speed and efficiency. Moreover, the proposed structure supports a zero-skipping scheme to reduce power consumption further. Our circuit-to-application co-simulation results demonstrate a comparable accuracy for our platform to the full-precision baseline on various object classification tasks while reaching an efficiency of <inline-formula><tex-math>$sim$</tex-math></inline-formula>3.48 TOp/s/W.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 4","pages":"1356-1366"},"PeriodicalIF":5.4,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1109/TETC.2024.3480132
Yunfei He;Yang Wu;Lishan Huang;Zhenwan Peng;Fei Yang;Yiwen Zhang;Victor S Sheng
Empowered by their remarkable advantages, graph neural networks (GNN) serve as potent tools for embedding graph-structured data and finding applications across various domains. Particularly, a prevalent assumption in most GNNs is the reliability of the underlying graph structure. This assumption, often implicit, can inadvertently lead to the propagation of misleading information through structures like false links. In response to this challenge, numerous methods for graph structure learning (GSL) have been developed. Among these methods, one popular approach is to construct a simple and intuitive K-nearest neighbor (KNN) graph as a sample to infer true graph structure. However, KNN graphs that follow the single-point distribution can easily mislead the true graph structure estimation. The primary reason is that, from a statistical perspective, the KNN graph, as a sample, follows a single-point distribution, whereas the true graph structure, as the population, as a whole mostly follows a long-tail distribution. In theory, the sample and the population should share the same distribution; otherwise, accurately inferring the true graph structure becomes challenging. To address this problem, this paper proposes an Adaptive Graph Structure Estimation with Long-Tail Distributed Implicit Graph, referred to as AGSEI. AGSEI comprises three main components: long-tail implicit graph construction, explicit graph structure estimation, and joint optimization. The first component relies on a multi-layer graph convolutional network to learn low-order to high-order node representations, compute node similarity, and construct several corresponding long-tail implicit graphs. Since the original imperfect graph structure can mislead GNNs into propagating false information, it reduces the reliability of the long-tail implicit graphs. AGSEI attempts to limit the aggregation of irrelevant information by introducing the Hilbert-Schmidt independence criterion. That is, maximizing the dependence between the predicted label and ground truth. With this strategy, AGSEI can learn node features dependent on labels to facilitate the construction of reliable long-tail implicit graphs, and then provide adaptive multi-view graph structure information to support subsequent GSL. In the second component, the graph structure is estimated using the stochastic block model (SBM) with the Expectation-Maximization algorithm. Considering that it is difficult for a single GSL to approach the true graph structure, the third part considers the joint optimization of the long-tail implicit graph construction and the explicit graph structure estimation. This involves optimizing the two parts alternately until the model converges. We conducted multiple experiments on five public datasets, including tasks such as classification and clustering. These experiments not only demonstrated the performance of AGSEI but also confirmed that the graph structures it estimates align with the long-tail distributio
{"title":"AGSEI: Adaptive Graph Structure Estimation With Long-Tail Distributed Implicit Graphs","authors":"Yunfei He;Yang Wu;Lishan Huang;Zhenwan Peng;Fei Yang;Yiwen Zhang;Victor S Sheng","doi":"10.1109/TETC.2024.3480132","DOIUrl":"https://doi.org/10.1109/TETC.2024.3480132","url":null,"abstract":"Empowered by their remarkable advantages, graph neural networks (GNN) serve as potent tools for embedding graph-structured data and finding applications across various domains. Particularly, a prevalent assumption in most GNNs is the reliability of the underlying graph structure. This assumption, often implicit, can inadvertently lead to the propagation of misleading information through structures like false links. In response to this challenge, numerous methods for graph structure learning (GSL) have been developed. Among these methods, one popular approach is to construct a simple and intuitive K-nearest neighbor (KNN) graph as a sample to infer true graph structure. However, KNN graphs that follow the single-point distribution can easily mislead the true graph structure estimation. The primary reason is that, from a statistical perspective, the KNN graph, as a sample, follows a single-point distribution, whereas the true graph structure, as the population, as a whole mostly follows a long-tail distribution. In theory, the sample and the population should share the same distribution; otherwise, accurately inferring the true graph structure becomes challenging. To address this problem, this paper proposes an Adaptive Graph Structure Estimation with Long-Tail Distributed Implicit Graph, referred to as AGSEI. AGSEI comprises three main components: long-tail implicit graph construction, explicit graph structure estimation, and joint optimization. The first component relies on a multi-layer graph convolutional network to learn low-order to high-order node representations, compute node similarity, and construct several corresponding long-tail implicit graphs. Since the original imperfect graph structure can mislead GNNs into propagating false information, it reduces the reliability of the long-tail implicit graphs. AGSEI attempts to limit the aggregation of irrelevant information by introducing the Hilbert-Schmidt independence criterion. That is, maximizing the dependence between the predicted label and ground truth. With this strategy, AGSEI can learn node features dependent on labels to facilitate the construction of reliable long-tail implicit graphs, and then provide adaptive multi-view graph structure information to support subsequent GSL. In the second component, the graph structure is estimated using the stochastic block model (SBM) with the Expectation-Maximization algorithm. Considering that it is difficult for a single GSL to approach the true graph structure, the third part considers the joint optimization of the long-tail implicit graph construction and the explicit graph structure estimation. This involves optimizing the two parts alternately until the model converges. We conducted multiple experiments on five public datasets, including tasks such as classification and clustering. These experiments not only demonstrated the performance of AGSEI but also confirmed that the graph structures it estimates align with the long-tail distributio","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 3","pages":"698-713"},"PeriodicalIF":5.4,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145043855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1109/TETC.2024.3481035
Tien Nguyen;Aengus Daly;Sergi Gomez-Quintana;Feargal O'Sullivan;Andriy Temko;Emanuel Popovici
Detecting seizures in neonates requires continuous electroencephalography (EEG) monitoring, a costly process that demands trained experts. Although recent advancements in machine learning offer promising solutions for automated seizure detection, the opaque nature of these algorithms poses significant challenges to their adoption in healthcare settings. A prior study demonstrated that integrating machine learning with sonification—an interpretation method that converts bio-signals into sound—can mitigate the black-box problem while enhancing seizure detection performance. This AI-assisted sonification algorithm can provide a valuable complementary tool in seizure monitoring besides the traditional visualization method. A low-power and affordable implementation of the algorithm is presented in this study using a microcontroller. To improve its practicality, we also introduce a real-time design that allows the sonification algorithm to function in parallel with data acquisition. The system consumes 12 mW in average, making it suitable for a battery-powered device.
{"title":"Low-Power Real-Time Seizure Monitoring Using AI-Assisted Sonification of Neonatal EEG","authors":"Tien Nguyen;Aengus Daly;Sergi Gomez-Quintana;Feargal O'Sullivan;Andriy Temko;Emanuel Popovici","doi":"10.1109/TETC.2024.3481035","DOIUrl":"https://doi.org/10.1109/TETC.2024.3481035","url":null,"abstract":"Detecting seizures in neonates requires continuous electroencephalography (EEG) monitoring, a costly process that demands trained experts. Although recent advancements in machine learning offer promising solutions for automated seizure detection, the opaque nature of these algorithms poses significant challenges to their adoption in healthcare settings. A prior study demonstrated that integrating machine learning with sonification—an interpretation method that converts bio-signals into sound—can mitigate the black-box problem while enhancing seizure detection performance. This AI-assisted sonification algorithm can provide a valuable complementary tool in seizure monitoring besides the traditional visualization method. A low-power and affordable implementation of the algorithm is presented in this study using a microcontroller. To improve its practicality, we also introduce a real-time design that allows the sonification algorithm to function in parallel with data acquisition. The system consumes 12 mW in average, making it suitable for a battery-powered device.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 1","pages":"80-89"},"PeriodicalIF":5.1,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10726674","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143570700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-17DOI: 10.1109/TETC.2024.3479202
Haixu Yu;Xudong Zhao
In quantum information science, one of the ambitious goals is to look for an efficient technique for classifying multiple quantum states. To solve the binary classification problem for multiple quantum states characterized by parameters, we propose a deep reinforcement learning with curriculum design (DRL-CD) method. In DRL-CD, a series of tasks are created, using state parameter intervals and fidelity thresholds, to form a curriculum. Then, a quantum state binary classifier can be obtained by utilizing deep reinforcement learning (DRL) to solve each task in the designed curriculum. In particular, we construct a training set by sampling the state parameter interval corresponding to each task, and each task is accomplished by learning the control strategies capable of steering the sampled quantum states to the target state. In addition, a knowledge review method is proposed to prevent DRL from forgetting the learned classification knowledge. Some state classification problems of the spin-1/2 quantum system and $Lambda$-type atomic system are solved by the proposed DRL-CD method, and comparison experiments with deep Q-network (DQN) and stochastic gradient descent (SGD) show the better classification performance of DRL-CD.
{"title":"Deep Reinforcement Learning With Curriculum Design for Quantum State Classification","authors":"Haixu Yu;Xudong Zhao","doi":"10.1109/TETC.2024.3479202","DOIUrl":"https://doi.org/10.1109/TETC.2024.3479202","url":null,"abstract":"In quantum information science, one of the ambitious goals is to look for an efficient technique for classifying multiple quantum states. To solve the binary classification problem for multiple quantum states characterized by parameters, we propose a deep reinforcement learning with curriculum design (DRL-CD) method. In DRL-CD, a series of tasks are created, using state parameter intervals and fidelity thresholds, to form a curriculum. Then, a quantum state binary classifier can be obtained by utilizing deep reinforcement learning (DRL) to solve each task in the designed curriculum. In particular, we construct a training set by sampling the state parameter interval corresponding to each task, and each task is accomplished by learning the control strategies capable of steering the sampled quantum states to the target state. In addition, a knowledge review method is proposed to prevent DRL from forgetting the learned classification knowledge. Some state classification problems of the spin-1/2 quantum system and <inline-formula><tex-math>$Lambda$</tex-math></inline-formula>-type atomic system are solved by the proposed DRL-CD method, and comparison experiments with deep Q-network (DQN) and stochastic gradient descent (SGD) show the better classification performance of DRL-CD.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"13 3","pages":"654-668"},"PeriodicalIF":5.4,"publicationDate":"2024-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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