Pub Date : 2023-07-24DOI: 10.1109/TETC.2023.3296772
Mónica Sánchez de Francisco;Paloma Díaz;Teresa Onorati;Álvaro Monteron;Ignacio Aedo
Social and ubiquitous computing opens up many opportunities to engage citizens in activities that benefit their communities. Technology is ready and available, but there are still open issues concerning how to engage people in activities that are not extrinsically rewarding or whose impact is not immediately perceived. In this paper, we explore the role that situated motivational affordances can play in encouraging citizens in one of such activities, early warning. With this purpose, we designed and implemented a gamified app, IWarn that was iteratively designed following an action-research process to align the needs and capabilities of two types of stakeholders: emergency managers and citizens. The situated motivational affordances framework was used to lead the evaluation considering the motivational affordances enabled by the app and the situation in which it was used. The IWarn app was evaluated in an in-the-wild deployment where 4 emergency workers and 17 citizens took part in a real exercise for one week. Our results suggest that the gamified elements helped to improve intrinsic and extrinsic motivation and user engagement. This work contributes to the social computing domain by illustrating a use case where carefully designed gamification can help in engaging citizens in participatory processes
{"title":"Designing Mobile Technologies to Encourage Civic Engagement: The Role of Situated Motivational Affordances","authors":"Mónica Sánchez de Francisco;Paloma Díaz;Teresa Onorati;Álvaro Monteron;Ignacio Aedo","doi":"10.1109/TETC.2023.3296772","DOIUrl":"10.1109/TETC.2023.3296772","url":null,"abstract":"Social and ubiquitous computing opens up many opportunities to engage citizens in activities that benefit their communities. Technology is ready and available, but there are still open issues concerning how to engage people in activities that are not extrinsically rewarding or whose impact is not immediately perceived. In this paper, we explore the role that situated motivational affordances can play in encouraging citizens in one of such activities, early warning. With this purpose, we designed and implemented a gamified app, IWarn that was iteratively designed following an action-research process to align the needs and capabilities of two types of stakeholders: emergency managers and citizens. The situated motivational affordances framework was used to lead the evaluation considering the motivational affordances enabled by the app and the situation in which it was used. The IWarn app was evaluated in an in-the-wild deployment where 4 emergency workers and 17 citizens took part in a real exercise for one week. Our results suggest that the gamified elements helped to improve intrinsic and extrinsic motivation and user engagement. This work contributes to the social computing domain by illustrating a use case where carefully designed gamification can help in engaging citizens in participatory processes","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.1,"publicationDate":"2023-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10192506","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62529024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1109/TETC.2023.3296016
Jim Plusquellic;Eirini Eleni Tsiropoulou;Cyrus Minwalla
Authentication between IoT devices is important for maintaining security, trust and data integrity in an edge device ecosystem. The low-power, reduced computing capacity of the IoT device makes public-private, certificate-based forms of authentication impractical, while other lighter-weight, symmetric cryptography-based approaches, such as message authentication codes, are easy to spoof in unsupervised environments where adversaries have direct physical access to the device. Such environments are better served by security primitives rooted in the hardware with capabilities exceeding those available in cryptography-only frameworks. A key foundational hardware security primitive is the physical unclonable function or PUF. PUFs are well known for removing the need to store secrets in secure non-volatile memories, and for providing very large sets of authentication credentials. In this article, we describe two PUF-based mutual authentication protocols rooted in the entropy provided by a strong PUF. The security properties of the authentication protocols, called COBRA and PARCE, are evaluated in hardware experiments on SoC-based FPGAs, and under extended industrial-standard operating conditions. A codesign-based system architecture is presented in which the SiRF PUF and core authentication functions are implemented in the programmable logic as a secure enclave, while network and database operations are implemented in software on an embedded microprocessor.
{"title":"Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF","authors":"Jim Plusquellic;Eirini Eleni Tsiropoulou;Cyrus Minwalla","doi":"10.1109/TETC.2023.3296016","DOIUrl":"10.1109/TETC.2023.3296016","url":null,"abstract":"Authentication between IoT devices is important for maintaining security, trust and data integrity in an edge device ecosystem. The low-power, reduced computing capacity of the IoT device makes public-private, certificate-based forms of authentication impractical, while other lighter-weight, symmetric cryptography-based approaches, such as message authentication codes, are easy to spoof in unsupervised environments where adversaries have direct physical access to the device. Such environments are better served by security primitives rooted in the hardware with capabilities exceeding those available in cryptography-only frameworks. A key foundational hardware security primitive is the physical unclonable function or PUF. PUFs are well known for removing the need to store secrets in secure non-volatile memories, and for providing very large sets of authentication credentials. In this article, we describe two PUF-based mutual authentication protocols rooted in the entropy provided by a strong PUF. The security properties of the authentication protocols, called COBRA and PARCE, are evaluated in hardware experiments on SoC-based FPGAs, and under extended industrial-standard operating conditions. A codesign-based system architecture is presented in which the SiRF PUF and core authentication functions are implemented in the programmable logic as a secure enclave, while network and database operations are implemented in software on an embedded microprocessor.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62529012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-18DOI: 10.1109/TETC.2023.3294986
Nicolas Brisebarre;Jean-Michel Muller;Joris Picot
Assume we use a binary floating-point arithmetic and that $operatorname{RN}$ is the round-to-nearest function. Also assume that $c$ is a constant or a real function of one or more variables, and that we have at our disposal a correctly rounded implementation of $c$ , say $hat{c}= operatorname{RN}(c)$ . For evaluating $x cdot c$ (resp. $ x / c$ or $c / x$ ), the natural way is to replace it by $operatorname{RN}(x cdot hat{c})$ (resp. $ operatorname{RN}(x / hat{c})$ or $operatorname{RN}(hat{c}/ x)$ ), that is, to call function $hat{c}$ and to perform a floating-point multiplication or division. This can be generalized to the approximation of $n/d$ by $operatorname{RN}(hat{n}/hat{d})$ and the approximation of $n cdot d$ by $operatorname{RN}(hat{n} cdot hat{d})$ , where $hat{n} = operatorname{RN}(n)$ and $hat{d} = operatorname{RN}(d)$ , and $n$ and $d$ are functions for which we have at our disposal a correctly rounded implementation. We discuss tight error bounds in ulps of such approximations. From our results, one immediately obtains tight error bounds for calculations such as $mathtt {x * pi}$ , $mathtt {ln(2)/x}$ , $mathtt {x/(y+z)}$ , $mathtt {(x+y)*z}$ , $mathtt {x/sqrt(y)}$ , $mathtt {sqrt(x)/{y}}$ , $mathtt {(x+y)(z+t)}$ , $mathtt {(x+y)/(z+t)}$ , $mathtt {(x+y)/(zt)}$ , etc. in floating-point arithmetic.
{"title":"Error in Ulps of the Multiplication or Division by a Correctly-Rounded Function or Constant in Binary Floating-Point Arithmetic","authors":"Nicolas Brisebarre;Jean-Michel Muller;Joris Picot","doi":"10.1109/TETC.2023.3294986","DOIUrl":"10.1109/TETC.2023.3294986","url":null,"abstract":"Assume we use a binary floating-point arithmetic and that \u0000<inline-formula><tex-math>$operatorname{RN}$</tex-math></inline-formula>\u0000 is the round-to-nearest function. Also assume that \u0000<inline-formula><tex-math>$c$</tex-math></inline-formula>\u0000 is a constant or a real function of one or more variables, and that we have at our disposal a correctly rounded implementation of \u0000<inline-formula><tex-math>$c$</tex-math></inline-formula>\u0000, say \u0000<inline-formula><tex-math>$hat{c}= operatorname{RN}(c)$</tex-math></inline-formula>\u0000. For evaluating \u0000<inline-formula><tex-math>$x cdot c$</tex-math></inline-formula>\u0000 (resp. \u0000<inline-formula><tex-math>$ x / c$</tex-math></inline-formula>\u0000 or \u0000<inline-formula><tex-math>$c / x$</tex-math></inline-formula>\u0000), the natural way is to replace it by \u0000<inline-formula><tex-math>$operatorname{RN}(x cdot hat{c})$</tex-math></inline-formula>\u0000 (resp. \u0000<inline-formula><tex-math>$ operatorname{RN}(x / hat{c})$</tex-math></inline-formula>\u0000 or \u0000<inline-formula><tex-math>$operatorname{RN}(hat{c}/ x)$</tex-math></inline-formula>\u0000), that is, to call function \u0000<inline-formula><tex-math>$hat{c}$</tex-math></inline-formula>\u0000 and to perform a floating-point multiplication or division. This can be generalized to the approximation of \u0000<inline-formula><tex-math>$n/d$</tex-math></inline-formula>\u0000 by \u0000<inline-formula><tex-math>$operatorname{RN}(hat{n}/hat{d})$</tex-math></inline-formula>\u0000 and the approximation of \u0000<inline-formula><tex-math>$n cdot d$</tex-math></inline-formula>\u0000 by \u0000<inline-formula><tex-math>$operatorname{RN}(hat{n} cdot hat{d})$</tex-math></inline-formula>\u0000, where \u0000<inline-formula><tex-math>$hat{n} = operatorname{RN}(n)$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$hat{d} = operatorname{RN}(d)$</tex-math></inline-formula>\u0000, and \u0000<inline-formula><tex-math>$n$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$d$</tex-math></inline-formula>\u0000 are functions for which we have at our disposal a correctly rounded implementation. We discuss tight error bounds in ulps of such approximations. From our results, one immediately obtains tight error bounds for calculations such as \u0000<inline-formula><tex-math>$mathtt {x * pi}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {ln(2)/x}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {x/(y+z)}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {(x+y)*z}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {x/sqrt(y)}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {sqrt(x)/{y}}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {(x+y)(z+t)}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {(x+y)/(z+t)}$</tex-math></inline-formula>\u0000, \u0000<inline-formula><tex-math>$mathtt {(x+y)/(zt)}$</tex-math></inline-formula>\u0000, etc. in floating-point arithmetic.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In-memory computing (IMC) has been proposed to overcome the von Neumann bottleneck in data-intensive applications. However, existing IMC solutions could not achieve both high parallelism and high flexibility, which limits their application in more general scenarios: As a highly parallel IMC design, the functionality of a MAC crossbar is limited to the matrix-vector multiplication; Another IMC method of logic-in-memory (LiM) is more flexible in supporting different logic functions, but has low parallelism. To improve the LiM parallelism, we are inspired by investigating how the single-instruction, multiple-data (SIMD) instruction set in conventional CPU could potentially help to expand the number of LiM operands in one cycle. The biggest challenge is the inefficiency in handling non-continuous data in parallel due to the SIMD limitation of (i) continuous address, (ii) limited cache bandwidth, and (iii) large full-resolution parallel computing overheads. This article presents GRAPHIC, the first reported in-memory SIMD architecture that solves the parallelism and irregular data access challenges in applying SIMD to LiM. GRAPHIC exploits content-addressable memory (CAM) and row-wise-accessible SRAM. By providing the in-situ, full-parallelism, and low-overhead operations of address search, cache read-compute-and-update, GRAPHIC accomplishes high-efficiency gather and aggregation with high parallelism, high energy efficiency, low latency, and low area overheads. Experiments in both continuous data access and irregular data pattern applications show an average speedup of 5x over iso-area AVX-like LiM, and 3-5x over the emerging CAM-based accelerators of CAPE and GaaS-X in advanced techniques.
{"title":"GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility","authors":"Yiming Chen;Mingyen Lee;Guohao Dai;Mufeng Zhou;Nagadastagiri Challapalle;Tianyi Wang;Yao Yu;Yongpan Liu;Yu Wang;Huazhong Yang;Vijaykrishnan Narayanan;Xueqing Li","doi":"10.1109/TETC.2023.3290683","DOIUrl":"10.1109/TETC.2023.3290683","url":null,"abstract":"In-memory computing (IMC) has been proposed to overcome the von Neumann bottleneck in data-intensive applications. However, existing IMC solutions could not achieve both high parallelism and high flexibility, which limits their application in more general scenarios: As a highly parallel IMC design, the functionality of a MAC crossbar is limited to the matrix-vector multiplication; Another IMC method of logic-in-memory (LiM) is more flexible in supporting different logic functions, but has low parallelism. To improve the LiM parallelism, we are inspired by investigating how the single-instruction, multiple-data (SIMD) instruction set in conventional CPU could potentially help to expand the number of LiM operands in one cycle. The biggest challenge is the inefficiency in handling non-continuous data in parallel due to the SIMD limitation of (i) continuous address, (ii) limited cache bandwidth, and (iii) large full-resolution parallel computing overheads. This article presents GRAPHIC, the first reported in-memory SIMD architecture that solves the parallelism and irregular data access challenges in applying SIMD to LiM. GRAPHIC exploits content-addressable memory (CAM) and row-wise-accessible SRAM. By providing the in-situ, full-parallelism, and low-overhead operations of address search, cache read-compute-and-update, GRAPHIC accomplishes high-efficiency gather and aggregation with high parallelism, high energy efficiency, low latency, and low area overheads. Experiments in both continuous data access and irregular data pattern applications show an average speedup of 5x over iso-area AVX-like LiM, and 3-5x over the emerging CAM-based accelerators of CAPE and GaaS-X in advanced techniques.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-13DOI: 10.1109/TETC.2023.3293477
Xiaozhou Lu;Sunghwan Kim
As maintaining a proper balanced GC content is crucial for minimizing errors in DNA storage, constructing GC-balanced DNA codes has become an important research topic. In this article, we propose a novel code construction method based on the weight distribution of the data, which enables us to construct GC-balanced DNA codes. Additionally, we introduce a specific encoding process for both balanced and imbalanced data parts. One of the key differences between the proposed codes and existing codes is that the parity lengths of the proposed codes are variable depending on the data parts, while the parity lengths of existing codes remain fixed. To evaluate the effectiveness of the proposed codes, we compare their average parity lengths to those of existing codes. Our results demonstrate that the proposed codes have significantly shorter average parity lengths for DNA sequences with appropriate GC contents.
保持适当平衡的 GC 含量对于减少 DNA 存储中的错误至关重要，因此构建 GC 平衡 DNA 代码已成为一个重要的研究课题。在本文中，我们提出了一种基于数据权重分布的新型代码构建方法，它使我们能够构建 GC 平衡 DNA 代码。此外，我们还为平衡和不平衡数据部分引入了特定的编码过程。拟议代码与现有代码的主要区别之一是，拟议代码的奇偶校验长度可根据数据部分的不同而变化，而现有代码的奇偶校验长度则保持固定。为了评估拟议编码的有效性，我们将其平均奇偶校验长度与现有编码的平均奇偶校验长度进行了比较。结果表明，对于具有适当 GC 含量的 DNA 序列，建议的编码具有明显较短的平均奇偶校验长度。
{"title":"New Construction of Balanced Codes Based on Weights of Data for DNA Storage","authors":"Xiaozhou Lu;Sunghwan Kim","doi":"10.1109/TETC.2023.3293477","DOIUrl":"10.1109/TETC.2023.3293477","url":null,"abstract":"As maintaining a proper balanced GC content is crucial for minimizing errors in DNA storage, constructing GC-balanced DNA codes has become an important research topic. In this article, we propose a novel code construction method based on the weight distribution of the data, which enables us to construct GC-balanced DNA codes. Additionally, we introduce a specific encoding process for both balanced and imbalanced data parts. One of the key differences between the proposed codes and existing codes is that the parity lengths of the proposed codes are variable depending on the data parts, while the parity lengths of existing codes remain fixed. To evaluate the effectiveness of the proposed codes, we compare their average parity lengths to those of existing codes. Our results demonstrate that the proposed codes have significantly shorter average parity lengths for DNA sequences with appropriate GC contents.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-12DOI: 10.1109/TETC.2023.3293426
Khakim Akhunov;Kasım Sinan Yıldırım
There is an emerging requirement for performing data-intensive parallel computations, e.g., machine-learning inference, locally on batteryless sensors. These devices are resource-constrained and operate intermittently due to the irregular energy availability in the environment. Intermittent execution might lead to several side effects that might prevent the correct execution of computational tasks. Even though recent studies proposed methods to cope with these side effects and execute these tasks correctly, they overlooked the efficient intermittent execution of parallelizable data-intensive machine-learning tasks. In this article, we present PiMCo—a novel programmable CRAM-based in-memory coprocessor that exploits the Processing In-Memory (PIM) paradigm and facilitates the power-failure resilient execution of parallelizable computational loads. Contrary to existing PIM solutions for intermittent computing, PiMCo promotes better programmability to accelerate a variety of parallelizable tasks. Our performance evaluation demonstrates that PiMCo improves the performance of existing low-power accelerators for intermittent computing by up to 8× and energy efficiency by up to 150×.
{"title":"CRAM-Based Acceleration for Intermittent Computing of Parallelizable Tasks","authors":"Khakim Akhunov;Kasım Sinan Yıldırım","doi":"10.1109/TETC.2023.3293426","DOIUrl":"10.1109/TETC.2023.3293426","url":null,"abstract":"There is an emerging requirement for performing data-intensive parallel computations, e.g., machine-learning inference, locally on batteryless sensors. These devices are resource-constrained and operate intermittently due to the irregular energy availability in the environment. Intermittent execution might lead to several side effects that might prevent the correct execution of computational tasks. Even though recent studies proposed methods to cope with these side effects and execute these tasks correctly, they overlooked the efficient intermittent execution of parallelizable data-intensive machine-learning tasks. In this article, we present PiMCo—a novel programmable CRAM-based in-memory coprocessor that exploits the Processing In-Memory (PIM) paradigm and facilitates the power-failure resilient execution of parallelizable computational loads. Contrary to existing PIM solutions for intermittent computing, PiMCo promotes better programmability to accelerate a variety of parallelizable tasks. Our performance evaluation demonstrates that PiMCo improves the performance of existing low-power accelerators for intermittent computing by up to 8× and energy efficiency by up to 150×.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-12DOI: 10.1109/TETC.2023.3293140
Purab Ranjan Sutradhar;Sathwika Bavikadi;Sai Manoj Pudukotai Dinakarrao;Mark A. Indovina;Amlan Ganguly
Memory-centric computing systems have demonstrated superior performance and efficiency in memory-intensive applications compared to state-of-the-art CPUs and GPUs. 3-D stacked DRAM architectures unlock higher I/O data bandwidth than the traditional 2-D memory architecture and therefore are better suited for incorporating memory-centric processors. However, merely integrating high-precision ALUs in the 3-D stacked memory does not ensure an optimized design since such a design can only achieve a limited utilization of the internal bandwidth of a memory chip and limited operational parallelization. To address this, we propose 3DL-PIM, a 3-D stacked memory-based Processing in Memory (PIM) architecture that locates a plurality of Look-up Table (LUT)-based low-footprint Processing Elements (PE) within the memory banks in order to achieve high parallel computing performance by maximizing data-bandwidth utilization. Instead of relying on the traditional logic-based ALUs, the PEs are formed by clustering a group of programmable LUTs and therefore can be programmed on-the-fly to perform various logic/arithmetic operations. Our simulations show that 3DL-PIM can achieve respectively up to 2.6× higher processing performance at 2.65× higher area efficiency compared to a state-of-the-art 3-D stacked memory-based accelerator.
与最先进的 CPU 和 GPU 相比，以内存为中心的计算系统在内存密集型应用中表现出卓越的性能和效率。与传统的二维内存架构相比，三维堆叠 DRAM 架构可释放更高的 I/O 数据带宽，因此更适合集成以内存为中心的处理器。然而，仅仅在三维堆叠内存中集成高精度 ALU 并不能确保设计的优化，因为这样的设计只能实现有限的内存芯片内部带宽利用率和有限的操作并行化。针对这一问题，我们提出了基于三维堆叠内存的内存中处理（PIM）架构--3DL-PIM，该架构将多个基于查找表（LUT）的低脚本处理单元（PE）置于内存库中，通过最大限度地利用数据带宽来实现高并行计算性能。PE 不依赖于传统的基于逻辑的 ALU，而是由一组可编程 LUT 组成，因此可以通过即时编程来执行各种逻辑/算术运算。我们的模拟结果表明，与最先进的基于内存的三维堆叠加速器相比，3DL-PIM 的处理性能最多可提高 2.6 倍，而面积效率却提高了 2.65 倍。
{"title":"3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications","authors":"Purab Ranjan Sutradhar;Sathwika Bavikadi;Sai Manoj Pudukotai Dinakarrao;Mark A. Indovina;Amlan Ganguly","doi":"10.1109/TETC.2023.3293140","DOIUrl":"10.1109/TETC.2023.3293140","url":null,"abstract":"Memory-centric computing systems have demonstrated superior performance and efficiency in memory-intensive applications compared to state-of-the-art CPUs and GPUs. 3-D stacked DRAM architectures unlock higher I/O data bandwidth than the traditional 2-D memory architecture and therefore are better suited for incorporating memory-centric processors. However, merely integrating high-precision ALUs in the 3-D stacked memory does not ensure an optimized design since such a design can only achieve a limited utilization of the internal bandwidth of a memory chip and limited operational parallelization. To address this, we propose 3DL-PIM, a 3-D stacked memory-based Processing in Memory (PIM) architecture that locates a plurality of Look-up Table (LUT)-based low-footprint Processing Elements (PE) within the memory banks in order to achieve high parallel computing performance by maximizing data-bandwidth utilization. Instead of relying on the traditional logic-based ALUs, the PEs are formed by clustering a group of programmable LUTs and therefore can be programmed on-the-fly to perform various logic/arithmetic operations. Our simulations show that 3DL-PIM can achieve respectively up to 2.6× higher processing performance at 2.65× higher area efficiency compared to a state-of-the-art 3-D stacked memory-based accelerator.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-11DOI: 10.1109/TETC.2023.3292866
Di Wu;Yi He;Xin Luo
A High-dimensional and s parse (HiDS) matrix is frequently encountered in Big Data-related applications such as e-commerce systems or wireless sensor networks. It is of great significance to perform highly accurate representation learning on an HiDS matrix due to the great desires of extracting latent knowledge from it. L atent f actor a nalysis (LFA), which represents an HiDS matrix by learning the low-rank embeddings based on its observed entries only, is one of the most effective and efficient approaches to this issue. However, most existing LFA-based models directly perform such embeddings on an HiDS matrix without exploiting its hidden graph structures, resulting in accuracy loss. To aid this issue, this paper proposes a g raph-incorporated l atent f actor a nalysis (GLFA) model. It adopts two-fold ideas: 1) a graph is constructed for identifying the hidden h igh- o rder i nteraction (HOI) among nodes described by an HiDS matrix, and 2) a recurrent LFA structure is carefully designed with the incorporation of HOI, thereby improving the representation learning ability of a resultant model. Experimental results on three real-world datasets demonstrate that GLFA outperforms six state-of-the-art models in predicting the missing data of an HiDS matrix, which evidently supports its strong representation learning ability to HiDS data.
{"title":"A Graph-Incorporated Latent Factor Analysis Model for High-Dimensional and Sparse Data","authors":"Di Wu;Yi He;Xin Luo","doi":"10.1109/TETC.2023.3292866","DOIUrl":"10.1109/TETC.2023.3292866","url":null,"abstract":"A High-dimensional and \u0000<underline>s</u>\u0000parse (HiDS) matrix is frequently encountered in Big Data-related applications such as e-commerce systems or wireless sensor networks. It is of great significance to perform highly accurate representation learning on an HiDS matrix due to the great desires of extracting latent knowledge from it. \u0000<underline>L</u>\u0000atent \u0000<underline>f</u>\u0000actor \u0000<underline>a</u>\u0000nalysis (LFA), which represents an HiDS matrix by learning the low-rank embeddings based on its observed entries only, is one of the most effective and efficient approaches to this issue. However, most existing LFA-based models directly perform such embeddings on an HiDS matrix without exploiting its hidden graph structures, resulting in accuracy loss. To aid this issue, this paper proposes a \u0000<underline>g</u>\u0000raph-incorporated \u0000<underline>l</u>\u0000atent \u0000<underline>f</u>\u0000actor \u0000<underline>a</u>\u0000nalysis (GLFA) model. It adopts two-fold ideas: 1) a graph is constructed for identifying the hidden \u0000<underline>h</u>\u0000igh-\u0000<underline>o</u>\u0000rder \u0000<underline>i</u>\u0000nteraction (HOI) among nodes described by an HiDS matrix, and 2) a recurrent LFA structure is carefully designed with the incorporation of HOI, thereby improving the representation learning ability of a resultant model. Experimental results on three real-world datasets demonstrate that GLFA outperforms six state-of-the-art models in predicting the missing data of an HiDS matrix, which evidently supports its strong representation learning ability to HiDS data.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-11DOI: 10.1109/TETC.2023.3292251
Shaahin Angizi;Sepehr Tabrizchi;David Z. Pan;Arman Roohi
This work proposes a Processing-In-Sensor Accelerator, namely PISA, as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing in AI devices. PISA intrinsically implements a coarse-grained convolution operation in Binarized-Weight Neural Networks (BWNNs) leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. This remarkably reduces the power consumption of data conversion and transmission to an off-chip processor. The design is completed with a bit-wise near-sensor in-memory computing unit to process the remaining network layers. Once the object is detected, PISA switches to typical sensing mode to capture the image for a fine-grained convolution using only a near-sensor processing unit. Our circuit-to-application co-simulation results on a BWNN acceleration demonstrate minor accuracy degradation on various image datasets in coarse-grained evaluation compared to baseline BWNN models, while PISA achieves a frame rate of 1000 and efficiency of $sim$ 1.74 TOp/s/W. Lastly, PISA substantially reduces data conversion and transmission energy by $sim$ 84% compared to a baseline.
{"title":"PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems","authors":"Shaahin Angizi;Sepehr Tabrizchi;David Z. Pan;Arman Roohi","doi":"10.1109/TETC.2023.3292251","DOIUrl":"10.1109/TETC.2023.3292251","url":null,"abstract":"This work proposes a Processing-In-Sensor Accelerator, namely PISA, as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing in AI devices. PISA intrinsically implements a coarse-grained convolution operation in Binarized-Weight Neural Networks (BWNNs) leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. This remarkably reduces the power consumption of data conversion and transmission to an off-chip processor. The design is completed with a bit-wise near-sensor in-memory computing unit to process the remaining network layers. Once the object is detected, PISA switches to typical sensing mode to capture the image for a fine-grained convolution using only a near-sensor processing unit. Our circuit-to-application co-simulation results on a BWNN acceleration demonstrate minor accuracy degradation on various image datasets in coarse-grained evaluation compared to baseline BWNN models, while PISA achieves a frame rate of 1000 and efficiency of \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u0000 1.74 TOp/s/W. Lastly, PISA substantially reduces data conversion and transmission energy by \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u0000 84% compared to a baseline.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-11DOI: 10.1109/TETC.2023.3292924
Yu-Wei Chang;Hong-Yen Chen;Chansu Han;Tomohiro Morikawa;Takeshi Takahashi;Tsung-Nan Lin
5G networks with the vast number of devices pose security threats. Manual analysis of such extensive security data is complex. Dark-NMF can detect malware activities by monitoring unused IP address space, i.e., the darknet. However, the challenges of cooperative training for Dark-NMF are immense computational complexity with Big Data, communication overhead, and privacy concern with darknet sensor IP addresses. Darknet sensors can observe multivariate time series of packets from the same hosts, represented as intersecting columns in different data matrices. Previous works do not consider intersecting columns, losing a host's semantics because they do not aggregate the host's time series. To solve these problems, we proposed a federated IoT malware detection NMF for intersecting source hosts (FINISH) algorithm for offloading computing tasks to 5G multiaccess edge computing (MEC). The experiments show that FINISH is scalable to a data size with a shorter computational time and has a lower false positive detection performance than Dark-NMF. The comparison results demonstrate that FINISH has better computation and communication efficiency than related works and a short communication time, taking only 1/10 the execution time in a simulated 5G MEC. The experimental results can provide substantial insights into developing federated cybersecurity in the future.
拥有大量设备的 5G 网络会带来安全威胁。对如此广泛的安全数据进行人工分析非常复杂。Dark-NMF 可以通过监控未使用的 IP 地址空间（即暗网）来检测恶意软件活动。然而，Dark-NMF 在合作训练方面面临的挑战是大数据带来的巨大计算复杂性、通信开销以及暗网传感器 IP 地址带来的隐私问题。暗网传感器可以观察到来自同一主机的多变量时间序列数据包，这些数据包在不同的数据矩阵中表现为交叉列。以前的工作没有考虑到相交列，从而失去了主机的语义，因为它们没有汇总主机的时间序列。为了解决这些问题，我们提出了一种联合物联网恶意软件检测 NMF for intersecting source hosts（FINISH）算法，用于将计算任务卸载到 5G 多接入边缘计算（MEC）。实验表明，与Dark-NMF相比，FINISH可扩展到更大的数据规模，计算时间更短，误报检测性能更低。对比结果表明，与相关研究相比，FINISH 的计算和通信效率更高，通信时间更短，在模拟的 5G MEC 中仅需 1/10 的执行时间。实验结果可为未来联盟网络安全的发展提供重要启示。
{"title":"FINISH: Efficient and Scalable NMF-Based Federated Learning for Detecting Malware Activities","authors":"Yu-Wei Chang;Hong-Yen Chen;Chansu Han;Tomohiro Morikawa;Takeshi Takahashi;Tsung-Nan Lin","doi":"10.1109/TETC.2023.3292924","DOIUrl":"10.1109/TETC.2023.3292924","url":null,"abstract":"5G networks with the vast number of devices pose security threats. Manual analysis of such extensive security data is complex. Dark-NMF can detect malware activities by monitoring unused IP address space, i.e., the darknet. However, the challenges of cooperative training for Dark-NMF are immense computational complexity with Big Data, communication overhead, and privacy concern with darknet sensor IP addresses. Darknet sensors can observe multivariate time series of packets from the same hosts, represented as intersecting columns in different data matrices. Previous works do not consider intersecting columns, losing a host's semantics because they do not aggregate the host's time series. To solve these problems, we proposed a federated IoT malware detection NMF for intersecting source hosts (FINISH) algorithm for offloading computing tasks to 5G multiaccess edge computing (MEC). The experiments show that FINISH is scalable to a data size with a shorter computational time and has a lower false positive detection performance than Dark-NMF. The comparison results demonstrate that FINISH has better computation and communication efficiency than related works and a short communication time, taking only 1/10 the execution time in a simulated 5G MEC. The experimental results can provide substantial insights into developing federated cybersecurity in the future.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":null,"pages":null},"PeriodicalIF":5.9,"publicationDate":"2023-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62528873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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